From 6579905088dc8f3828140978e5a5a79612e4f255 Mon Sep 17 00:00:00 2001 From: Raphael Coeffic Date: Sat, 1 Jun 2024 03:45:40 +0200 Subject: [PATCH] chore(hal): remove StdPeriph (#5023) Co-authored-by: raphaelcoeffic <1050031+raphaelcoeffic@users.noreply.github.com> Co-authored-by: Malte Langermann Co-authored-by: 3djc <3djc@gh.com> Co-authored-by: Richard Li --- .../boards/generic_stm32/analog_inputs.cpp | 11 +- radio/src/boards/generic_stm32/aux_ports.cpp | 49 +- radio/src/boards/generic_stm32/bor_level.cpp | 29 +- .../src/boards/generic_stm32/module_ports.cpp | 147 +- radio/src/boards/generic_stm32/rgb_leds.cpp | 7 +- .../src/boards/generic_stm32/sport_update.cpp | 14 +- .../boards/generic_stm32/trainer_ports.cpp | 27 +- radio/src/cli.cpp | 20 +- radio/src/hal/gpio.h | 52 + radio/src/lv_conf.h | 30 +- radio/src/main.cpp | 25 +- radio/src/opentx.cpp | 8 +- .../targets/common/arm/stm32/CMakeLists.txt | 1 + .../common/arm/stm32/audio_dac_driver.cpp | 65 +- .../common/arm/stm32/bluetooth_driver.cpp | 31 +- .../targets/common/arm/stm32/board_common.h | 41 +- .../arm/stm32/bootloader/CMakeLists.txt | 2 +- .../common/arm/stm32/bootloader/boot.cpp | 18 +- .../common/arm/stm32/delays_driver.cpp | 5 + .../targets/common/arm/stm32/diskio_sdio.cpp | 4 +- .../common/arm/stm32/f2/CMakeLists.txt | 9 +- .../common/arm/stm32/f2/system_stm32f2xx.c | 5 +- .../common/arm/stm32/f4/CMakeLists.txt | 15 +- .../common/arm/stm32/f4/system_stm32f4xx.c | 10 +- .../targets/common/arm/stm32/flash_driver.cpp | 20 +- .../common/arm/stm32/flysky_gimbal_driver.cpp | 6 +- .../common/arm/stm32/heartbeat_driver.cpp | 24 +- .../targets/common/arm/stm32/pwr_driver.cpp | 79 +- .../arm/stm32/rotary_encoder_driver.cpp | 4 +- .../targets/common/arm/stm32/sdram_driver.cpp | 274 + .../common/arm/stm32/stm32_exti_driver.cpp | 4 + .../targets/common/arm/stm32/stm32_gpio.cpp | 170 + .../src/targets/common/arm/stm32/stm32_gpio.h | 74 + .../common/arm/stm32/stm32_gpio_driver.cpp | 1 + .../common/arm/stm32/stm32_gpio_driver.h | 2 +- .../targets/common/arm/stm32/stm32_hal_ll.h | 1 + .../common/arm/stm32/stm32_pulse_driver.cpp | 20 +- .../common/arm/stm32/stm32_pulse_driver.h | 4 +- .../arm/stm32/stm32_softserial_driver.cpp | 50 +- .../arm/stm32/stm32_softserial_driver.h | 7 +- .../targets/common/arm/stm32/stm32_timer.cpp | 38 +- .../common/arm/stm32/stm32_usart_driver.cpp | 75 +- .../common/arm/stm32/stm32_usart_driver.h | 5 +- .../common/arm/stm32/stm32f4xx_hal_conf.h | 4 +- .../targets/common/arm/stm32/usb_driver.cpp | 37 +- .../src/targets/common/arm/stm32/vs1053b.cpp | 57 +- radio/src/targets/horus/CMakeLists.txt | 2 +- radio/src/targets/horus/backlight_driver.cpp | 25 +- radio/src/targets/horus/board.cpp | 50 +- radio/src/targets/horus/board.h | 16 +- radio/src/targets/horus/hal.h | 419 +- radio/src/targets/horus/haptic_driver.cpp | 16 +- radio/src/targets/horus/lcd_driver.cpp | 92 +- radio/src/targets/horus/led_driver.cpp | 53 +- radio/src/targets/horus/sdram_driver.c | 467 - radio/src/targets/horus/tp_gt911.cpp | 77 +- .../src/targets/horus/usb_charger_driver.cpp | 18 +- radio/src/targets/nv14/CMakeLists.txt | 2 +- radio/src/targets/nv14/backlight_driver.cpp | 26 +- radio/src/targets/nv14/battery_driver.cpp | 14 +- radio/src/targets/nv14/battery_driver.h | 13 +- radio/src/targets/nv14/board.cpp | 70 +- radio/src/targets/nv14/board.h | 19 +- .../src/targets/nv14/bootloader/boot_menu.cpp | 11 +- radio/src/targets/nv14/hal.h | 233 +- radio/src/targets/nv14/haptic_driver.cpp | 16 +- radio/src/targets/nv14/lcd_driver.cpp | 126 +- radio/src/targets/nv14/lcd_driver.h | 30 +- radio/src/targets/nv14/sdram_driver.c | 257 - radio/src/targets/nv14/touch_driver.cpp | 51 +- radio/src/targets/pl18/CMakeLists.txt | 2 +- radio/src/targets/pl18/backlight_driver.cpp | 27 +- radio/src/targets/pl18/battery_driver.cpp | 33 +- radio/src/targets/pl18/battery_driver.h | 23 +- radio/src/targets/pl18/board.cpp | 43 +- radio/src/targets/pl18/board.h | 14 +- radio/src/targets/pl18/extmodule_helper.cpp | 49 - radio/src/targets/pl18/hal.h | 160 +- radio/src/targets/pl18/haptic_driver.cpp | 16 +- radio/src/targets/pl18/lcd_driver.cpp | 165 +- radio/src/targets/pl18/lcd_driver.h | 27 +- radio/src/targets/pl18/sdram_driver.c | 257 - radio/src/targets/pl18/touch_driver.cpp | 50 +- radio/src/targets/simu/simpgmspace.cpp | 5 +- radio/src/targets/taranis/CMakeLists.txt | 2 +- .../src/targets/taranis/backlight_driver.cpp | 52 +- radio/src/targets/taranis/board.cpp | 92 +- radio/src/targets/taranis/board.h | 6 +- radio/src/targets/taranis/dwt.h | 2 + radio/src/targets/taranis/hal.h | 1089 +- radio/src/targets/taranis/haptic_driver.cpp | 27 +- radio/src/targets/taranis/lcd_driver_aspi.cpp | 54 +- radio/src/targets/taranis/lcd_driver_spi.cpp | 43 +- radio/src/targets/taranis/led_driver.cpp | 56 +- radio/src/targets/taranis/top_lcd_driver.cpp | 38 +- .../targets/taranis/usb_charger_driver.cpp | 17 +- .../Device/ST/STM32F2xx/Include/stm32f2xx.h | 6967 --------- .../ST/STM32F2xx/Include/system_stm32f2xx.h | 105 - .../CMSIS/Include/arm_common_tables.h | 35 - .../Libraries/CMSIS/Include/arm_math.h | 7051 --------- .../Libraries/CMSIS/Include/core_cm0.h | 665 - .../Libraries/CMSIS/Include/core_cm3.h | 1240 -- .../Libraries/CMSIS/Include/core_cm4.h | 1378 -- .../Libraries/CMSIS/Include/core_cm4_simd.h | 701 - .../Libraries/CMSIS/Include/core_cmFunc.h | 609 - .../Libraries/CMSIS/Include/core_cmInstr.h | 585 - .../STM32F2xx_StdPeriph_Driver/inc/misc.h | 178 - .../inc/stm32f2xx_adc.h | 649 - .../inc/stm32f2xx_can.h | 644 - .../inc/stm32f2xx_crc.h | 83 - .../inc/stm32f2xx_cryp.h | 344 - .../inc/stm32f2xx_dac.h | 304 - .../inc/stm32f2xx_dbgmcu.h | 109 - .../inc/stm32f2xx_dcmi.h | 312 - .../inc/stm32f2xx_dma.h | 609 - .../inc/stm32f2xx_exti.h | 183 - .../inc/stm32f2xx_flash.h | 340 - .../inc/stm32f2xx_fsmc.h | 675 - .../inc/stm32f2xx_gpio.h | 411 - .../inc/stm32f2xx_hash.h | 250 - .../inc/stm32f2xx_i2c.h | 698 - .../inc/stm32f2xx_iwdg.h | 131 - .../inc/stm32f2xx_pwr.h | 166 - .../inc/stm32f2xx_rcc.h | 515 - .../inc/stm32f2xx_rng.h | 120 - .../inc/stm32f2xx_rtc.h | 650 - .../inc/stm32f2xx_sdio.h | 536 - .../inc/stm32f2xx_spi.h | 526 - .../inc/stm32f2xx_syscfg.h | 179 - .../inc/stm32f2xx_tim.h | 1150 -- .../inc/stm32f2xx_usart.h | 429 - .../inc/stm32f2xx_wwdg.h | 111 - .../STM32F2xx_StdPeriph_Driver/src/misc.c | 249 - .../src/stm32f2xx_adc.c | 1748 --- .../src/stm32f2xx_can.c | 1704 --- .../src/stm32f2xx_crc.c | 133 - .../src/stm32f2xx_cryp.c | 856 -- .../src/stm32f2xx_cryp_aes.c | 644 - .../src/stm32f2xx_cryp_des.c | 297 - .../src/stm32f2xx_cryp_tdes.c | 314 - .../src/stm32f2xx_dac.c | 707 - .../src/stm32f2xx_dbgmcu.c | 180 - .../src/stm32f2xx_dcmi.c | 540 - .../src/stm32f2xx_dma.c | 1289 -- .../src/stm32f2xx_exti.c | 312 - .../src/stm32f2xx_flash.c | 1060 -- .../src/stm32f2xx_fsmc.c | 987 -- .../src/stm32f2xx_gpio.c | 566 - .../src/stm32f2xx_hash.c | 706 - .../src/stm32f2xx_hash_md5.c | 320 - .../src/stm32f2xx_hash_sha1.c | 323 - .../src/stm32f2xx_i2c.c | 1401 -- .../src/stm32f2xx_iwdg.c | 269 - .../src/stm32f2xx_pwr.c | 620 - .../src/stm32f2xx_rcc.c | 1817 --- .../src/stm32f2xx_rng.c | 405 - .../src/stm32f2xx_rtc.c | 2244 --- .../src/stm32f2xx_sdio.c | 1010 -- .../src/stm32f2xx_spi.c | 1183 -- .../src/stm32f2xx_syscfg.c | 210 - .../src/stm32f2xx_tim.c | 3358 ----- .../src/stm32f2xx_usart.c | 1469 -- .../src/stm32f2xx_wwdg.c | 309 - .../Device/ST/STM32F4xx/Include/stm32f4xx.h | 12068 ---------------- .../ST/STM32F4xx/Include/system_stm32f4xx.h | 105 - .../CMSIS/Include/arm_common_tables.h | 136 - .../CMSIS/Include/arm_const_structs.h | 79 - .../Libraries/CMSIS/Include/arm_math.h | 7556 ---------- .../Libraries/CMSIS/Include/core_cm0.h | 740 - .../Libraries/CMSIS/Include/core_cm0plus.h | 854 -- .../Libraries/CMSIS/Include/core_cm3.h | 1693 --- .../Libraries/CMSIS/Include/core_cm4.h | 1858 --- .../Libraries/CMSIS/Include/core_cm4_simd.h | 673 - .../Libraries/CMSIS/Include/core_cm7.h | 2397 --- .../Libraries/CMSIS/Include/core_cmFunc.h | 664 - .../Libraries/CMSIS/Include/core_cmInstr.h | 916 -- .../Libraries/CMSIS/Include/core_cmSimd.h | 697 - .../Libraries/CMSIS/Include/core_sc000.h | 864 -- .../Libraries/CMSIS/Include/core_sc300.h | 1675 --- .../STM32F4xx_StdPeriph_Driver/inc/misc.h | 178 - .../inc/stm32f4xx_adc.h | 656 - .../inc/stm32f4xx_can.h | 657 - .../inc/stm32f4xx_crc.h | 83 - .../inc/stm32f4xx_cryp.h | 384 - .../inc/stm32f4xx_dac.h | 304 - .../inc/stm32f4xx_dbgmcu.h | 109 - .../inc/stm32f4xx_dcmi.h | 312 - .../inc/stm32f4xx_dma.h | 609 - .../inc/stm32f4xx_dma2d.h | 475 - .../inc/stm32f4xx_exti.h | 185 - .../inc/stm32f4xx_flash.h | 497 - .../inc/stm32f4xx_flash_ramfunc.h | 103 - .../inc/stm32f4xx_fmc.h | 1143 -- .../inc/stm32f4xx_fsmc.h | 675 - .../inc/stm32f4xx_gpio.h | 592 - .../inc/stm32f4xx_hash.h | 257 - .../inc/stm32f4xx_i2c.h | 709 - .../inc/stm32f4xx_iwdg.h | 131 - .../inc/stm32f4xx_ltdc.h | 503 - .../inc/stm32f4xx_pwr.h | 245 - .../inc/stm32f4xx_rcc.h | 1066 -- .../inc/stm32f4xx_rng.h | 121 - .../inc/stm32f4xx_rtc.h | 888 -- .../inc/stm32f4xx_sai.h | 649 - .../inc/stm32f4xx_sdio.h | 536 - .../inc/stm32f4xx_spi.h | 549 - .../inc/stm32f4xx_syscfg.h | 350 - .../inc/stm32f4xx_tim.h | 1150 -- .../inc/stm32f4xx_usart.h | 433 - .../inc/stm32f4xx_wwdg.h | 111 - .../STM32F4xx_StdPeriph_Driver/src/misc.c | 249 - .../src/stm32f4xx_adc.c | 1745 --- .../src/stm32f4xx_can.c | 1856 --- .../src/stm32f4xx_crc.c | 133 - .../src/stm32f4xx_cryp.c | 934 -- .../src/stm32f4xx_cryp_aes.c | 1707 --- .../src/stm32f4xx_cryp_des.c | 312 - .../src/stm32f4xx_cryp_tdes.c | 328 - .../src/stm32f4xx_dac.c | 714 - .../src/stm32f4xx_dbgmcu.c | 180 - .../src/stm32f4xx_dcmi.c | 538 - .../src/stm32f4xx_dma.c | 1301 -- .../src/stm32f4xx_dma2d.c | 784 - .../src/stm32f4xx_exti.c | 312 - .../src/stm32f4xx_flash.c | 1619 --- .../src/stm32f4xx_flash_ramfunc.c | 158 - .../src/stm32f4xx_fmc.c | 1506 -- .../src/stm32f4xx_fsmc.c | 1100 -- .../src/stm32f4xx_gpio.c | 611 - .../src/stm32f4xx_hash.c | 726 - .../src/stm32f4xx_hash_md5.c | 320 - .../src/stm32f4xx_hash_sha1.c | 323 - .../src/stm32f4xx_i2c.c | 1462 -- .../src/stm32f4xx_iwdg.c | 266 - .../src/stm32f4xx_ltdc.c | 1110 -- .../src/stm32f4xx_pwr.c | 1053 -- .../src/stm32f4xx_rcc.c | 3192 ---- .../src/stm32f4xx_rng.c | 406 - .../src/stm32f4xx_rtc.c | 2765 ---- .../src/stm32f4xx_sai.c | 1167 -- .../src/stm32f4xx_sdio.c | 1011 -- .../src/stm32f4xx_spi.c | 1327 -- .../src/stm32f4xx_syscfg.c | 521 - .../src/stm32f4xx_tim.c | 3365 ----- .../src/stm32f4xx_usart.c | 1486 -- .../src/stm32f4xx_wwdg.c | 307 - .../thirdparty/libopenui/src/mainwindow.cpp | 12 +- 247 files changed, 2190 insertions(+), 145252 deletions(-) create mode 100644 radio/src/hal/gpio.h create mode 100644 radio/src/targets/common/arm/stm32/sdram_driver.cpp create mode 100644 radio/src/targets/common/arm/stm32/stm32_gpio.cpp create mode 100644 radio/src/targets/common/arm/stm32/stm32_gpio.h delete mode 100644 radio/src/targets/horus/sdram_driver.c delete mode 100644 radio/src/targets/nv14/sdram_driver.c delete mode 100644 radio/src/targets/pl18/extmodule_helper.cpp delete mode 100644 radio/src/targets/pl18/sdram_driver.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_des.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_tdes.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dac.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_sha1.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_i2c.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c delete mode 100644 radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h delete mode 100755 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h delete mode 100755 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_tdes.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dac.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c delete mode 100644 radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c diff --git a/radio/src/boards/generic_stm32/analog_inputs.cpp b/radio/src/boards/generic_stm32/analog_inputs.cpp index bbcbc7eda..e7c3cb74e 100644 --- a/radio/src/boards/generic_stm32/analog_inputs.cpp +++ b/radio/src/boards/generic_stm32/analog_inputs.cpp @@ -89,13 +89,14 @@ const etx_hal_adc_driver_t _adc_driver = { }; #if defined(PWM_STICKS) +#include "stm32_gpio.h" static const stick_pwm_timer_t _sticks_timer = { - PWM_GPIO, - PWM_GPIOA_PINS, - PWM_GPIO_AF, - PWM_TIMER, - PWM_IRQn, + .GPIOx = PWM_GPIO, + .GPIO_Pin = PWM_GPIOA_PINS, + .GPIO_Alternate = PWM_GPIO_AF, + .TIMx = PWM_TIMER, + .TIM_IRQn = PWM_IRQn, }; #if !defined(PWM_IRQHandler) diff --git a/radio/src/boards/generic_stm32/aux_ports.cpp b/radio/src/boards/generic_stm32/aux_ports.cpp index d730de382..21cd6b4a4 100644 --- a/radio/src/boards/generic_stm32/aux_ports.cpp +++ b/radio/src/boards/generic_stm32/aux_ports.cpp @@ -20,8 +20,11 @@ */ #include "hal/serial_port.h" +#include "hal/gpio.h" + #include "stm32_serial_driver.h" #include "stm32_gpio_driver.h" +#include "stm32_gpio.h" #include "board.h" #include "dataconstants.h" @@ -34,21 +37,10 @@ #endif #if defined(AUX_SERIAL_PWR_GPIO) || defined(AUX2_SERIAL_PWR_GPIO) -static void _aux_pwr(GPIO_TypeDef *GPIOx, uint32_t pin, uint8_t on) +static void _aux_pwr(gpio_t pin, uint8_t on) { - stm32_gpio_enable_clock(GPIOx); - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - pinInit.Pin = pin; - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - pinInit.Pull = LL_GPIO_PULL_UP; - LL_GPIO_Init(GPIOx, &pinInit); - - if (on) { - LL_GPIO_SetOutputPin(GPIOx, pin); - } else { - LL_GPIO_ResetOutputPin(GPIOx, pin); - } + gpio_init(pin, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_write(pin, on); } #endif @@ -56,23 +48,22 @@ static void _aux_pwr(GPIO_TypeDef *GPIOx, uint32_t pin, uint8_t on) #if !defined(AUX_SERIAL_DMA_TX) #define AUX_SERIAL_DMA_TX nullptr - #define AUX_SERIAL_DMA_Stream_TX nullptr - #define AUX_SERIAL_DMA_Stream_TX_LL 0 - #define AUX_SERIAL_DMA_Channel_TX 0 + #define AUX_SERIAL_DMA_TX_STREAM 0 + #define AUX_SERIAL_DMA_TX_CHANNEL 0 #endif static const stm32_usart_t auxUSART = { .USARTx = AUX_SERIAL_USART, - .GPIOx = AUX_SERIAL_GPIO, - .GPIO_Pin = AUX_SERIAL_GPIO_PIN_TX | AUX_SERIAL_GPIO_PIN_RX, + .txGPIO = AUX_SERIAL_TX_GPIO, + .rxGPIO = AUX_SERIAL_RX_GPIO, .IRQn = AUX_SERIAL_USART_IRQn, .IRQ_Prio = 7, // TODO: define constant .txDMA = AUX_SERIAL_DMA_TX, - .txDMA_Stream = AUX_SERIAL_DMA_Stream_TX_LL, - .txDMA_Channel = AUX_SERIAL_DMA_Channel_TX, + .txDMA_Stream = AUX_SERIAL_DMA_TX_STREAM, + .txDMA_Channel = AUX_SERIAL_DMA_TX_CHANNEL, .rxDMA = AUX_SERIAL_DMA_RX, - .rxDMA_Stream = AUX_SERIAL_DMA_Stream_RX_LL, - .rxDMA_Channel = AUX_SERIAL_DMA_Channel_RX, + .rxDMA_Stream = AUX_SERIAL_DMA_RX_STREAM, + .rxDMA_Channel = AUX_SERIAL_DMA_RX_CHANNEL, }; DEFINE_STM32_SERIAL_PORT(Aux, auxUSART, AUX_SERIAL_RX_BUFFER, AUX_SERIAL_TX_BUFFER); @@ -80,7 +71,7 @@ DEFINE_STM32_SERIAL_PORT(Aux, auxUSART, AUX_SERIAL_RX_BUFFER, AUX_SERIAL_TX_BUFF #if defined(AUX_SERIAL_PWR_GPIO) void set_aux_pwr(uint8_t on) { - _aux_pwr(AUX_SERIAL_PWR_GPIO, AUX_SERIAL_PWR_GPIO_PIN, on); + _aux_pwr(AUX_SERIAL_PWR_GPIO, on); } #define AUX_PWR_FCT set_aux_pwr #else @@ -102,16 +93,16 @@ const etx_serial_port_t auxSerialPort = { static const stm32_usart_t aux2USART = { .USARTx = AUX2_SERIAL_USART, - .GPIOx = AUX2_SERIAL_GPIO, - .GPIO_Pin = AUX2_SERIAL_GPIO_PIN_TX | AUX2_SERIAL_GPIO_PIN_RX, + .txGPIO = AUX2_SERIAL_TX_GPIO, + .rxGPIO = AUX2_SERIAL_RX_GPIO, .IRQn = AUX2_SERIAL_USART_IRQn, .IRQ_Prio = 7, // TODO: define constant .txDMA = nullptr, .txDMA_Stream = 0, .txDMA_Channel = 0, .rxDMA = AUX2_SERIAL_DMA_RX, - .rxDMA_Stream = AUX2_SERIAL_DMA_Stream_RX_LL, - .rxDMA_Channel = AUX2_SERIAL_DMA_Channel_RX, + .rxDMA_Stream = AUX2_SERIAL_DMA_RX_STREAM, + .rxDMA_Channel = AUX2_SERIAL_DMA_RX_CHANNEL, }; DEFINE_STM32_SERIAL_PORT(Aux2, aux2USART, AUX_SERIAL_RX_BUFFER, AUX_SERIAL_TX_BUFFER); @@ -119,7 +110,7 @@ DEFINE_STM32_SERIAL_PORT(Aux2, aux2USART, AUX_SERIAL_RX_BUFFER, AUX_SERIAL_TX_BU #if defined(AUX2_SERIAL_PWR_GPIO) void set_aux2_pwr(uint8_t on) { - _aux_pwr(AUX2_SERIAL_PWR_GPIO, AUX2_SERIAL_PWR_GPIO_PIN, on); + _aux_pwr(AUX2_SERIAL_PWR_GPIO, on); } #define AUX2_PWR_FCT set_aux2_pwr #else diff --git a/radio/src/boards/generic_stm32/bor_level.cpp b/radio/src/boards/generic_stm32/bor_level.cpp index 39ef4bb8d..356bbf501 100644 --- a/radio/src/boards/generic_stm32/bor_level.cpp +++ b/radio/src/boards/generic_stm32/bor_level.cpp @@ -20,16 +20,33 @@ */ #if defined(STM32F4) -#include "stm32f4xx_flash.h" +#include "stm32_hal.h" void board_set_bor_level() { - if (FLASH_OB_GetBOR() != OB_BOR_LEVEL3) + FLASH_OBProgramInitTypeDef OB; + HAL_FLASHEx_OBGetConfig(&OB); + + if (OB.BORLevel != OB_BOR_LEVEL3) { - FLASH_OB_Unlock(); - FLASH_OB_BORConfig(OB_BOR_LEVEL3); - FLASH_OB_Launch(); - FLASH_OB_Lock(); + + HAL_FLASH_Unlock(); + HAL_FLASH_OB_Unlock(); + + OB.OptionType = OPTIONBYTE_BOR; + OB.BORLevel = OB_BOR_LEVEL3; + + if ( HAL_FLASHEx_OBProgram(&OB) != HAL_OK ) + { + HAL_FLASH_OB_Lock(); + HAL_FLASH_Lock(); + } + + HAL_FLASH_OB_Launch(); + + HAL_FLASH_OB_Lock(); + HAL_FLASH_Lock(); } + } #endif diff --git a/radio/src/boards/generic_stm32/module_ports.cpp b/radio/src/boards/generic_stm32/module_ports.cpp index 104d07dca..84f2b115a 100644 --- a/radio/src/boards/generic_stm32/module_ports.cpp +++ b/radio/src/boards/generic_stm32/module_ports.cpp @@ -19,7 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" #include "hal/module_port.h" + +#include "stm32_gpio.h" #include "stm32_serial_driver.h" #include "stm32_softserial_driver.h" #include "stm32_dma.h" @@ -36,8 +39,8 @@ static const stm32_usart_t intmoduleUSART = { .USARTx = INTMODULE_USART, - .GPIOx = INTMODULE_GPIO, - .GPIO_Pin = INTMODULE_TX_GPIO_PIN | INTMODULE_RX_GPIO_PIN, + .txGPIO = INTMODULE_TX_GPIO, + .rxGPIO = INTMODULE_RX_GPIO, .IRQn = INTMODULE_USART_IRQn, .IRQ_Prio = INTMODULE_USART_IRQ_PRIORITY, #if defined(INTMODULE_DMA) @@ -70,8 +73,7 @@ DEFINE_STM32_SERIAL_PORT(InternalModule, intmoduleUSART, INTMODULE_FIFO_SIZE, 0) static stm32_pulse_dma_tc_cb_t _int_timer_DMA_TC_Callback; static const stm32_pulse_timer_t intmoduleTimer = { - .GPIOx = INTMODULE_TX_GPIO, - .GPIO_Pin = INTMODULE_TX_GPIO_PIN, + .GPIO = INTMODULE_TX_GPIO, .GPIO_Alternate = INTMODULE_TX_GPIO_AF, .TIMx = INTMODULE_TIMER, .TIM_Freq = INTMODULE_TIMER_FREQ, @@ -123,34 +125,21 @@ DEFINE_STM32_SOFTSERIAL_PORT(InternalModule, intmoduleTimer); #define EXTMODULE_USART_IRQ_PRIORITY 6 #if defined(EXTMODULE_TX_INVERT_GPIO) && defined(EXTMODULE_RX_INVERT_GPIO) + +#define HAS_EXTMODULE_INVERTERS + static void _extmod_set_inverted(uint8_t enable) { // In EdgeTX the external module is normally always // inverted, so invert the logic here - if (!enable) { - LL_GPIO_SetOutputPin(EXTMODULE_TX_INVERT_GPIO, - EXTMODULE_TX_INVERT_GPIO_PIN); - LL_GPIO_SetOutputPin(EXTMODULE_RX_INVERT_GPIO, - EXTMODULE_RX_INVERT_GPIO_PIN); - } else { - LL_GPIO_ResetOutputPin(EXTMODULE_TX_INVERT_GPIO, - EXTMODULE_TX_INVERT_GPIO_PIN); - LL_GPIO_ResetOutputPin(EXTMODULE_RX_INVERT_GPIO, - EXTMODULE_RX_INVERT_GPIO_PIN); - } + gpio_write(EXTMODULE_TX_INVERT_GPIO, !enable); + gpio_write(EXTMODULE_RX_INVERT_GPIO, !enable); } static void _extmod_init_inverter() { - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - pinInit.Pin = EXTMODULE_TX_INVERT_GPIO_PIN; - LL_GPIO_Init(EXTMODULE_TX_INVERT_GPIO, &pinInit); - - pinInit.Pin = EXTMODULE_RX_INVERT_GPIO_PIN; - LL_GPIO_Init(EXTMODULE_RX_INVERT_GPIO, &pinInit); + gpio_init(EXTMODULE_TX_INVERT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(EXTMODULE_RX_INVERT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); // this sets the output to idle-low as is // the default in EdgeTX on external module @@ -161,15 +150,15 @@ static void _extmod_init_inverter() static const stm32_usart_t extmoduleUSART = { .USARTx = EXTMODULE_USART, - .GPIOx = EXTMODULE_TX_GPIO, - .GPIO_Pin = EXTMODULE_TX_GPIO_PIN | EXTMODULE_RX_GPIO_PIN, + .txGPIO = EXTMODULE_TX_GPIO, + .rxGPIO = EXTMODULE_RX_GPIO, .IRQn = EXTMODULE_USART_IRQn, .IRQ_Prio = EXTMODULE_USART_IRQ_PRIORITY, .txDMA = EXTMODULE_USART_TX_DMA, - .txDMA_Stream = EXTMODULE_USART_TX_DMA_STREAM_LL, + .txDMA_Stream = EXTMODULE_USART_TX_DMA_STREAM, .txDMA_Channel = EXTMODULE_USART_TX_DMA_CHANNEL, .rxDMA = EXTMODULE_USART_TX_DMA, - .rxDMA_Stream = EXTMODULE_USART_RX_DMA_STREAM_LL, + .rxDMA_Stream = EXTMODULE_USART_RX_DMA_STREAM, .rxDMA_Channel = EXTMODULE_USART_RX_DMA_CHANNEL, .set_input = nullptr, .txDMA_IRQn = (IRQn_Type)0, @@ -182,8 +171,7 @@ DEFINE_STM32_SERIAL_PORT(ExternalModule, extmoduleUSART, INTMODULE_FIFO_SIZE, 0) static const stm32_usart_t sbus_trainer_USART = { .USARTx = TRAINER_MODULE_SBUS_USART, - .GPIOx = TRAINER_MODULE_SBUS_GPIO, - .GPIO_Pin = TRAINER_MODULE_SBUS_GPIO_PIN, + .rxGPIO = TRAINER_MODULE_SBUS_GPIO, .IRQn = (IRQn_Type)-1, .IRQ_Prio = 0, .txDMA = nullptr, @@ -201,15 +189,14 @@ DEFINE_STM32_SERIAL_PORT(SbusTrainer, sbus_trainer_USART, 32, 0); static stm32_pulse_dma_tc_cb_t _ext_timer_DMA_TC_Callback; static const stm32_pulse_timer_t extmoduleTimer = { - .GPIOx = EXTMODULE_TX_GPIO, - .GPIO_Pin = EXTMODULE_TX_GPIO_PIN, + .GPIO = EXTMODULE_TX_GPIO, .GPIO_Alternate = EXTMODULE_TIMER_TX_GPIO_AF, .TIMx = EXTMODULE_TIMER, .TIM_Freq = EXTMODULE_TIMER_FREQ, .TIM_Channel = EXTMODULE_TIMER_Channel, .TIM_IRQn = EXTMODULE_TIMER_IRQn, .DMAx = EXTMODULE_TIMER_DMA, - .DMA_Stream = EXTMODULE_TIMER_DMA_STREAM_LL, + .DMA_Stream = EXTMODULE_TIMER_DMA_STREAM, .DMA_Channel = EXTMODULE_TIMER_DMA_CHANNEL, .DMA_IRQn = EXTMODULE_TIMER_DMA_STREAM_IRQn, .DMA_TC_CallbackPtr = &_ext_timer_DMA_TC_Callback, @@ -220,7 +207,7 @@ static_assert(__STM32_PULSE_IS_TIMER_CHANNEL_SUPPORTED(EXTMODULE_TIMER_Channel), "Unsupported timer channel"); // Make sure the DMA channel is supported -static_assert(__STM32_DMA_IS_STREAM_SUPPORTED(EXTMODULE_TIMER_DMA_STREAM_LL), +static_assert(__STM32_DMA_IS_STREAM_SUPPORTED(EXTMODULE_TIMER_DMA_STREAM), "Unsupported DMA stream"); #if !defined(EXTMODULE_TIMER_DMA_IRQHandler) @@ -249,8 +236,7 @@ static_assert(__IS_TRAINER_TIMER_IN_CHANNEL_SUPPORTED(TRAINER_MODULE_CPPM_TIMER_ "Unsupported trainer timer input channel"); static const stm32_pulse_timer_t trainerModuleTimer = { - .GPIOx = TRAINER_MODULE_CPPM_GPIO, - .GPIO_Pin = TRAINER_MODULE_CPPM_GPIO_PIN, + .GPIO = TRAINER_MODULE_CPPM_GPIO, .GPIO_Alternate = TRAINER_MODULE_CPPM_GPIO_AF, .TIMx = TRAINER_MODULE_CPPM_TIMER, .TIM_Freq = TRAINER_MODULE_CPPM_FREQ, @@ -273,47 +259,34 @@ static const stm32_pulse_timer_t trainerModuleTimer = { static void _set_sport_input(uint8_t enable) { if (TELEMETRY_SET_INPUT) { - if (enable) { - LL_GPIO_SetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - } else { - LL_GPIO_ResetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - } + gpio_write(TELEMETRY_DIR_GPIO, enable); } else { - if (enable) { - LL_GPIO_ResetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - } else { - LL_GPIO_SetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN); - } + gpio_write(TELEMETRY_DIR_GPIO, !enable); } } -#if defined(TELEMETRY_REV_GPIO) +#if defined(TELEMETRY_TX_REV_GPIO) && defined(TELEMETRY_RX_REV_GPIO) + +#define HAS_SPORT_INVERTER + static void _sport_set_inverted(uint8_t enable) { - uint32_t pins = TELEMETRY_TX_REV_GPIO_PIN | TELEMETRY_RX_REV_GPIO_PIN; - if (!enable) { - LL_GPIO_SetOutputPin(TELEMETRY_REV_GPIO, pins); - } else { - LL_GPIO_ResetOutputPin(TELEMETRY_REV_GPIO, pins); - } + gpio_write(TELEMETRY_TX_REV_GPIO, !enable); + gpio_write(TELEMETRY_RX_REV_GPIO, !enable); } static void _sport_init_inverter() { - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = TELEMETRY_TX_REV_GPIO_PIN | TELEMETRY_RX_REV_GPIO_PIN; - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - LL_GPIO_Init(TELEMETRY_REV_GPIO, &pinInit); + gpio_init(TELEMETRY_TX_REV_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TELEMETRY_RX_REV_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); _sport_set_inverted(false); } #endif static const stm32_usart_t sportUSART = { .USARTx = TELEMETRY_USART, - .GPIOx = TELEMETRY_GPIO, - .GPIO_Pin = TELEMETRY_TX_GPIO_PIN | TELEMETRY_RX_GPIO_PIN, + .txGPIO = TELEMETRY_TX_GPIO, + .rxGPIO = TELEMETRY_RX_GPIO, .IRQn = TELEMETRY_USART_IRQn, .IRQ_Prio = TELEMETRY_USART_IRQ_PRIORITY, .txDMA = TELEMETRY_DMA, @@ -336,26 +309,19 @@ DEFINE_STM32_SERIAL_PORT(SportModule, sportUSART, TELEMETRY_FIFO_SIZE, 0); static void _sport_direction_init() { - LL_GPIO_InitTypeDef dirPinInit; - LL_GPIO_StructInit(&dirPinInit); - - dirPinInit.Pin = TELEMETRY_DIR_GPIO_PIN; - dirPinInit.Mode = LL_GPIO_MODE_OUTPUT; - LL_GPIO_Init(TELEMETRY_DIR_GPIO, &dirPinInit); + gpio_init(TELEMETRY_DIR_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); } #if defined(TELEMETRY_TIMER) static const stm32_softserial_rx_port sportSoftRX = { - .GPIOx = TELEMETRY_GPIO, - .GPIO_Pin = TELEMETRY_RX_GPIO_PIN, + .GPIO = TELEMETRY_RX_GPIO, .TIMx = TELEMETRY_TIMER, .TIM_Freq = PERI2_FREQUENCY * TIMER_MULT_APB2, .TIM_IRQn = TELEMETRY_TIMER_IRQn, .EXTI_Port = TELEMETRY_EXTI_PORT, .EXTI_SysLine = TELEMETRY_EXTI_SYS_LINE, .EXTI_Line = TELEMETRY_EXTI_LINE, - .dir_GPIOx = TELEMETRY_DIR_GPIO, - .dir_Pin = TELEMETRY_DIR_GPIO_PIN, + .dir_GPIO = TELEMETRY_DIR_GPIO, .dir_Input = TELEMETRY_SET_INPUT, // re-use S.PORT serial RX buffer .buffer = { SportModule_RXBuffer, TELEMETRY_FIFO_SIZE }, @@ -386,11 +352,7 @@ static void _internal_module_set_bootcmd(uint8_t enable) enable = !enable; } - if (enable) { - LL_GPIO_SetOutputPin(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); - } else { - LL_GPIO_ResetOutputPin(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); - } + gpio_write(INTMODULE_BOOTCMD_GPIO, enable); } #endif @@ -443,14 +405,14 @@ static void _external_module_set_pwr(uint8_t enable) EXTERNAL_MODULE_ON(); #if defined(PCBNV14) if (hardwareOptions.pcbrev == PCBREV_NV14) { - LL_GPIO_ResetOutputPin(EXTMODULE_PWR_FIX_GPIO, EXTMODULE_PWR_FIX_GPIO_PIN); + gpio_clear(EXTMODULE_PWR_FIX_GPIO); } #endif } else { EXTERNAL_MODULE_OFF(); #if defined(PCBNV14) if (hardwareOptions.pcbrev == PCBREV_NV14) { - LL_GPIO_SetOutputPin(EXTMODULE_PWR_FIX_GPIO, EXTMODULE_PWR_FIX_GPIO_PIN); + gpio_set(EXTMODULE_PWR_FIX_GPIO); } #endif } @@ -465,7 +427,7 @@ static const etx_module_port_t _external_ports[] = { .dir_flags = ETX_MOD_DIR_TX_RX | ETX_MOD_FULL_DUPLEX, .drv = { .serial = &STM32SerialDriver }, .hw_def = REF_STM32_SERIAL_PORT(ExternalModule), -#if defined(EXTMODULE_TX_INVERT_GPIO) && defined(EXTMODULE_RX_INVERT_GPIO) +#if defined(HAS_EXTMODULE_INVERTERS) .set_inverted = _extmod_set_inverted, #else .set_inverted = nullptr, @@ -479,7 +441,7 @@ static const etx_module_port_t _external_ports[] = { .dir_flags = ETX_MOD_DIR_TX, .drv = { .timer = &STM32ModuleTimerDriver }, .hw_def = (void*)&extmoduleTimer, -#if defined(EXTMODULE_TX_INVERT_GPIO) && defined(EXTMODULE_RX_INVERT_GPIO) +#if defined(HAS_EXTMODULE_INVERTERS) .set_inverted = _extmod_set_inverted, #else .set_inverted = nullptr, @@ -492,7 +454,7 @@ static const etx_module_port_t _external_ports[] = { .dir_flags = ETX_MOD_DIR_TX, .drv = { .serial = &STM32SoftSerialTxDriver }, .hw_def = REF_STM32_SOFTSERIAL_PORT(ExternalModule), -#if defined(EXTMODULE_TX_INVERT_GPIO) && defined(EXTMODULE_RX_INVERT_GPIO) +#if defined(HAS_EXTMODULE_INVERTERS) .set_inverted = _extmod_set_inverted, #else .set_inverted = nullptr, @@ -527,7 +489,7 @@ static const etx_module_port_t _external_ports[] = { .dir_flags = ETX_MOD_DIR_TX | ETX_MOD_DIR_RX, .drv = { .serial = &STM32SerialDriver }, .hw_def = REF_STM32_SERIAL_PORT(SportModule), -#if defined(TELEMETRY_REV_GPIO) +#if defined(HAS_SPORT_INVERTER) .set_inverted = _sport_set_inverted, #else .set_inverted = nullptr, @@ -560,11 +522,7 @@ static const etx_module_t _external_module = { // from board.cpp void _sport_set_pwr(uint8_t enabled) { - if (enabled) { - LL_GPIO_SetOutputPin(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); - } else { - LL_GPIO_ResetOutputPin(SPORT_UPDATE_PWR_GPIO, SPORT_UPDATE_PWR_GPIO_PIN); - } + gpio_write(SPORT_UPDATE_PWR_GPIO, enabled); } #if defined(RADIO_X7) @@ -598,26 +556,19 @@ void boardInitModulePorts() sportUpdateInit(); #endif -#if defined(TELEMETRY_REV_GPIO) +#if defined(HAS_SPORT_INVERTER) _sport_init_inverter(); #endif -#if defined(EXTMODULE_TX_INVERT_GPIO) && defined(EXTMODULE_RX_INVERT_GPIO) +#if defined(HAS_EXTMODULE_INVERTERS) _extmod_init_inverter(); #endif #if defined(PCBNV14) if (hardwareOptions.pcbrev == PCBREV_NV14) { - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - pinInit.Pin = EXTMODULE_PWR_FIX_GPIO_PIN; - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - // pin must be pulled to V+ (voltage of board - VCC is not enough to fully close transistor) // for additional transistor to ensuring module is completely disabled - pinInit.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; - - LL_GPIO_SetOutputPin(EXTMODULE_PWR_FIX_GPIO, EXTMODULE_PWR_FIX_GPIO_PIN); - LL_GPIO_Init(EXTMODULE_PWR_FIX_GPIO, &pinInit); + gpio_init(EXTMODULE_PWR_FIX_GPIO, GPIO_OD, GPIO_PIN_SPEED_LOW); + gpio_set(EXTMODULE_PWR_FIX_GPIO); } #endif } diff --git a/radio/src/boards/generic_stm32/rgb_leds.cpp b/radio/src/boards/generic_stm32/rgb_leds.cpp index 54fee303d..8615b803d 100644 --- a/radio/src/boards/generic_stm32/rgb_leds.cpp +++ b/radio/src/boards/generic_stm32/rgb_leds.cpp @@ -28,6 +28,8 @@ #include "stm32_ws2812.h" #include "stm32_dma.h" +#include "stm32_gpio.h" +#include "hal/gpio.h" #if !defined(SIMU) #include @@ -81,9 +83,8 @@ void rgbLedStop() } const stm32_pulse_timer_t _led_timer = { - .GPIOx = LED_STRIP_GPIO, - .GPIO_Pin = LED_STRIP_GPIO_PIN_DATA, - .GPIO_Alternate = LED_STRIP_GPIO_PIN_AF, + .GPIO = LED_STRIP_GPIO, + .GPIO_Alternate = LED_STRIP_GPIO_AF, .TIMx = LED_STRIP_TIMER, .TIM_Freq = LED_STRIP_TIMER_FREQ, .TIM_Channel = LED_STRIP_TIMER_CHANNEL, diff --git a/radio/src/boards/generic_stm32/sport_update.cpp b/radio/src/boards/generic_stm32/sport_update.cpp index 1b5617400..d0e870756 100644 --- a/radio/src/boards/generic_stm32/sport_update.cpp +++ b/radio/src/boards/generic_stm32/sport_update.cpp @@ -19,10 +19,14 @@ * GNU General Public License for more details. */ -#include "hal.h" #include "stm32_hal_ll.h" +#include "stm32_gpio.h" #include "hal/module_port.h" +#include "hal/gpio.h" + +#include "hal.h" + #include "opentx.h" // g_eeGeneral void sportUpdateInit() @@ -41,13 +45,7 @@ void sportUpdateInit() } #endif - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = SPORT_UPDATE_PWR_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(SPORT_UPDATE_PWR_GPIO, &GPIO_InitStructure); + gpio_init(SPORT_UPDATE_PWR_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif } diff --git a/radio/src/boards/generic_stm32/trainer_ports.cpp b/radio/src/boards/generic_stm32/trainer_ports.cpp index b7c3fc127..7b8dc6476 100644 --- a/radio/src/boards/generic_stm32/trainer_ports.cpp +++ b/radio/src/boards/generic_stm32/trainer_ports.cpp @@ -21,8 +21,10 @@ #include "stm32_pulse_driver.h" #include "stm32_gpio_driver.h" +#include "stm32_gpio.h" #include "trainer_driver.h" +#include "hal/gpio.h" #include "hal/module_port.h" #include "dataconstants.h" @@ -30,21 +32,14 @@ void board_trainer_init() { -#if defined(TRAINER_DETECT_GPIO_PIN) - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = TRAINER_DETECT_GPIO_PIN; - pinInit.Mode = LL_GPIO_MODE_INPUT; - pinInit.Pull = LL_GPIO_PULL_UP; - stm32_gpio_enable_clock(TRAINER_DETECT_GPIO); - LL_GPIO_Init(TRAINER_DETECT_GPIO, &pinInit); +#if defined(TRAINER_DETECT_GPIO) + gpio_init(TRAINER_DETECT_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); #endif trainer_init(); } -#if defined(TRAINER_GPIO) +#if defined(TRAINER_IN_GPIO) bool trainer_dsc_available() { return true; } @@ -55,8 +50,7 @@ static_assert(__IS_TRAINER_TIMER_IN_CHANNEL_SUPPORTED(TRAINER_IN_TIMER_Channel), "Unsupported trainer timer input channel"); static const stm32_pulse_timer_t trainerOutputTimer = { - .GPIOx = TRAINER_GPIO, - .GPIO_Pin = TRAINER_OUT_GPIO_PIN, + .GPIO = TRAINER_OUT_GPIO, .GPIO_Alternate = TRAINER_GPIO_AF, .TIMx = TRAINER_TIMER, .TIM_Freq = TRAINER_TIMER_FREQ, @@ -75,8 +69,7 @@ void trainer_init_dsc_out() } static const stm32_pulse_timer_t trainerInputTimer = { - .GPIOx = TRAINER_GPIO, - .GPIO_Pin = TRAINER_IN_GPIO_PIN, + .GPIO = TRAINER_IN_GPIO, .GPIO_Alternate = TRAINER_GPIO_AF, .TIMx = TRAINER_TIMER, .TIM_Freq = TRAINER_TIMER_FREQ, @@ -105,14 +98,14 @@ void trainer_stop_dsc() {} bool is_trainer_dsc_connected() { -#if defined(TRAINER_DETECT_GPIO_PIN) - bool set = LL_GPIO_IsInputPinSet(TRAINER_DETECT_GPIO, TRAINER_DETECT_GPIO_PIN); +#if defined(TRAINER_DETECT_GPIO) + bool set = gpio_read(TRAINER_DETECT_GPIO); #if defined(TRAINER_DETECT_INVERTED) return !set; #else return set; #endif -#else // TRAINER_DETECT_GPIO_PIN +#else // TRAINER_DETECT_GPIO return true; #endif } diff --git a/radio/src/cli.cpp b/radio/src/cli.cpp index 717c90cd3..fdfc6372b 100644 --- a/radio/src/cli.cpp +++ b/radio/src/cli.cpp @@ -998,24 +998,24 @@ int cliSet(const char **argv) } cliSerialPrint("%s: rfmod %d power %s", argv[0], module, argv[4]); } -#if defined(INTMODULE_BOOTCMD_GPIO) else if (!strcmp(argv[3], "bootpin")) { int level = 0; if (toInt(argv, 4, &level) < 0) { cliSerialPrint("%s: invalid bootpin argument '%s'", argv[0], argv[4]); return -1; } - if (module == 0) { - if (level) { - GPIO_SetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); - cliSerialPrint("%s: bootpin set", argv[0]); - } else { - GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); - cliSerialPrint("%s: bootpin reset", argv[0]); - } + const auto* mod = modulePortGetModuleDescription(INTERNAL_MODULE); + if (!mod || !mod->set_bootcmd) { + cliSerialPrint("%s: invalid module or has no bootcmd pin", argv[0]); + return -1; + } + mod->set_bootcmd(level); + if (level) { + cliSerialPrint("%s: bootcmd set", argv[0]); + } else { + cliSerialPrint("%s: bootcmd reset", argv[0]); } } -#endif else { if (strlen(argv[2]) == 0) { cliSerialPrint("%s: missing rfmod arguments", argv[0]); diff --git a/radio/src/hal/gpio.h b/radio/src/hal/gpio.h new file mode 100644 index 000000000..4aa8392c2 --- /dev/null +++ b/radio/src/hal/gpio.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#include + +typedef uint32_t gpio_t; + +typedef uint8_t gpio_mode_t; +typedef uint8_t gpio_af_t; +typedef uint8_t gpio_speed_t; + +typedef enum { + GPIO_RISING = 1, + GPIO_FALLING = 2, + GPIO_BOTH = 3 +} gpio_flank_t; + +typedef void (*gpio_cb_t)(); + +void gpio_init(gpio_t pin, gpio_mode_t mode, gpio_speed_t speed); +void gpio_init_af(gpio_t pin, gpio_af_t af, gpio_speed_t speed); +void gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb); +void gpio_init_analog(gpio_t pin); + +void gpio_int_disable(gpio_t pin); + +gpio_mode_t gpio_get_mode(gpio_t pin); +int gpio_read(gpio_t pin); +void gpio_set(gpio_t pin); +void gpio_clear(gpio_t pin); +void gpio_write(gpio_t pin, int value); +void gpio_toggle(gpio_t pin); diff --git a/radio/src/lv_conf.h b/radio/src/lv_conf.h index 4c7931594..24777c146 100644 --- a/radio/src/lv_conf.h +++ b/radio/src/lv_conf.h @@ -173,21 +173,21 @@ /*Must be defined to include path of CMSIS header of target processor e.g. "stm32f769xx.h" or "stm32f429xx.h"*/ #define LV_GPU_DMA2D_CMSIS_INCLUDE "stm32f4xx.h" - #if !defined(DMA2D_NLR_PL_Pos) - #define DMA2D_NLR_PL_Pos 16 - #endif - #if !defined(DMA2D_NLR_NL_Pos) - #define DMA2D_NLR_NL_Pos 0 - #endif - #if !defined(DMA2D_CR_START_Msk) - #define DMA2D_CR_START_Msk DMA2D_CR_START - #endif - #if !defined(DMA2D_FGPFCCR_AM_Pos) - #define DMA2D_FGPFCCR_AM_Pos 16 - #endif - #if !defined(DMA2D_FGPFCCR_ALPHA_Pos) - #define DMA2D_FGPFCCR_ALPHA_Pos 24 - #endif +// #if !defined(DMA2D_NLR_PL_Pos) +// #define DMA2D_NLR_PL_Pos 16 +// #endif +// #if !defined(DMA2D_NLR_NL_Pos) +// #define DMA2D_NLR_NL_Pos 0 +// #endif +// #if !defined(DMA2D_CR_START_Msk) +// #define DMA2D_CR_START_Msk DMA2D_CR_START +// #endif +// #if !defined(DMA2D_FGPFCCR_AM_Pos) +// #define DMA2D_FGPFCCR_AM_Pos 16 +// #endif +// #if !defined(DMA2D_FGPFCCR_ALPHA_Pos) +// #define DMA2D_FGPFCCR_ALPHA_Pos 24 +// #endif #endif /*Use NXP's PXP GPU iMX RTxxx platforms*/ diff --git a/radio/src/main.cpp b/radio/src/main.cpp index 9e4be7b04..c891ebe30 100644 --- a/radio/src/main.cpp +++ b/radio/src/main.cpp @@ -19,12 +19,11 @@ * GNU General Public License for more details. */ -#include "opentx.h" - #include "hal/adc_driver.h" #include "hal/storage.h" #include "hal/abnormal_reboot.h" #include "hal/usb_driver.h" +#include "opentx.h" #if defined(LIBOPENUI) #include "libopenui.h" @@ -203,28 +202,6 @@ void handleUsbConnection() #endif // defined(STM32) && !defined(SIMU) } -#if defined(JACK_DETECT_GPIO) && !defined(SIMU) -bool isJackPlugged() -{ - // debounce - static bool debounced_state = 0; - static bool last_state = 0; - - if (GPIO_ReadInputDataBit(JACK_DETECT_GPIO, JACK_DETECT_GPIO_PIN)) { - if (!last_state) { - debounced_state = false; - } - last_state = false; - } else { - if (last_state) { - debounced_state = true; - } - last_state = true; - } - return debounced_state; -} -#endif - #if defined(PCBXLITES) uint8_t jackState = SPEAKER_ACTIVE; diff --git a/radio/src/opentx.cpp b/radio/src/opentx.cpp index 3f7c73bf3..e39bb4c32 100644 --- a/radio/src/opentx.cpp +++ b/radio/src/opentx.cpp @@ -22,6 +22,8 @@ #if !defined(SIMU) #include "stm32_ws2812.h" #include "boards/generic_stm32/rgb_leds.h" +#include "stm32_hal.h" +#include "stm32_hal_ll.h" #endif #include "opentx.h" @@ -104,9 +106,9 @@ void toggleLatencySwitch() #if defined(PCBHORUS) if (latencyToggleSwitch) - GPIO_ResetBits(EXTMODULE_TX_GPIO, EXTMODULE_TX_GPIO_PIN); + gpio_clear(EXTMODULE_TX_GPIO); else - GPIO_SetBits(EXTMODULE_TX_GPIO, EXTMODULE_TX_GPIO_PIN); + gpio_set(EXTMODULE_TX_GPIO); #else if (latencyToggleSwitch) sportUpdatePowerOn(); @@ -1561,7 +1563,7 @@ int main() #if !defined(SIMU) /* Ensure all priority bits are assigned as preemption priority bits. */ - NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 ); + NVIC_SetPriorityGrouping( NVIC_PRIORITYGROUP_4 ); #endif // G: The WDT remains active after a WDT reset -- at maximum clock speed. So it's diff --git a/radio/src/targets/common/arm/stm32/CMakeLists.txt b/radio/src/targets/common/arm/stm32/CMakeLists.txt index ef70ab3c0..c852cec2f 100644 --- a/radio/src/targets/common/arm/stm32/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/CMakeLists.txt @@ -91,6 +91,7 @@ if(NOT NATIVE_BUILD) ${STM32_DRIVER_DIR}/stm32_i2c_driver.cpp ${STM32_DRIVER_DIR}/stm32_timer.cpp ${STM32_DRIVER_DIR}/stm32_dma.cpp + ${STM32_DRIVER_DIR}/stm32_gpio.cpp ${STM32_DRIVER_DIR}/stm32_spi.cpp ${STM32_DRIVER_DIR}/stm32_adc.cpp ) diff --git a/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp b/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp index 45b2b201e..333fb1dc8 100644 --- a/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp +++ b/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp @@ -19,6 +19,11 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" +#include "stm32_dma.h" + #include "opentx.h" #if !defined(SIMU) @@ -27,7 +32,6 @@ const AudioBuffer * nextBuffer = nullptr; void setSampleRate(uint32_t frequency) { uint32_t timer = (PERI1_FREQUENCY * TIMER_MULT_APB1) / frequency - 1 ; // MCK/8 and 100 000 Hz - AUDIO_TIMER->CR1 &= ~TIM_CR1_CEN ; AUDIO_TIMER->CNT = 0 ; AUDIO_TIMER->ARR = limit(2, timer, 65535) ; @@ -37,38 +41,30 @@ void setSampleRate(uint32_t frequency) // Start TIMER6 at 100000Hz, used for DAC trigger void dacTimerInit() { - AUDIO_TIMER->PSC = 0 ; // Max speed + stm32_timer_enable_clock(AUDIO_TIMER); + AUDIO_TIMER->PSC = 0 ; // Max speed AUDIO_TIMER->ARR = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 100000 - 1 ; // 10 uS, 100 kHz AUDIO_TIMER->CR2 = 0 ; AUDIO_TIMER->CR2 = 0x20 ; AUDIO_TIMER->CR1 = TIM_CR1_CEN ; } -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) static inline void setMutePin(bool enabled) { - if (enabled) { #if defined(INVERTED_MUTE_PIN) - GPIO_ResetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - GPIO_SetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); + enabled = !enabled; #endif - } else { -#if defined(INVERTED_MUTE_PIN) - GPIO_SetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - GPIO_ResetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#endif - } + gpio_write(AUDIO_MUTE_GPIO, enabled); } static inline bool getMutePin(void) { + bool enabled = gpio_read(AUDIO_MUTE_GPIO) ? 1 : 0; #if defined(INVERTED_MUTE_PIN) - return !GPIO_ReadOutputDataBit(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - return GPIO_ReadOutputDataBit(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); + enabled = !enabled; #endif + return enabled; } #endif @@ -76,27 +72,17 @@ static inline bool getMutePin(void) // Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function // So maybe it is automatically done void dacInit() -{ - dacTimerInit(); - - GPIO_InitTypeDef GPIO_InitStructure; - -#if defined(AUDIO_MUTE_GPIO_PIN) - GPIO_InitStructure.GPIO_Pin = AUDIO_MUTE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(AUDIO_MUTE_GPIO, &GPIO_InitStructure); +{ +#if defined(AUDIO_MUTE_GPIO) + // Mute before init anything + gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); setMutePin(true); #endif - GPIO_InitStructure.GPIO_Pin = AUDIO_OUTPUT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(AUDIO_OUTPUT_GPIO, &GPIO_InitStructure); + dacTimerInit(); + + gpio_init_analog(AUDIO_OUTPUT_GPIO); + stm32_dma_enable_clock(AUDIO_DMA); // Chan 7, 16-bit wide, Medium priority, memory increments AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN ; // Disable DMA @@ -108,6 +94,7 @@ void dacInit() AUDIO_DMA_Stream->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ; // AUDIO_DMA_Stream->NDTR = 100 ; + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC1); DAC->DHR12R1 = 2010 ; DAC->SR = DAC_SR_DMAUDR1 ; // Write 1 to clear flag DAC->CR = DAC_CR_TEN1 | DAC_CR_EN1 ; // Enable DAC @@ -117,7 +104,7 @@ void dacInit() NVIC_SetPriority(AUDIO_DMA_Stream_IRQn, 7); } -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) void audioMute() { if (!g_eeGeneral.audioMuteEnable) return; @@ -129,7 +116,7 @@ void audioMute() } else if (now - audioQueue.lastAudioPlayTime > AUDIO_MUTE_DELAY / 10) { // delay expired, we may mute - setMutePin(true); + setMutePin(true); } #else // mute @@ -164,7 +151,7 @@ void audioConsumeCurrentBuffer() if (!nextBuffer) { nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer(); if (nextBuffer) { -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) audioUnmute(); #endif AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA channel @@ -175,7 +162,7 @@ void audioConsumeCurrentBuffer() DAC->SR = DAC_SR_DMAUDR1; // Write 1 to clear flag DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1; // Enable DAC } -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) else { audioMute(); } diff --git a/radio/src/targets/common/arm/stm32/bluetooth_driver.cpp b/radio/src/targets/common/arm/stm32/bluetooth_driver.cpp index 24a363fa6..605765aa2 100644 --- a/radio/src/targets/common/arm/stm32/bluetooth_driver.cpp +++ b/radio/src/targets/common/arm/stm32/bluetooth_driver.cpp @@ -20,7 +20,10 @@ */ #include "bluetooth_driver.h" +#include "hal/gpio.h" + #include "stm32_hal_ll.h" +#include "stm32_gpio.h" #include "board.h" #include "debug.h" @@ -33,8 +36,8 @@ static const stm32_usart_t btUSART = { .USARTx = BT_USART, - .GPIOx = BT_USART_GPIO, - .GPIO_Pin = BT_TX_GPIO_PIN | BT_RX_GPIO_PIN, + .txGPIO = BT_TX_GPIO, + .rxGPIO = BT_RX_GPIO, .IRQn = BT_USART_IRQn, .IRQ_Prio = BT_USART_IRQ_PRIORITY, .txDMA = nullptr, @@ -57,16 +60,8 @@ void* _bt_usart_ctx = nullptr; void bluetoothInit(uint32_t baudrate, bool enable) { -#if defined(BT_EN_GPIO_PIN) - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = BT_EN_GPIO_PIN; - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - pinInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - pinInit.Pull = LL_GPIO_PULL_NO; - - LL_GPIO_Init(BT_EN_GPIO, &pinInit); +#if defined(BT_EN_GPIO) + gpio_init(BT_EN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif #if !defined(BOOT) @@ -85,21 +80,17 @@ void bluetoothInit(uint32_t baudrate, bool enable) } #endif -#if defined(BT_EN_GPIO_PIN) - if (enable) { - LL_GPIO_ResetOutputPin(BT_EN_GPIO, BT_EN_GPIO_PIN); - } else { - LL_GPIO_SetOutputPin(BT_EN_GPIO, BT_EN_GPIO_PIN); - } +#if defined(BT_EN_GPIO) + gpio_write(BT_EN_GPIO, !enable); #endif } #if !defined(BOOT) void bluetoothDisable() { -#if defined(BT_EN_GPIO_PIN) +#if defined(BT_EN_GPIO) // close bluetooth (recent modules will go to bootloader mode) - LL_GPIO_SetOutputPin(BT_EN_GPIO, BT_EN_GPIO_PIN); + gpio_set(BT_EN_GPIO); #endif if (_bt_usart_ctx) { STM32SerialDriver.deinit(_bt_usart_ctx); diff --git a/radio/src/targets/common/arm/stm32/board_common.h b/radio/src/targets/common/arm/stm32/board_common.h index b3d074d5d..36aa38ece 100644 --- a/radio/src/targets/common/arm/stm32/board_common.h +++ b/radio/src/targets/common/arm/stm32/board_common.h @@ -28,58 +28,21 @@ #if !defined(SIMU) && !defined(BACKUP) #if defined(STM32F4) #include "stm32f4xx.h" - #include "stm32f4xx_rcc.h" - #include "stm32f4xx_syscfg.h" - #include "stm32f4xx_gpio.h" - #include "stm32f4xx_exti.h" - #include "stm32f4xx_tim.h" - #include "stm32f4xx_spi.h" - #include "stm32f4xx_pwr.h" - #include "stm32f4xx_dma.h" - #include "stm32f4xx_dbgmcu.h" - #include "misc.h" #else #include "stm32f2xx.h" - #include "stm32f2xx_rcc.h" - #include "stm32f2xx_syscfg.h" - #include "stm32f2xx_gpio.h" - #include "stm32f2xx_exti.h" - #include "stm32f2xx_tim.h" - #include "stm32f2xx_spi.h" - #include "stm32f2xx_pwr.h" - #include "stm32f2xx_dma.h" - #include "stm32f2xx_dbgmcu.h" - #include "misc.h" #include "dwt.h" // the old ST library that we use does not define DWT register for STM32F2xx #endif #endif -//#include "usb_driver.h" #if defined(SIMU) #include "../simu/simpgmspace.h" #endif -// Delays driver -#define SYSTEM_TICKS_1MS ((CPU_FREQ + 500) / 1000) -#define SYSTEM_TICKS_1US ((CPU_FREQ + 500000) / 1000000) -#define SYSTEM_TICKS_01US ((CPU_FREQ + 5000000) / 10000000) - -#ifdef __cplusplus -extern "C" { -#endif - -static inline uint32_t ticksNow() -{ #if !defined(SIMU) && !defined(BACKUP) - return DWT->CYCCNT; + #define ticksNow() ((uint32_t)(DWT->CYCCNT)) #else - return 0; -#endif -} - -#ifdef __cplusplus -} + #define ticksNow() ((uint32_t)(0UL)) #endif #include "delays_driver.h" diff --git a/radio/src/targets/common/arm/stm32/bootloader/CMakeLists.txt b/radio/src/targets/common/arm/stm32/bootloader/CMakeLists.txt index c9ba78dba..09fd42806 100644 --- a/radio/src/targets/common/arm/stm32/bootloader/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/bootloader/CMakeLists.txt @@ -62,7 +62,7 @@ if(PCB STREQUAL X10 OR PCB STREQUAL X12S OR PCB STREQUAL NV14 OR PCB STREQUAL PL ../../../../../targets/common/arm/stm32/spi_flash.cpp ../../../../../drivers/frftl.cpp ../../../../../crc.cpp - ../../../../../targets/${TARGET_DIR}/sdram_driver.c + ../../../../../targets/common/arm/stm32/sdram_driver.cpp ../../../../../targets/${TARGET_DIR}/haptic_driver.cpp ) diff --git a/radio/src/targets/common/arm/stm32/bootloader/boot.cpp b/radio/src/targets/common/arm/stm32/bootloader/boot.cpp index 6c99d7341..c673818ae 100644 --- a/radio/src/targets/common/arm/stm32/bootloader/boot.cpp +++ b/radio/src/targets/common/arm/stm32/bootloader/boot.cpp @@ -20,6 +20,7 @@ */ #include "stm32_hal_ll.h" +#include "stm32_timer.h" #include "hal/usb_driver.h" #if defined(BLUETOOTH) @@ -100,6 +101,7 @@ MemoryType memoryType; uint32_t unlocked = 0; void per5ms() {} // make linker happy + void per10ms() { tenms |= 1u; // 10 mS has passed @@ -202,18 +204,12 @@ void writeEepromBlock() #if !defined(SIMU) void bootloaderInitApp() { - RCC_AHB1PeriphClockCmd(PWR_RCC_AHB1Periph | LCD_RCC_AHB1Periph | - BACKLIGHT_RCC_AHB1Periph | - KEYS_BACKLIGHT_RCC_AHB1Periph, - ENABLE); + LL_AHB1_GRP1_EnableClock(LCD_RCC_AHB1Periph); +#if defined(LCD_RCC_APB2Periph) + LL_APB2_GRP1_EnableClock(LCD_RCC_APB2Periph); +#endif + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); - RCC_APB1PeriphClockCmd(ROTARY_ENCODER_RCC_APB1Periph | LCD_RCC_APB1Periph | - BACKLIGHT_RCC_APB1Periph, - ENABLE); - - RCC_APB2PeriphClockCmd( - LCD_RCC_APB2Periph | BACKLIGHT_RCC_APB2Periph | RCC_APB2Periph_SYSCFG, - ENABLE); #if defined(HAVE_BOARD_BOOTLOADER_INIT) boardBootloaderInit(); diff --git a/radio/src/targets/common/arm/stm32/delays_driver.cpp b/radio/src/targets/common/arm/stm32/delays_driver.cpp index 934cf0c6a..241f3814e 100644 --- a/radio/src/targets/common/arm/stm32/delays_driver.cpp +++ b/radio/src/targets/common/arm/stm32/delays_driver.cpp @@ -19,8 +19,13 @@ * GNU General Public License for more details. */ +#include "delays_driver.h" #include "board.h" +#define SYSTEM_TICKS_1MS ((CPU_FREQ + 500) / 1000) +#define SYSTEM_TICKS_1US ((CPU_FREQ + 500000) / 1000000) +#define SYSTEM_TICKS_01US ((CPU_FREQ + 5000000) / 10000000) + void delaysInit() { CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; diff --git a/radio/src/targets/common/arm/stm32/diskio_sdio.cpp b/radio/src/targets/common/arm/stm32/diskio_sdio.cpp index 471a713de..5ad0d40c1 100644 --- a/radio/src/targets/common/arm/stm32/diskio_sdio.cpp +++ b/radio/src/targets/common/arm/stm32/diskio_sdio.cpp @@ -21,11 +21,13 @@ #include "diskio_sdio.h" +#include "hal/gpio.h" #include "stm32_dma.h" #include "stm32_hal.h" #include "stm32_hal_ll.h" #include "stm32_gpio_driver.h" +#include "stm32_gpio.h" #include "hal.h" @@ -215,7 +217,7 @@ static DSTATUS sdio_status(BYTE lun) DSTATUS stat = RES_OK; #if defined(SD_PRESENT_GPIO) - if ((LL_GPIO_ReadInputPort(SD_PRESENT_GPIO) & SD_PRESENT_LL_GPIO_PIN) != 0) { + if (gpio_read(SD_PRESENT_GPIO)) { stat |= STA_NODISK; } #endif diff --git a/radio/src/targets/common/arm/stm32/f2/CMakeLists.txt b/radio/src/targets/common/arm/stm32/f2/CMakeLists.txt index 1fba325fb..3ffde29d9 100644 --- a/radio/src/targets/common/arm/stm32/f2/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/f2/CMakeLists.txt @@ -45,22 +45,15 @@ if(NOT NATIVE_BUILD) endif() # StdPeriph library -set(STM32LIB_DIR ${THIRDPARTY_DIR}/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries) -include_directories(${STM32LIB_DIR}/STM32F2xx_StdPeriph_Driver/inc) +set(STM32LIB_DIR ${THIRDPARTY_DIR}) include_directories(${STM32LIB_DIR}/CMSIS/Device/ST/STM32F2xx/Include) include_directories(${STM32LIB_DIR}/CMSIS/Include) add_definitions(-DSTM32F2) -set(STM32_STDPERIPH_DIR ${STM32LIB_DIR}/STM32F2xx_StdPeriph_Driver) - add_library(stm32_stdperiph OBJECT EXCLUDE_FROM_ALL targets/common/arm/stm32/f2/system_stm32f2xx.c boards/generic_stm32/startup/startup_stm32f205xx.s - ${STM32_STDPERIPH_DIR}/src/misc.c - ${STM32_STDPERIPH_DIR}/src/stm32f2xx_gpio.c - ${STM32_STDPERIPH_DIR}/src/stm32f2xx_dbgmcu.c - ${STM32_STDPERIPH_DIR}/src/stm32f2xx_rcc.c ) set(FIRMWARE_SRC ${FIRMWARE_SRC} $) diff --git a/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c b/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c index 31c9f43a6..a6a7e4e42 100644 --- a/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c +++ b/radio/src/targets/common/arm/stm32/f2/system_stm32f2xx.c @@ -31,6 +31,7 @@ */ #include "stm32f2xx.h" +#include "stm32_hal.h" /** * @} @@ -87,8 +88,8 @@ uint32_t SystemCoreClock = 120000000; - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - __I uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} diff --git a/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt b/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt index 580143e12..c93a7a081 100644 --- a/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt +++ b/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt @@ -24,6 +24,7 @@ if(NOT NATIVE_BUILD) add_library(stm32cube_ll OBJECT EXCLUDE_FROM_ALL # LL drivers ${STM32CUBE_DIR}/Src/stm32f4xx_ll_gpio.c + ${STM32CUBE_DIR}/Src/stm32f4xx_ll_fmc.c ${STM32CUBE_DIR}/Src/stm32f4xx_ll_tim.c ${STM32CUBE_DIR}/Src/stm32f4xx_ll_dma.c ${STM32CUBE_DIR}/Src/stm32f4xx_ll_usart.c @@ -46,6 +47,8 @@ if(NOT NATIVE_BUILD) ${STM32CUBE_DIR}/Src/stm32f4xx_hal_dma.c ${STM32CUBE_DIR}/Src/stm32f4xx_hal_pcd.c ${STM32CUBE_DIR}/Src/stm32f4xx_hal_pcd_ex.c + ${STM32CUBE_DIR}/Src/stm32f4xx_hal_flash.c + ${STM32CUBE_DIR}/Src/stm32f4xx_hal_flash_ex.c ${STM32CUBE_DIR}/Src/stm32f4xx_hal_cortex.c ${STM32_COLORLCD_DRIVERS} @@ -62,29 +65,19 @@ if(NOT NATIVE_BUILD) endif() # StdPeriph library -set(STM32LIB_DIR ${THIRDPARTY_DIR}/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries) -include_directories(${STM32LIB_DIR}/STM32F4xx_StdPeriph_Driver/inc) +set(STM32LIB_DIR ${THIRDPARTY_DIR}) include_directories(${STM32LIB_DIR}/CMSIS/Device/ST/STM32F4xx/Include) include_directories(${STM32LIB_DIR}/CMSIS/Include) add_definitions(-DSTM32F4) -set(STM32_STDPERIPH_DIR ${STM32LIB_DIR}/STM32F4xx_StdPeriph_Driver) - set(STM32_STDPERIPH_SRC targets/common/arm/stm32/f4/system_stm32f4xx.c - ${STM32_STDPERIPH_DIR}/src/misc.c - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_gpio.c - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_dbgmcu.c - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_rcc.c - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_flash.c ) if(CPU_TYPE_FULL STREQUAL STM32F429xI) set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC} boards/generic_stm32/startup/startup_stm32f42_43xxx.s - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_fmc.c - ${STM32_STDPERIPH_DIR}/src/stm32f4xx_dma.c ) elseif (CPU_TYPE_FULL STREQUAL STM32F413xG) set(STM32_STDPERIPH_SRC ${STM32_STDPERIPH_SRC} diff --git a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c index a46d4e4af..b8d67febe 100644 --- a/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c +++ b/radio/src/targets/common/arm/stm32/f4/system_stm32f4xx.c @@ -120,7 +120,9 @@ * @{ */ -#include "stm32f4xx.h" +#include "thirdparty/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "stm32_hal.h" +#include "stm32_hal_ll.h" /** * @} @@ -195,8 +197,8 @@ uint32_t SystemCoreClock = 168000000; #endif - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - __I uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; /** * @} @@ -257,10 +259,8 @@ void SystemInit(void) #if defined(SDRAM) void SDRAM_Init(); - void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); SDRAM_Init(); // calls SDRAM_GPIOConfig() - FMC_SDRAMWriteProtectionConfig(((uint32_t)0x00000001), DISABLE); #endif #ifdef DATA_IN_ExtSRAM diff --git a/radio/src/targets/common/arm/stm32/flash_driver.cpp b/radio/src/targets/common/arm/stm32/flash_driver.cpp index 166d724a1..93a3d55d6 100644 --- a/radio/src/targets/common/arm/stm32/flash_driver.cpp +++ b/radio/src/targets/common/arm/stm32/flash_driver.cpp @@ -19,20 +19,18 @@ * GNU General Public License for more details. */ +#include "stm32_cmsis.h" +#include "stm32_hal.h" + #include "board.h" #include "hal/watchdog_driver.h" -#if defined(STM32F4) -#include "stm32f4xx_flash.h" -#elif defined(STM32F2) -#include "stm32f2xx_flash.h" -#endif void waitFlashIdle() { do { WDG_RESET(); - } while (FLASH->SR & FLASH_FLAG_BSY); + } while (FLASH->SR & FLASH_SR_BSY); } //After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the @@ -64,8 +62,8 @@ void eraseSector(uint32_t sector) waitFlashIdle(); - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR &= ~FLASH_CR_PSIZE; + FLASH->CR |= FLASH_CR_PSIZE_1; FLASH->CR &= SECTOR_MASK; FLASH->CR |= FLASH_CR_SER | (sector << 3); FLASH->CR |= FLASH_CR_STRT; @@ -136,7 +134,7 @@ void flashWrite(uint32_t * address, const uint32_t * buffer) // page size is 256 #undef SECTOR_ADDRESS #undef FLASH_BANK - + for (uint32_t i=0; iCR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR &= ~FLASH_CR_PSIZE; + FLASH->CR |= FLASH_CR_PSIZE_1; FLASH->CR |= FLASH_CR_PG; *address = *buffer; diff --git a/radio/src/targets/common/arm/stm32/flysky_gimbal_driver.cpp b/radio/src/targets/common/arm/stm32/flysky_gimbal_driver.cpp index 682b6e046..bc4eca4e2 100644 --- a/radio/src/targets/common/arm/stm32/flysky_gimbal_driver.cpp +++ b/radio/src/targets/common/arm/stm32/flysky_gimbal_driver.cpp @@ -21,10 +21,12 @@ #include "flysky_gimbal_driver.h" #include "stm32_serial_driver.h" +#include "stm32_gpio.h" #include "stm32_adc.h" #include "delays_driver.h" #include "hal/adc_driver.h" +#include "hal/gpio.h" #include "hal.h" #include "crc.h" @@ -33,8 +35,8 @@ static const stm32_usart_t fsUSART = { .USARTx = FLYSKY_HALL_SERIAL_USART, - .GPIOx = FLYSKY_HALL_SERIAL_GPIO, - .GPIO_Pin = FLYSKY_HALL_SERIAL_RX_GPIO_PIN, + .txGPIO = GPIO_UNDEF, + .rxGPIO = FLYSKY_HALL_SERIAL_RX_GPIO, .IRQn = FLYSKY_HALL_SERIAL_USART_IRQn, .IRQ_Prio = 6, .txDMA = nullptr, diff --git a/radio/src/targets/common/arm/stm32/heartbeat_driver.cpp b/radio/src/targets/common/arm/stm32/heartbeat_driver.cpp index d72f09574..5b3191daa 100644 --- a/radio/src/targets/common/arm/stm32/heartbeat_driver.cpp +++ b/radio/src/targets/common/arm/stm32/heartbeat_driver.cpp @@ -19,8 +19,12 @@ * GNU General Public License for more details. */ -#include "stm32_hal_ll.h" +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "stm32_exti_driver.h" +#include "stm32_hal_ll.h" + #include "mixer_scheduler.h" #include "board.h" #include "debug.h" @@ -47,21 +51,9 @@ void init_intmodule_heartbeat() { TRACE("init_intmodule_heartbeat"); - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = INTMODULE_HEARTBEAT_GPIO_PIN; - pinInit.Mode = LL_GPIO_MODE_INPUT; - pinInit.Speed = LL_GPIO_SPEED_FREQ_LOW; - pinInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - pinInit.Pull = LL_GPIO_PULL_UP; - - LL_GPIO_Init(INTMODULE_HEARTBEAT_GPIO, &pinInit); - - LL_SYSCFG_SetEXTISource(INTMODULE_HEARTBEAT_EXTI_PORT, INTMODULE_HEARTBEAT_EXTI_SYS_LINE); - - stm32_exti_enable(INTMODULE_HEARTBEAT_EXTI_LINE, INTMODULE_HEARTBEAT_TRIGGER, - trigger_intmodule_heartbeat); + gpio_init_int(INTMODULE_HEARTBEAT_GPIO, GPIO_IN_PU, + INTMODULE_HEARTBEAT_TRIGGER, + trigger_intmodule_heartbeat); heartbeatCapture.valid = true; } diff --git a/radio/src/targets/common/arm/stm32/pwr_driver.cpp b/radio/src/targets/common/arm/stm32/pwr_driver.cpp index 74d22dcf0..9e1abe628 100644 --- a/radio/src/targets/common/arm/stm32/pwr_driver.cpp +++ b/radio/src/targets/common/arm/stm32/pwr_driver.cpp @@ -19,68 +19,58 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" #include "hal/abnormal_reboot.h" void pwrInit() { - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - #if defined(INTMODULE_BOOTCMD_GPIO) - INIT_INTMODULE_BOOTCMD_PIN(); - GPIO_InitStructure.GPIO_Pin = INTMODULE_BOOTCMD_GPIO_PIN; - GPIO_Init(INTMODULE_BOOTCMD_GPIO, &GPIO_InitStructure); + gpio_init(INTMODULE_BOOTCMD_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_write(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_DEFAULT); #endif // Internal module power #if defined(HARDWARE_INTERNAL_MODULE) + gpio_init(INTMODULE_PWR_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); INTERNAL_MODULE_OFF(); - GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; - GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); #endif // External module power #if defined(HARDWARE_EXTERNAL_MODULE) + gpio_init(EXTMODULE_PWR_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); EXTERNAL_MODULE_PWR_OFF(); - GPIO_InitStructure.GPIO_Pin = EXTMODULE_PWR_GPIO_PIN; - GPIO_Init(EXTMODULE_PWR_GPIO, &GPIO_InitStructure); #endif - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - // PWR switch #if defined(PWR_SWITCH_GPIO) - GPIO_InitStructure.GPIO_Pin = PWR_SWITCH_GPIO_PIN; - GPIO_Init(PWR_SWITCH_GPIO, &GPIO_InitStructure); + gpio_init(PWR_SWITCH_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); #endif #if defined(PWR_EXTRA_SWITCH_GPIO) // PWR Extra switch - GPIO_InitStructure.GPIO_Pin = PWR_EXTRA_SWITCH_GPIO_PIN; - GPIO_Init(PWR_EXTRA_SWITCH_GPIO, &GPIO_InitStructure); + gpio_init(PWR_EXTRA_SWITCH_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); #endif #if defined(PCBREV_HARDCODED) hardwareOptions.pcbrev = PCBREV_HARDCODED; -#elif defined(PCBREV_GPIO_PIN) +#elif defined(PCBREV_GPIO) #if defined(PCBREV_GPIO_PULL_DOWN) - GPIO_ResetBits(PCBREV_GPIO, PCBREV_GPIO_PIN); - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; + gpio_init(PCBREV_GPIO, GPIO_IN_PD, GPIO_PIN_SPEED_LOW); + #else + gpio_init(PCBREV_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); #endif - GPIO_InitStructure.GPIO_Pin = PCBREV_GPIO_PIN; - GPIO_Init(PCBREV_GPIO, &GPIO_InitStructure); + hardwareOptions.pcbrev = PCBREV_VALUE(); +#elif defined(PCBREV_GPIO_1) && defined(PCBREV_GPIO_2) + gpio_init(PCBREV_GPIO_1, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); #if defined(PCBREV_TOUCH_GPIO_PIN) #if defined(PCBREV_TOUCH_GPIO_PULL_UP) - GPIO_ResetBits(PCBREV_TOUCH_GPIO, PCBREV_TOUCH_GPIO_PIN); - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; + gpio_init(PCBREV_GPIO_2, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); + #else + gpio_init(PCBREV_TOUCH_GPIO, GPIO_IN_PD, GPIO_PIN_SPEED_LOW); #endif - GPIO_InitStructure.GPIO_Pin = PCBREV_TOUCH_GPIO_PIN; - GPIO_Init(PCBREV_TOUCH_GPIO, &GPIO_InitStructure); #endif hardwareOptions.pcbrev = PCBREV_VALUE(); @@ -89,44 +79,32 @@ void pwrInit() void pwrOn() { - // we keep the init of the PIN to have pwrOn as quick as possible #if defined(PWR_ON_GPIO) - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PWR_ON_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(PWR_ON_GPIO, &GPIO_InitStructure); - - GPIO_SetBits(PWR_ON_GPIO, PWR_ON_GPIO_PIN); + gpio_init(PWR_ON_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_set(PWR_ON_GPIO); #endif } void pwrOff() { #if defined(PWR_ON_GPIO) - GPIO_ResetBits(PWR_ON_GPIO, PWR_ON_GPIO_PIN); + gpio_clear(PWR_ON_GPIO); #endif } #if defined(PWR_EXTRA_SWITCH_GPIO) bool pwrForcePressed() { - return (GPIO_ReadInputDataBit(PWR_SWITCH_GPIO, PWR_SWITCH_GPIO_PIN) == Bit_RESET && GPIO_ReadInputDataBit(PWR_EXTRA_SWITCH_GPIO, PWR_EXTRA_SWITCH_GPIO_PIN) == Bit_RESET); + return !gpio_read(PWR_SWITCH_GPIO) && !gpio_read(PWR_EXTRA_SWITCH_GPIO); } #endif bool pwrPressed() { #if defined(PWR_EXTRA_SWITCH_GPIO) - return (GPIO_ReadInputDataBit(PWR_SWITCH_GPIO, PWR_SWITCH_GPIO_PIN) == - Bit_RESET || - GPIO_ReadInputDataBit(PWR_EXTRA_SWITCH_GPIO, - PWR_EXTRA_SWITCH_GPIO_PIN) == Bit_RESET); + return !gpio_read(PWR_SWITCH_GPIO) && !gpio_read(PWR_EXTRA_SWITCH_GPIO); #elif defined(PWR_SWITCH_GPIO) - return GPIO_ReadInputDataBit(PWR_SWITCH_GPIO, PWR_SWITCH_GPIO_PIN) == - Bit_RESET; + return !gpio_read(PWR_SWITCH_GPIO); #else return true; #endif @@ -145,13 +123,6 @@ bool pwrOffPressed() void pwrResetHandler() { - RCC->AHB1ENR |= PWR_RCC_AHB1Periph; - - // these two NOPs are needed (see STM32F errata sheet) before the peripheral - // register can be written after the peripheral clock was enabled - __ASM volatile ("nop"); - __ASM volatile ("nop"); - if (WAS_RESET_BY_WATCHDOG_OR_SOFTWARE()) { pwrOn(); } diff --git a/radio/src/targets/common/arm/stm32/rotary_encoder_driver.cpp b/radio/src/targets/common/arm/stm32/rotary_encoder_driver.cpp index 0bee64429..458803266 100644 --- a/radio/src/targets/common/arm/stm32/rotary_encoder_driver.cpp +++ b/radio/src/targets/common/arm/stm32/rotary_encoder_driver.cpp @@ -29,6 +29,7 @@ #include "hal/rotary_encoder.h" #include "board_common.h" +#include "stm32_timer.h" #if !defined(BOOT) #include "opentx.h" @@ -153,7 +154,8 @@ void rotaryEncoderInit() stm32_gpio_enable_clock(ROTARY_ENCODER_GPIO); LL_GPIO_Init(ROTARY_ENCODER_GPIO, &pinInit); - + + stm32_timer_enable_clock(ROTARY_ENCODER_TIMER); ROTARY_ENCODER_TIMER->ARR = 99; // 100uS ROTARY_ENCODER_TIMER->PSC = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 1000000 - 1; // 1uS ROTARY_ENCODER_TIMER->CCER = 0; diff --git a/radio/src/targets/common/arm/stm32/sdram_driver.cpp b/radio/src/targets/common/arm/stm32/sdram_driver.cpp new file mode 100644 index 000000000..3af464733 --- /dev/null +++ b/radio/src/targets/common/arm/stm32/sdram_driver.cpp @@ -0,0 +1,274 @@ +/* + * Copyright (C) OpenTX + * + * Based on code named + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_hal_ll.h" + +#include "board.h" + +#if defined(SDRAM_BANK1) + #define SDRAM_BANK FMC_SDRAM_BANK1 + #define COMMAND_TARGET FMC_SDRAM_CMD_TARGET_BANK1 +#elif defined(SDRAM_BANK2) + #define SDRAM_BANK FMC_SDRAM_BANK2 + #define COMMAND_TARGET FMC_SDRAM_CMD_TARGET_BANK2 +#else + #error "No bank definition for SDRAM" +#endif + +#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16 +#define SDRAM_CAS_LATENCY FMC_SDRAM_CAS_LATENCY_3 +#define SDRAM_READBURST FMC_SDRAM_RBURST_ENABLE +#define SDRAM_READPIPEDELAY FMC_SDRAM_RPIPE_DELAY_1 +#define SDRAM_CLK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 + +#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) +#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) +#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) +#define SDRAM_MODEREG_BURST_FULL_PAGE ((uint16_t)0x0007) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define SDRAM_MODEREG_CAS_LATENCY_1 ((uint16_t)0x0010) +#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) +#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +#define GPIO_AF_FMC GPIO_AF12 + +extern "C" void SDRAM_GPIOConfig(void) +{ + /*-- GPIOs Configuration -----------------------------------------------------*/ + /* + +-------------------+--------------------+--------------------+--------------------+ + + SDRAM pins assignment + + +-------------------+--------------------+--------------------+--------------------+ + | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | + | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | + | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | + | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | + | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ + | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | + | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | + +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | + | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | + | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | + | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | + +-------------------+--------------------+--------------------+ + | PC3 <-> FMC_SDCKE0| PB5 <-> FMC_SDCKE1 | + | PH3 <-> FMC_SDNE0 | PH6 <-> FMC_SDNE1 | + | PH5 <-> FMC_SDNWE | | + +-------------------++-------------------+ + */ + +#if defined(SDRAM_BANK1) + /* GPIOC configuration */ + gpio_init_af(GPIO_PIN(GPIOC, 3), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +#else + /* GPIOB configuration */ + gpio_init_af(GPIO_PIN(GPIOB, 5), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +#endif + + /* GPIOH configuration */ + gpio_init_af(GPIO_PIN(GPIOH, 5), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +#if defined(SDRAM_BANK1) + gpio_init_af(GPIO_PIN(GPIOH, 3), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +#else + gpio_init_af(GPIO_PIN(GPIOH, 6), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +#endif + + /* GPIOD configuration */ + gpio_init_af(GPIO_PIN(GPIOD, 0), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 1), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 8), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 9), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 10), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 14), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOD, 15), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + + /* GPIOE configuration */ + gpio_init_af(GPIO_PIN(GPIOE, 0), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 1), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 7), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 8), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 9), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 10), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 11), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 12), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 13), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 14), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOE, 15), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + + /* GPIOF configuration */ + gpio_init_af(GPIO_PIN(GPIOF, 0), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 1), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 2), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 3), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 4), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 5), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 11), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 12), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 13), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 14), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOF, 15), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + + /* GPIOG configuration */ + gpio_init_af(GPIO_PIN(GPIOG, 0), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOG, 1), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOG, 4), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOG, 5), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOG, 8), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(GPIO_PIN(GPIOG, 15), GPIO_AF_FMC, GPIO_PIN_SPEED_VERY_HIGH); +} + +void SDRAM_InitSequence(void) +{ + FMC_SDRAM_CommandTypeDef FMC_SDRAMCommandStructure; + uint32_t tmpr = 0; + + /* Step 3 --------------------------------------------------------------------*/ + /* Configure a clock configuration enable command */ + FMC_SDRAMCommandStructure.CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; + FMC_SDRAMCommandStructure.CommandTarget = COMMAND_TARGET; + FMC_SDRAMCommandStructure.AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while((__FMC_SDRAM_GET_FLAG(FMC_SDRAM_DEVICE, FMC_SDRAM_FLAG_BUSY) != 0)); + + /* Send the command */ + FMC_SDRAM_SendCommand(FMC_SDRAM_DEVICE, &FMC_SDRAMCommandStructure, 10); + + /* Step 4 --------------------------------------------------------------------*/ + /* Insert 100 ms delay */ + delay_ms(100); + + /* Step 5 --------------------------------------------------------------------*/ + /* Configure a PALL (precharge all) command */ + FMC_SDRAMCommandStructure.CommandMode = FMC_SDRAM_CMD_PALL; + FMC_SDRAMCommandStructure.CommandTarget = COMMAND_TARGET; + FMC_SDRAMCommandStructure.AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.ModeRegisterDefinition = 0; + /* Wait until the SDRAM controller is ready */ + while((__FMC_SDRAM_GET_FLAG(FMC_SDRAM_DEVICE, FMC_SDRAM_FLAG_BUSY) != 0)); + + /* Send the command */ + FMC_SDRAM_SendCommand(FMC_SDRAM_DEVICE, &FMC_SDRAMCommandStructure, 10); + + /* Step 6 --------------------------------------------------------------------*/ + /* Configure a Auto-Refresh command */ + FMC_SDRAMCommandStructure.CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; + FMC_SDRAMCommandStructure.CommandTarget = COMMAND_TARGET; + FMC_SDRAMCommandStructure.AutoRefreshNumber = 4; + FMC_SDRAMCommandStructure.ModeRegisterDefinition = 0; + + /* Wait until the SDRAM controller is ready */ + while((__FMC_SDRAM_GET_FLAG(FMC_SDRAM_DEVICE, FMC_SDRAM_FLAG_BUSY) != 0)); + + /* Send the command */ + FMC_SDRAM_SendCommand(FMC_SDRAM_DEVICE, &FMC_SDRAMCommandStructure, 10); + + /* Step 7 --------------------------------------------------------------------*/ + /* Program the external memory mode register */ + tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | + SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | + SDRAM_MODEREG_CAS_LATENCY_3 | + SDRAM_MODEREG_OPERATING_MODE_STANDARD | + SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; + + /* Configure a load Mode register command*/ + FMC_SDRAMCommandStructure.CommandMode = FMC_SDRAM_CMD_LOAD_MODE; + FMC_SDRAMCommandStructure.CommandTarget = COMMAND_TARGET; + FMC_SDRAMCommandStructure.AutoRefreshNumber = 1; + FMC_SDRAMCommandStructure.ModeRegisterDefinition = tmpr; + + /* Wait until the SDRAM controller is ready */ + while((__FMC_SDRAM_GET_FLAG(FMC_SDRAM_DEVICE, FMC_SDRAM_FLAG_BUSY) != 0)); + + /* Send the command */ + FMC_SDRAM_SendCommand(FMC_SDRAM_DEVICE, &FMC_SDRAMCommandStructure, 10); + + /* Step 8: Set the refresh rate counter - refer to section SDRAM refresh timer register in RM0455 */ + /* Set the device refresh rate + * COUNT = [(SDRAM self refresh time / number of row) x SDRAM CLK] – 20 + = [(64ms/4096) * 84MHz] - 20 = 1312 - 20 ~ 1292 */ + FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_DEVICE, 1292); + /* Wait until the SDRAM controller is ready */ + while((__FMC_SDRAM_GET_FLAG(FMC_SDRAM_DEVICE, FMC_SDRAM_FLAG_BUSY) != 0)); +} + +extern "C" void SDRAM_Init(void) +{ + //delay funcion needed + delaysInit(); + // Clocks must be enabled here, because the sdramInit is called before main + LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FMC); + + /* GPIO configuration for FMC SDRAM bank */ + SDRAM_GPIOConfig(); + + + /* FMC Configuration ---------------------------------------------------------*/ + FMC_SDRAM_InitTypeDef FMC_SDRAMInitStructure; + FMC_SDRAM_TimingTypeDef FMC_SDRAMTimingInitStructure; + + /* FMC SDRAM Bank configuration */ + /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */ + /* TMRD: 2 Clock cycles */ + FMC_SDRAMTimingInitStructure.LoadToActiveDelay = 2; + /* TXSR: min=72ns (7x11.9ns) */ + FMC_SDRAMTimingInitStructure.ExitSelfRefreshDelay = 7; + /* TRAS: min=42ns (4x11.9ns) max=120k (ns) */ + FMC_SDRAMTimingInitStructure.SelfRefreshTime = 4; + /* TRC: min=60 (6x11.9ns) */ + FMC_SDRAMTimingInitStructure.RowCycleDelay = 6; + /* TWR: 2 CLK */ + FMC_SDRAMTimingInitStructure.WriteRecoveryTime = 2; + /* TRP: 15ns => 2x11.9ns */ + FMC_SDRAMTimingInitStructure.RPDelay = 2; + /* TRCD: 15ns => 2x11.9ns */ + FMC_SDRAMTimingInitStructure.RCDDelay = 2; + + /* FMC SDRAM control configuration */ + FMC_SDRAMInitStructure.SDBank = SDRAM_BANK; + /* Row addressing: [7:0] */ + FMC_SDRAMInitStructure.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_8; + /* Column addressing: [11:0] */ + FMC_SDRAMInitStructure.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12; + FMC_SDRAMInitStructure.MemoryDataWidth = SDRAM_MEMORY_WIDTH; + FMC_SDRAMInitStructure.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; + FMC_SDRAMInitStructure.CASLatency = SDRAM_CAS_LATENCY; + FMC_SDRAMInitStructure.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; + FMC_SDRAMInitStructure.SDClockPeriod = SDRAM_CLK_PERIOD; + FMC_SDRAMInitStructure.ReadBurst = SDRAM_READBURST; + FMC_SDRAMInitStructure.ReadPipeDelay = SDRAM_READPIPEDELAY; +// FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; + + /* FMC SDRAM bank initialization */ + FMC_SDRAM_Init(FMC_SDRAM_DEVICE, &FMC_SDRAMInitStructure); + FMC_SDRAM_Timing_Init(FMC_SDRAM_DEVICE, &FMC_SDRAMTimingInitStructure, SDRAM_BANK); + + + /* FMC SDRAM device initialization sequence */ + SDRAM_InitSequence(); + FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_DEVICE, SDRAM_BANK); +} diff --git a/radio/src/targets/common/arm/stm32/stm32_exti_driver.cpp b/radio/src/targets/common/arm/stm32/stm32_exti_driver.cpp index b7950defe..27b90c3fd 100644 --- a/radio/src/targets/common/arm/stm32/stm32_exti_driver.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_exti_driver.cpp @@ -98,6 +98,10 @@ void stm32_exti_enable(uint32_t line, uint8_t trigger, stm32_exti_handler_t cb) { if (line > LL_EXTI_LINE_15) return; +#if defined(LL_APB2_GRP1_PERIPH_EXTI) + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_EXTI); +#endif + LL_EXTI_InitTypeDef EXTI_init; LL_EXTI_StructInit(&EXTI_init); diff --git a/radio/src/targets/common/arm/stm32/stm32_gpio.cpp b/radio/src/targets/common/arm/stm32/stm32_gpio.cpp new file mode 100644 index 000000000..6b95f5937 --- /dev/null +++ b/radio/src/targets/common/arm/stm32/stm32_gpio.cpp @@ -0,0 +1,170 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_exti_driver.h" +#include "stm32_gpio_driver.h" +#include "stm32_hal_ll.h" + +static inline GPIO_TypeDef* _port(gpio_t pin) +{ + return (GPIO_TypeDef*)(pin & ~(0x0f)); +} + +static inline int _port_num(gpio_t pin) +{ + return (((pin - GPIOA_BASE) >> 10) & 0x0f); +} + +static inline void _enable_clock(GPIO_TypeDef* port) +{ + uint32_t reg_idx = (((uint32_t)port) - GPIOA_BASE) >> 10; + LL_AHB1_GRP1_EnableClock(RCC_AHB1ENR_GPIOAEN << reg_idx); +} + +static inline int _pin_num(gpio_t pin) +{ + return (pin & 0x0f); +} + +static inline void _set_mode(GPIO_TypeDef* port, int pin_num, unsigned mode) +{ + uint32_t tmp = port->MODER; + tmp &= ~(0x3 << (2 * pin_num)); + tmp |= ((mode & 0x3) << (2 * pin_num)); + port->MODER = tmp; +} + +static inline unsigned _get_mode(GPIO_TypeDef* port, int pin_num) +{ + uint32_t tmp = port->MODER; + tmp >>= (2 * pin_num); + return tmp & 0x03; +} + + +void gpio_init(gpio_t pin, gpio_mode_t mode, gpio_speed_t speed) +{ + GPIO_TypeDef* port = _port(pin); + int pin_num = _pin_num(pin); + + _enable_clock(port); + _set_mode(port, pin, mode); + + // pull up/down + port->PUPDR &= ~(0x3 << (2 * pin_num)); + port->PUPDR |= (((mode >> 2) & 0x3) << (2 * pin_num)); + + // output mode + port->OTYPER &= ~(1 << pin_num); + port->OTYPER |= (((mode >> 4) & 0x1) << pin_num); + + // pin speed to max + port->OSPEEDR |= (speed << (2 * pin_num)); +} + +void gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank, gpio_cb_t cb) +{ + int port_num = _port_num(pin); + int pin_num = _pin_num(pin); + + gpio_init(pin, mode, GPIO_PIN_SPEED_LOW); + + // enable specific pin as exti sources + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); + SYSCFG->EXTICR[pin_num >> 2] &= ~(0xf << ((pin_num & 0x03) * 4)); + SYSCFG->EXTICR[pin_num >> 2] |= (port_num << ((pin_num & 0x03) * 4)); + + stm32_exti_enable(1 << pin_num, (uint8_t)flank, cb); +} + +void gpio_int_disable(gpio_t pin) +{ + int pin_num = _pin_num(pin); + stm32_exti_disable(1 << pin_num); +} + +void gpio_init_af(gpio_t pin, gpio_af_t af, gpio_speed_t speed) +{ + GPIO_TypeDef* port = _port(pin); + int pin_num = _pin_num(pin); + + _enable_clock(port); + + // set selected function + port->AFR[(pin_num > 7) ? 1 : 0] &= ~(0xf << ((pin_num & 0x07) * 4)); + port->AFR[(pin_num > 7) ? 1 : 0] |= (af << ((pin_num & 0x07) * 4)); + // pin speed to max + port->OSPEEDR |= (speed << (2 * pin_num)); + + _set_mode(port, pin_num, 2); +} + +void gpio_init_analog(gpio_t pin) +{ + GPIO_TypeDef* port = _port(pin); + int pin_num = _pin_num(pin); + + _enable_clock(port); + _set_mode(port, pin_num, 3); + + // PUPD has to be 0b00 + port->PUPDR &= ~(0x3 << (2 * pin_num)); +} + +gpio_mode_t gpio_get_mode(gpio_t pin) +{ + return _get_mode(_port(pin), _pin_num(pin)); +} + +int gpio_read(gpio_t pin) +{ + return (_port(pin)->IDR & (1 << _pin_num(pin))); +} + +void gpio_set(gpio_t pin) +{ + _port(pin)->BSRR = (1 << _pin_num(pin)); +} + +void gpio_clear(gpio_t pin) +{ + _port(pin)->BSRR = (1 << (_pin_num(pin) + 16)); +} + +void gpio_toggle(gpio_t pin) +{ + if (gpio_read(pin)) { + gpio_clear(pin); + } else { + gpio_set(pin); + } +} + +void gpio_write(gpio_t pin, int value) +{ + if (value) { + gpio_set(pin); + } else { + gpio_clear(pin); + } +} diff --git a/radio/src/targets/common/arm/stm32/stm32_gpio.h b/radio/src/targets/common/arm/stm32/stm32_gpio.h new file mode 100644 index 000000000..a36675064 --- /dev/null +++ b/radio/src/targets/common/arm/stm32/stm32_gpio.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) EdgeTX + * + * Based on code named + * opentx - https://github.com/opentx/opentx + * th9x - http://code.google.com/p/th9x + * er9x - http://code.google.com/p/er9x + * gruvin9x - http://code.google.com/p/gruvin9x + * + * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#pragma once + +#include "stm32_cmsis.h" +#include + +#define GPIO_UNDEF (0xffffffff) + +// #define GPIO_PIN(x, y) ((GPIOA_BASE + (x << 10)) | y) +#define GPIO_PIN(x, y) ((intptr_t)x | y) + +// Generate GPIO mode bitfields +// +// bit 0+1: pin mode (input / output) +// bit 2+3: pull resistor configuration +// bit 4: output type (0: push-pull, 1: open-drain) +// +#define _GPIO_MODE(io, pr, ot) ((io << 0) | (pr << 2) | (ot << 4)) + +enum { + GPIO_IN = _GPIO_MODE(0, 0, 0), // input w/o pull R + GPIO_IN_PD = _GPIO_MODE(0, 2, 0), // input with pull-down + GPIO_IN_PU = _GPIO_MODE(0, 1, 0), // input with pull-up + GPIO_OUT = _GPIO_MODE(1, 0, 0), // push-pull output + GPIO_OD = _GPIO_MODE(1, 0, 1), // open-drain w/o pull R + GPIO_OD_PU = _GPIO_MODE(1, 1, 1) // open-drain with pull-up +}; + +enum { + GPIO_AF0 = 0, + GPIO_AF1, + GPIO_AF2, + GPIO_AF3, + GPIO_AF4, + GPIO_AF5, + GPIO_AF6, + GPIO_AF7, + GPIO_AF8, + GPIO_AF9, + GPIO_AF10, + GPIO_AF11, + GPIO_AF12, + GPIO_AF13, + GPIO_AF14, + GPIO_AF15, + GPIO_AF_UNDEF +}; + +enum { + GPIO_PIN_SPEED_LOW = 0x00, + GPIO_PIN_SPEED_MEDIUM = 0x01, + GPIO_PIN_SPEED_HIGH = 0x02, + GPIO_PIN_SPEED_VERY_HIGH = 0x03, +}; diff --git a/radio/src/targets/common/arm/stm32/stm32_gpio_driver.cpp b/radio/src/targets/common/arm/stm32/stm32_gpio_driver.cpp index 913c2a215..c4fe50ad2 100644 --- a/radio/src/targets/common/arm/stm32/stm32_gpio_driver.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_gpio_driver.cpp @@ -20,6 +20,7 @@ */ #include "stm32_gpio_driver.h" +#include "stm32_hal_ll.h" void stm32_gpio_enable_clock(GPIO_TypeDef *GPIOx) { diff --git a/radio/src/targets/common/arm/stm32/stm32_gpio_driver.h b/radio/src/targets/common/arm/stm32/stm32_gpio_driver.h index d672d6f9c..75003cce7 100644 --- a/radio/src/targets/common/arm/stm32/stm32_gpio_driver.h +++ b/radio/src/targets/common/arm/stm32/stm32_gpio_driver.h @@ -21,6 +21,6 @@ #pragma once -#include "stm32_hal_ll.h" +#include "stm32_cmsis.h" void stm32_gpio_enable_clock(GPIO_TypeDef *GPIOx); diff --git a/radio/src/targets/common/arm/stm32/stm32_hal_ll.h b/radio/src/targets/common/arm/stm32/stm32_hal_ll.h index 4006daf47..612d47cb7 100644 --- a/radio/src/targets/common/arm/stm32/stm32_hal_ll.h +++ b/radio/src/targets/common/arm/stm32/stm32_hal_ll.h @@ -35,6 +35,7 @@ extern "C" { #if defined(STM32F4) #define USE_RTOS 0U #include "STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h" + #include "STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_fmc.h" #include "STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma2d.h" #include "STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h" #include "STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_tim.h" diff --git a/radio/src/targets/common/arm/stm32/stm32_pulse_driver.cpp b/radio/src/targets/common/arm/stm32/stm32_pulse_driver.cpp index 55550ebd6..744e9e08e 100644 --- a/radio/src/targets/common/arm/stm32/stm32_pulse_driver.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_pulse_driver.cpp @@ -23,6 +23,7 @@ #include "stm32_gpio_driver.h" #include "stm32_timer.h" #include "stm32_dma.h" +#include "stm32_gpio.h" #include "definitions.h" @@ -76,20 +77,13 @@ int stm32_pulse_init(const stm32_pulse_timer_t* tim, uint32_t freq) if (stm32_timer_is_clock_enabled(tim->TIMx)) return -1; // .. and GPIO pin is not used - uint32_t pin_mode = LL_GPIO_GetPinMode(tim->GPIOx, tim->GPIO_Pin); - if (pin_mode != LL_GPIO_MODE_INPUT) return -1; + if(gpio_get_mode(tim->GPIO) != GPIO_IN) return -1; if (tim->DMA_TC_CallbackPtr) { memset(tim->DMA_TC_CallbackPtr, 0, sizeof(stm32_pulse_dma_tc_cb_t)); } - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - pinInit.Pin = tim->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_ALTERNATE; - pinInit.Alternate = tim->GPIO_Alternate; - stm32_gpio_enable_clock(tim->GPIOx); - LL_GPIO_Init(tim->GPIOx, &pinInit); + gpio_init_af(tim->GPIO, tim->GPIO_Alternate, GPIO_PIN_SPEED_MEDIUM); LL_TIM_InitTypeDef timInit; LL_TIM_StructInit(&timInit); @@ -140,13 +134,7 @@ void stm32_pulse_deinit(const stm32_pulse_timer_t* tim) LL_TIM_DeInit(tim->TIMx); stm32_timer_disable_clock(tim->TIMx); - // Reconfigure pin as input - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = tim->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_INPUT; - LL_GPIO_Init(tim->GPIOx, &pinInit); + gpio_init(tim->GPIO, GPIO_IN, GPIO_PIN_SPEED_MEDIUM); } static inline bool _is_complementary_channel(uint32_t channel) diff --git a/radio/src/targets/common/arm/stm32/stm32_pulse_driver.h b/radio/src/targets/common/arm/stm32/stm32_pulse_driver.h index f32858eda..4cc32e37c 100644 --- a/radio/src/targets/common/arm/stm32/stm32_pulse_driver.h +++ b/radio/src/targets/common/arm/stm32/stm32_pulse_driver.h @@ -23,6 +23,7 @@ #include #include "stm32_hal_ll.h" +#include "hal/gpio.h" struct stm32_pulse_timer_t; typedef bool (*stm32_pulse_dma_tc_fct)(void*); @@ -34,8 +35,7 @@ struct stm32_pulse_dma_tc_cb_t { struct stm32_pulse_timer_t { - GPIO_TypeDef* GPIOx; - uint32_t GPIO_Pin; + gpio_t GPIO; uint32_t GPIO_Alternate; TIM_TypeDef* TIMx; diff --git a/radio/src/targets/common/arm/stm32/stm32_softserial_driver.cpp b/radio/src/targets/common/arm/stm32/stm32_softserial_driver.cpp index 9104f1dee..29561bce1 100644 --- a/radio/src/targets/common/arm/stm32/stm32_softserial_driver.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_softserial_driver.cpp @@ -22,6 +22,8 @@ #include "stm32_softserial_driver.h" #include "stm32_exti_driver.h" #include "stm32_timer.h" +#include "stm32_gpio.h" +#include "hal/gpio.h" #include @@ -48,8 +50,7 @@ static void _softserial_exti() // cheap debouncing... for (uint8_t i = 0; i < 16; ++i) { - if (LL_GPIO_IsInputPinSet(port->GPIOx, port->GPIO_Pin) == 0) - return; + if (!gpio_read(port->GPIO)) return; } // enable timer counter @@ -72,8 +73,7 @@ static bool _softserial_init_rx(const stm32_softserial_rx_port* port, const etx_serial_init* params) { // Test if pin is in reset state - uint32_t mode = LL_GPIO_GetPinMode(port->GPIOx, port->GPIO_Pin); - if (mode != LL_GPIO_MODE_INPUT) return false; + if(gpio_get_mode(port->GPIO) != GPIO_IN) return false; rxBitCount = 0; rxBuffer = port->buffer.buffer; @@ -98,45 +98,41 @@ static bool _softserial_init_rx(const stm32_softserial_rx_port* port, NVIC_SetPriority(port->TIM_IRQn, 0); NVIC_EnableIRQ(port->TIM_IRQn); - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - if (port->dir_GPIOx) { - pinInit.Pin = port->dir_Pin; - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - LL_GPIO_Init(port->dir_GPIOx, &pinInit); + if (port->dir_GPIO != GPIO_UNDEF) { + gpio_init(port->dir_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); if (!port->dir_Input) { - LL_GPIO_ResetOutputPin(port->dir_GPIOx, port->dir_Pin); + gpio_clear(port->dir_GPIO); } else { - LL_GPIO_SetOutputPin(port->dir_GPIOx, port->dir_Pin); + gpio_set(port->dir_GPIO); } } - pinInit.Pin = port->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_INPUT; - pinInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - pinInit.Pull = LL_GPIO_PULL_DOWN; - LL_GPIO_Init(port->GPIOx, &pinInit); + // pinInit.Pin = port->GPIO_Pin; + // pinInit.Mode = LL_GPIO_MODE_INPUT; + // pinInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; + // pinInit.Pull = LL_GPIO_PULL_DOWN; + // LL_GPIO_Init(port->GPIOx, &pinInit); // Connect EXTI line to TELEMETRY RX pin - LL_SYSCFG_SetEXTISource(port->EXTI_Port, port->EXTI_SysLine); + // LL_SYSCFG_SetEXTISource(port->EXTI_Port, port->EXTI_SysLine); // Configure EXTI for raising edge (start bit; assuming inverted serial) _softserialPort = port; - stm32_exti_enable(port->EXTI_Line, LL_EXTI_TRIGGER_RISING, _softserial_exti); - + // stm32_exti_enable(port->EXTI_Line, LL_EXTI_TRIGGER_RISING, _softserial_exti); + gpio_init_int(port->GPIO, GPIO_IN_PD, GPIO_RISING, _softserial_exti); return true; } static void _softserial_deinit_gpio(const stm32_softserial_rx_port* port) { // Reconfigure pin as input - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); + gpio_init(port->GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + // LL_GPIO_InitTypeDef pinInit; + // LL_GPIO_StructInit(&pinInit); - pinInit.Pin = port->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_INPUT; - LL_GPIO_Init(port->GPIOx, &pinInit); + // pinInit.Pin = port->GPIO_Pin; + // pinInit.Mode = LL_GPIO_MODE_INPUT; + // LL_GPIO_Init(port->GPIOx, &pinInit); } static void _softserial_deinit_rx(const stm32_softserial_rx_port* port) @@ -200,7 +196,7 @@ void stm32_softserial_rx_timer_isr(const stm32_softserial_rx_port* port) rxByte >>= 1; } - if (LL_GPIO_IsInputPinSet(port->GPIOx, port->GPIO_Pin) == 0) + if (!gpio_read(port->GPIO) == 0) rxByte |= 0x80; ++rxBitCount; diff --git a/radio/src/targets/common/arm/stm32/stm32_softserial_driver.h b/radio/src/targets/common/arm/stm32/stm32_softserial_driver.h index 97e5d0482..cf8713b43 100644 --- a/radio/src/targets/common/arm/stm32/stm32_softserial_driver.h +++ b/radio/src/targets/common/arm/stm32/stm32_softserial_driver.h @@ -21,6 +21,7 @@ #include "stm32_serial_driver.h" #include "stm32_pulse_driver.h" +#include "hal/gpio.h" // // RX soft-serial @@ -33,8 +34,7 @@ // struct stm32_softserial_rx_port { - GPIO_TypeDef* GPIOx; - uint32_t GPIO_Pin; + gpio_t GPIO; TIM_TypeDef* TIMx; uint32_t TIM_Freq; IRQn_Type TIM_IRQn; @@ -43,8 +43,7 @@ struct stm32_softserial_rx_port { uint32_t EXTI_Line; // Input/output direction pin - GPIO_TypeDef* dir_GPIOx; - uint32_t dir_Pin; + gpio_t dir_GPIO; uint32_t dir_Input; const stm32_serial_buffer buffer; diff --git a/radio/src/targets/common/arm/stm32/stm32_timer.cpp b/radio/src/targets/common/arm/stm32/stm32_timer.cpp index caabf7a11..4639f28d2 100644 --- a/radio/src/targets/common/arm/stm32/stm32_timer.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_timer.cpp @@ -33,8 +33,18 @@ void stm32_timer_enable_clock(TIM_TypeDef *TIMx) LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM4); } else if (TIMx == TIM5) { LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM5); + } else if (TIMx == TIM6) { + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM6); + } else if (TIMx == TIM7) { + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM7); } else if (TIMx == TIM8) { LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM8); + } else if (TIMx == TIM9) { + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM9); + } else if (TIMx == TIM10) { + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM10); + } else if (TIMx == TIM11) { + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM11); } else if (TIMx == TIM12) { LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM12); } else if (TIMx == TIM13) { @@ -56,15 +66,25 @@ void stm32_timer_disable_clock(TIM_TypeDef *TIMx) LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM4); } else if (TIMx == TIM5) { LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM5); + } else if (TIMx == TIM6) { + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM6); + } else if (TIMx == TIM7) { + LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM7); } else if (TIMx == TIM8) { LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM8); + } else if (TIMx == TIM9) { + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM9); + } else if (TIMx == TIM10) { + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM10); + } else if (TIMx == TIM11) { + LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM11); } else if (TIMx == TIM12) { LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM12); } else if (TIMx == TIM13) { LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM13); } else if (TIMx == TIM14) { LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM14); - } + } } bool stm32_timer_is_clock_enabled(TIM_TypeDef *TIMx) @@ -79,14 +99,24 @@ bool stm32_timer_is_clock_enabled(TIM_TypeDef *TIMx) return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM4) != 0; } else if (TIMx == TIM5) { return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM5) != 0; + } else if (TIMx == TIM6) { + return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM6) != 0; + } else if (TIMx == TIM7) { + return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM7) != 0; } else if (TIMx == TIM8) { return LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM8) != 0; + } else if (TIMx == TIM9) { + return LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM9) != 0; + } else if (TIMx == TIM10) { + return LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM10) != 0; + } else if (TIMx == TIM11) { + return LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM11) != 0; } else if (TIMx == TIM12) { - return LL_APB2_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12) != 0; + return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM12) != 0; } else if (TIMx == TIM13) { - return LL_APB2_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM13) != 0; + return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM13) != 0; } else if (TIMx == TIM14) { - return LL_APB2_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM14) != 0; + return LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM14) != 0; } // not supported diff --git a/radio/src/targets/common/arm/stm32/stm32_usart_driver.cpp b/radio/src/targets/common/arm/stm32/stm32_usart_driver.cpp index 02ab6ce26..8bdaf295f 100644 --- a/radio/src/targets/common/arm/stm32/stm32_usart_driver.cpp +++ b/radio/src/targets/common/arm/stm32/stm32_usart_driver.cpp @@ -20,8 +20,9 @@ */ #include "stm32_usart_driver.h" -#include "stm32_gpio_driver.h" +#include "stm32_gpio.h" #include "stm32_dma.h" +#include "hal/gpio.h" #include @@ -35,6 +36,7 @@ // The new CMSIS can be used when StdPeriph is gone, as it mandates // the old version located in "${STM32LIB_DIR}/CMSIS/Include" // +#if 0 static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { @@ -46,7 +48,7 @@ static inline uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn) return (0U); } } - +#endif static void _enable_usart_irq(const stm32_usart_t* usart) { NVIC_SetPriority(usart->IRQn, usart->IRQ_Prio); @@ -143,27 +145,27 @@ static void disable_usart_clock(USART_TypeDef* USARTx) } -static uint32_t _get_pin_speed(uint32_t baudrate) +static gpio_speed_t _get_pin_speed(uint32_t baudrate) { // 1 Mbps and above if (baudrate >= 1000000) { - return LL_GPIO_SPEED_FREQ_VERY_HIGH; + return GPIO_PIN_SPEED_VERY_HIGH; } // 400kbps and above else if (baudrate >= 400000) { - return LL_GPIO_SPEED_FREQ_HIGH; + return GPIO_PIN_SPEED_HIGH; } // under 400kbps - return LL_GPIO_SPEED_FREQ_LOW; + return GPIO_PIN_SPEED_LOW; } -static uint32_t _get_usart_af(USART_TypeDef* USARTx) +static gpio_af_t _get_usart_af(USART_TypeDef* USARTx) { if (USARTx == USART1 || USARTx == USART2 || USARTx == USART3) { - return LL_GPIO_AF_7; + return GPIO_AF7; } else { - return LL_GPIO_AF_8; + return GPIO_AF8; } } @@ -224,29 +226,21 @@ void stm32_usart_deinit_rx_dma(const stm32_usart_t* usart) bool stm32_usart_init(const stm32_usart_t* usart, const etx_serial_init* params) { // Test if the GPIO pins are in reset state - uint32_t pins = usart->GPIO_Pin; - while(pins != 0) { - uint32_t pin = 1 << POSITION_VAL(pins); - uint32_t mode = LL_GPIO_GetPinMode(usart->GPIOx, pin); - if (mode != LL_GPIO_MODE_INPUT) return false; - pins ^= pin; + if(gpio_get_mode(usart->txGPIO) != GPIO_IN || gpio_get_mode(usart->rxGPIO) != GPIO_IN) + { + return false; } enable_usart_clock(usart->USARTx); LL_USART_DeInit(usart->USARTx); - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Pin = usart->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_ALTERNATE; - pinInit.Speed = _get_pin_speed(params->baudrate); - pinInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - pinInit.Pull = LL_GPIO_PULL_UP; - pinInit.Alternate = _get_usart_af(usart->USARTx); - - stm32_gpio_enable_clock(usart->GPIOx); - LL_GPIO_Init(usart->GPIOx, &pinInit); + gpio_af_t af = _get_usart_af(usart->USARTx); + if (usart->rxGPIO != GPIO_UNDEF) { + gpio_init_af(usart->rxGPIO, af, _get_pin_speed(params->baudrate)); + } + if (usart->txGPIO != GPIO_UNDEF) { + gpio_init_af(usart->txGPIO, af, _get_pin_speed(params->baudrate)); + } LL_USART_InitTypeDef usartInit; LL_USART_StructInit(&usartInit); @@ -330,13 +324,13 @@ void stm32_usart_deinit(const stm32_usart_t* usart) LL_USART_DeInit(usart->USARTx); disable_usart_clock(usart->USARTx); - // Reconfigure pin as output - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - pinInit.Pin = usart->GPIO_Pin; - pinInit.Mode = LL_GPIO_MODE_INPUT; - LL_GPIO_Init(usart->GPIOx, &pinInit); - LL_GPIO_ResetOutputPin(usart->GPIOx, pinInit.Pin); + // Reconfigure pin as input + if (usart->rxGPIO != GPIO_UNDEF) { + gpio_init(usart->rxGPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + } + if (usart->txGPIO != GPIO_UNDEF) { + gpio_init(usart->txGPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + } } void stm32_usart_send_byte(const stm32_usart_t* usart, uint8_t byte) @@ -508,19 +502,6 @@ void stm32_usart_set_baudrate(const stm32_usart_t* usart, uint32_t baudrate) auto periphclk = _get_usart_periph_clock(usart->USARTx); auto oversampling = LL_USART_GetOverSampling(usart->USARTx); LL_USART_SetBaudRate(usart->USARTx, periphclk, oversampling, baudrate); - - // update pin speed accordingly (must be done one-by-one) - uint32_t pin_speed = _get_pin_speed(baudrate); - uint32_t pindef = usart->GPIO_Pin; - - // loop borrowed from LL_GPIO_init() - uint32_t pinpos = POSITION_VAL(pindef); - uint32_t currentpin = 0; - while ((pindef >> pinpos) != 0) { - currentpin = pindef & (1 << pinpos); - if (currentpin) LL_GPIO_SetPinSpeed(usart->GPIOx, currentpin, pin_speed); - pinpos++; - } } void stm32_usart_set_hw_option(const stm32_usart_t* usart, uint32_t option) diff --git a/radio/src/targets/common/arm/stm32/stm32_usart_driver.h b/radio/src/targets/common/arm/stm32/stm32_usart_driver.h index bc9e53627..240126b48 100644 --- a/radio/src/targets/common/arm/stm32/stm32_usart_driver.h +++ b/radio/src/targets/common/arm/stm32/stm32_usart_driver.h @@ -23,6 +23,7 @@ #include #include "hal/serial_driver.h" +#include "hal/gpio.h" #include "stm32_hal_ll.h" typedef void (*pin_setter_t)(uint8_t enable); @@ -31,8 +32,8 @@ struct stm32_usart_t { // USART defs USART_TypeDef* USARTx; - GPIO_TypeDef* GPIOx; - uint32_t GPIO_Pin; + gpio_t txGPIO; + gpio_t rxGPIO; // USART IRQ IRQn_Type IRQn; diff --git a/radio/src/targets/common/arm/stm32/stm32f4xx_hal_conf.h b/radio/src/targets/common/arm/stm32/stm32f4xx_hal_conf.h index 182978049..48f12018d 100644 --- a/radio/src/targets/common/arm/stm32/stm32f4xx_hal_conf.h +++ b/radio/src/targets/common/arm/stm32/stm32f4xx_hal_conf.h @@ -54,7 +54,7 @@ // #define HAL_NOR_MODULE_ENABLED // #define HAL_PCCARD_MODULE_ENABLED // #define HAL_SRAM_MODULE_ENABLED -// #define HAL_SDRAM_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED // #define HAL_HASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED // #define HAL_EXTI_MODULE_ENABLED @@ -101,7 +101,7 @@ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ + #define HSE_STARTUP_TIMEOUT 2000U /*!< Time out for HSE start up, in cycles through a loop, normal values seem to bs around 900 */ #endif /* HSE_STARTUP_TIMEOUT */ /** diff --git a/radio/src/targets/common/arm/stm32/usb_driver.cpp b/radio/src/targets/common/arm/stm32/usb_driver.cpp index 60c29b52b..a369328d2 100644 --- a/radio/src/targets/common/arm/stm32/usb_driver.cpp +++ b/radio/src/targets/common/arm/stm32/usb_driver.cpp @@ -37,6 +37,9 @@ extern "C" { #include "stm32_hal_ll.h" #include "stm32_hal.h" +#include "stm32_gpio.h" + +#include "hal/gpio.h" #include "hal/usb_driver.h" #include "hal.h" @@ -61,7 +64,7 @@ void setSelectedUsbMode(int mode) selectedUsbMode = usbMode(mode); } -#if defined(USB_GPIO_PIN_VBUS) +#if defined(USB_GPIO_VBUS) int usbPlugged() { #if defined(DEBUG_DISABLE_USB) @@ -71,8 +74,8 @@ int usbPlugged() static uint8_t debouncedState = 0; static uint8_t lastState = 0; - uint8_t state = LL_GPIO_IsInputPinSet(USB_GPIO, USB_GPIO_PIN_VBUS); - + // uint8_t state = GPIO_ReadInputDataBit(USB_GPIO, USB_GPIO_PIN_VBUS); + uint8_t state = gpio_read(USB_GPIO_VBUS) ? 1 : 0; if (state == lastState) debouncedState = state; else @@ -92,27 +95,15 @@ extern "C" void OTG_FS_IRQHandler() void usbInit() { - // Initialize hardware - __HAL_RCC_GPIOA_CLK_ENABLE(); - - LL_GPIO_InitTypeDef GPIO_InitStruct; - LL_GPIO_StructInit(&GPIO_InitStruct); - -#if defined(USB_GPIO_PIN_VBUS) - GPIO_InitStruct.Pin = USB_GPIO_PIN_VBUS; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(USB_GPIO, &GPIO_InitStruct); + gpio_init_af(USB_GPIO_DM, USB_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); + gpio_init_af(USB_GPIO_DP, USB_GPIO_AF, GPIO_PIN_SPEED_VERY_HIGH); + +#if defined(USB_GPIO_VBUS) + gpio_init(USB_GPIO_VBUS, GPIO_IN, GPIO_PIN_SPEED_LOW); #endif - - GPIO_InitStruct.Pin = USB_GPIO_PIN_DM | USB_GPIO_PIN_DP; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ALTERNATE; - GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = LL_GPIO_AF_10; // USB - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); + LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_OTGFS); usbDriverStarted = false; } diff --git a/radio/src/targets/common/arm/stm32/vs1053b.cpp b/radio/src/targets/common/arm/stm32/vs1053b.cpp index 0af2634d5..513abdb5d 100644 --- a/radio/src/targets/common/arm/stm32/vs1053b.cpp +++ b/radio/src/targets/common/arm/stm32/vs1053b.cpp @@ -21,8 +21,11 @@ #include "stm32_hal_ll.h" #include "stm32_gpio_driver.h" +#include "stm32_gpio.h" #include "stm32_spi.h" +#include "hal/gpio.h" + #include "opentx.h" #if !defined(SIMU) @@ -310,31 +313,22 @@ void audioSendRiffHeader() audioSpiWriteBuffer(RiffHeader, sizeof(RiffHeader)); } -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) static inline void setMutePin(bool enabled) { - if (enabled) { #if defined(INVERTED_MUTE_PIN) - GPIO_ResetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - GPIO_SetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); + enabled = !enabled; #endif - } else { -#if defined(INVERTED_MUTE_PIN) - GPIO_SetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - GPIO_ResetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#endif - } + gpio_write(AUDIO_MUTE_GPIO, enabled); } static inline bool getMutePin(void) { + bool muted = gpio_read(AUDIO_MUTE_GPIO) ? 1 : 0; #if defined(INVERTED_MUTE_PIN) - return !GPIO_ReadOutputDataBit(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -#else - return GPIO_ReadOutputDataBit(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); + muted = !muted; #endif + return muted; } void audioMute() @@ -374,42 +368,27 @@ void audioUnmute() setMutePin(false); #endif } - -void audioMuteInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = AUDIO_MUTE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(AUDIO_MUTE_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(AUDIO_MUTE_GPIO, AUDIO_MUTE_GPIO_PIN); -} #endif #if defined(PCBX12S) void audioShutdownInit() { - LL_GPIO_InitTypeDef pinInit; - LL_GPIO_StructInit(&pinInit); - - pinInit.Mode = LL_GPIO_MODE_OUTPUT; - pinInit.Pin = AUDIO_SHUTDOWN_GPIO_PIN; - LL_GPIO_Init(AUDIO_SHUTDOWN_GPIO, &pinInit); + gpio_init(AUDIO_SHUTDOWN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); // we never RESET it, there is a 2s delay on STARTUP - LL_GPIO_SetOutputPin(AUDIO_SHUTDOWN_GPIO, AUDIO_SHUTDOWN_GPIO_PIN); + gpio_set(AUDIO_SHUTDOWN_GPIO); } #endif void audioInit() { -#if defined(AUDIO_MUTE_GPIO_PIN) - audioMuteInit(); +#if defined(AUDIO_MUTE_GPIO) + // Mute before init anything + gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + setMutePin(true); #endif - #if defined(PCBX12S) +#if defined(PCBX12S) audioShutdownInit(); #endif @@ -451,7 +430,7 @@ void audioConsumeCurrentBuffer() } if (currentBuffer) { -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) audioUnmute(); #endif uint32_t written = audioSpiWriteData(currentBuffer, currentSize); @@ -463,7 +442,7 @@ void audioConsumeCurrentBuffer() currentSize = 0; } } -#if defined(AUDIO_MUTE_GPIO_PIN) +#if defined(AUDIO_MUTE_GPIO) else { audioMute(); } diff --git a/radio/src/targets/horus/CMakeLists.txt b/radio/src/targets/horus/CMakeLists.txt index c9424dd38..ef8c895a8 100644 --- a/radio/src/targets/horus/CMakeLists.txt +++ b/radio/src/targets/horus/CMakeLists.txt @@ -244,11 +244,11 @@ set(FIRMWARE_TARGET_SRC board.cpp backlight_driver.cpp led_driver.cpp - sdram_driver.c ) set(FIRMWARE_SRC ${FIRMWARE_SRC} + targets/common/arm/stm32/sdram_driver.cpp targets/common/arm/stm32/rotary_encoder_driver.cpp targets/common/arm/stm32/heartbeat_driver.cpp targets/common/arm/stm32/ads79xx.cpp diff --git a/radio/src/targets/horus/backlight_driver.cpp b/radio/src/targets/horus/backlight_driver.cpp index 19b3bcc92..197a3d226 100644 --- a/radio/src/targets/horus/backlight_driver.cpp +++ b/radio/src/targets/horus/backlight_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "opentx_types.h" #include "board.h" @@ -29,25 +33,14 @@ void backlightInit() { // PIN init - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); #if defined(KEYS_BACKLIGHT_GPIO) - GPIO_InitStructure.GPIO_Pin = KEYS_BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(KEYS_BACKLIGHT_GPIO, &GPIO_InitStructure); + gpio_init(KEYS_BACKLIGHT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif // TIMER init + stm32_timer_enable_clock(BACKLIGHT_TIMER); #if defined(PCBX12S) && PCBREV >= 13 BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 10000 - 1; // 1kHz @@ -89,10 +82,10 @@ void backlightEnable(uint8_t dutyCycle) #if defined(KEYS_BACKLIGHT_GPIO) && !defined(BOOT) if (dutyCycle == 0 || g_eeGeneral.keysBacklight == 0) { - GPIO_ResetBits(KEYS_BACKLIGHT_GPIO, KEYS_BACKLIGHT_GPIO_PIN); + gpio_clear(KEYS_BACKLIGHT_GPIO); } else { - GPIO_SetBits(KEYS_BACKLIGHT_GPIO, KEYS_BACKLIGHT_GPIO_PIN); + gpio_set(KEYS_BACKLIGHT_GPIO); } #endif diff --git a/radio/src/targets/horus/board.cpp b/radio/src/targets/horus/board.cpp index bedfc8ef3..51b837db5 100644 --- a/radio/src/targets/horus/board.cpp +++ b/radio/src/targets/horus/board.cpp @@ -19,11 +19,16 @@ * GNU General Public License for more details. */ +#include "stm32_hal.h" +#include "stm32_hal_ll.h" +#include "stm32_gpio.h" + #include "hal/adc_driver.h" #include "hal/trainer_driver.h" #include "hal/switch_driver.h" #include "hal/rotary_encoder.h" #include "hal/usb_driver.h" +#include "hal/gpio.h" #include "board.h" #include "boards/generic_stm32/module_ports.h" @@ -51,37 +56,8 @@ bool boardBacklightOn = false; void boardInit() { - RCC_AHB1PeriphClockCmd(PWR_RCC_AHB1Periph | - PCBREV_RCC_AHB1Periph | - LED_RCC_AHB1Periph | - LCD_RCC_AHB1Periph | - BACKLIGHT_RCC_AHB1Periph | - KEYS_BACKLIGHT_RCC_AHB1Periph | - SD_RCC_AHB1Periph | - AUDIO_RCC_AHB1Periph | - TELEMETRY_RCC_AHB1Periph | - BT_RCC_AHB1Periph | - AUDIO_RCC_AHB1Periph | - HAPTIC_RCC_AHB1Periph | - INTMODULE_RCC_AHB1Periph | - EXTMODULE_RCC_AHB1Periph | - SPORT_UPDATE_RCC_AHB1Periph, - ENABLE); - - RCC_APB1PeriphClockCmd(ROTARY_ENCODER_RCC_APB1Periph | - AUDIO_RCC_APB1Periph | - TELEMETRY_RCC_APB1Periph | - AUDIO_RCC_APB1Periph | - BACKLIGHT_RCC_APB1Periph, - ENABLE); - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | - LCD_RCC_APB2Periph | - HAPTIC_RCC_APB2Periph | - TELEMETRY_RCC_APB2Periph | - BT_RCC_APB2Periph | - BACKLIGHT_RCC_APB2Periph, - ENABLE); + LL_AHB1_GRP1_EnableClock(LCD_RCC_AHB1Periph); + LL_APB2_GRP1_EnableClock(LCD_RCC_APB2Periph); #if defined(RADIO_FAMILY_T16) void board_set_bor_level(); @@ -140,7 +116,7 @@ void boardInit() #if defined(DEBUG) - DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP|DBGMCU_TIM1_STOP|DBGMCU_TIM2_STOP|DBGMCU_TIM3_STOP|DBGMCU_TIM4_STOP|DBGMCU_TIM5_STOP|DBGMCU_TIM6_STOP|DBGMCU_TIM7_STOP|DBGMCU_TIM8_STOP|DBGMCU_TIM9_STOP|DBGMCU_TIM10_STOP|DBGMCU_TIM11_STOP|DBGMCU_TIM12_STOP|DBGMCU_TIM13_STOP|DBGMCU_TIM14_STOP, ENABLE); + // DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP|DBGMCU_TIM1_STOP|DBGMCU_TIM2_STOP|DBGMCU_TIM3_STOP|DBGMCU_TIM4_STOP|DBGMCU_TIM5_STOP|DBGMCU_TIM6_STOP|DBGMCU_TIM7_STOP|DBGMCU_TIM8_STOP|DBGMCU_TIM9_STOP|DBGMCU_TIM10_STOP|DBGMCU_TIM11_STOP|DBGMCU_TIM12_STOP|DBGMCU_TIM13_STOP|DBGMCU_TIM14_STOP, ENABLE); #endif ledInit(); @@ -176,14 +152,8 @@ void boardOff() #if defined(PCBX12S) // Shutdown the Audio amp - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = AUDIO_SHUTDOWN_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(AUDIO_SHUTDOWN_GPIO, &GPIO_InitStructure); - GPIO_ResetBits(AUDIO_SHUTDOWN_GPIO, AUDIO_SHUTDOWN_GPIO_PIN); + gpio_init(AUDIO_SHUTDOWN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_clear(AUDIO_SHUTDOWN_GPIO); #endif // Shutdown the Haptic diff --git a/radio/src/targets/horus/board.h b/radio/src/targets/horus/board.h index 4cb5c7581..c3fa6ef13 100644 --- a/radio/src/targets/horus/board.h +++ b/radio/src/targets/horus/board.h @@ -22,6 +22,8 @@ #ifndef _BOARD_H_ #define _BOARD_H_ +//#include "stm32_hal.h" +//#include "stm32_hal_ll.h" #include "definitions.h" #include "opentx_constants.h" @@ -100,9 +102,6 @@ void flashWrite(uint32_t * address, const uint32_t * buffer); uint32_t isFirmwareStart(const uint8_t * buffer); uint32_t isBootloaderStart(const uint8_t * buffer); -// SDRAM driver -void SDRAM_Init(); - #if defined(INTERNAL_MODULE_PXX1) || defined(INTERNAL_MODULE_PXX2) #define HARDWARE_INTERNAL_RAS #endif @@ -118,21 +117,20 @@ void SDRAM_Init(); // #define INTERNAL_MODULE_ON() \ do { \ - GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); \ + gpio_set(INTMODULE_PWR_GPIO); \ delay_ms(1); \ } while (0) #else // Just turn the modue ON for all other targets -#define INTERNAL_MODULE_ON() \ - GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) +#define INTERNAL_MODULE_ON() gpio_set(INTMODULE_PWR_GPIO) #endif -#define INTERNAL_MODULE_OFF() GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) -#define EXTERNAL_MODULE_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) -#define EXTERNAL_MODULE_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) +#define INTERNAL_MODULE_OFF() gpio_clear(INTMODULE_PWR_GPIO) +#define EXTERNAL_MODULE_ON() gpio_set(EXTMODULE_PWR_GPIO) +#define EXTERNAL_MODULE_OFF() gpio_clear(EXTMODULE_PWR_GPIO) #if !defined(PXX2) #define IS_PXX2_INTERNAL_ENABLED() (false) diff --git a/radio/src/targets/horus/hal.h b/radio/src/targets/horus/hal.h index a5b7e8c48..4b7822576 100644 --- a/radio/src/targets/horus/hal.h +++ b/radio/src/targets/horus/hal.h @@ -77,10 +77,9 @@ #endif // Rotary Encoder -#define ROTARY_ENCODER_RCC_APB1Periph RCC_APB1Periph_TIM12 #define ROTARY_ENCODER_GPIO GPIOH -#define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_11 // PH.11 -#define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_10 // PH.10 +#define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_11 // PH.11 +#define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_10 // PH.10 #define ROTARY_ENCODER_POSITION() ((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x03) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_11 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_10 @@ -306,7 +305,7 @@ #define PWM_STICKS #define PWM_TIMER TIM5 #define PWM_GPIO GPIOA - #define PWM_GPIO_AF GPIO_AF_TIM5 + #define PWM_GPIO_AF GPIO_AF2 #define PWM_IRQHandler TIM5_IRQHandler #define PWM_IRQn TIM5_IRQn #define PWM_GPIOA_PINS (ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_RV) @@ -372,158 +371,101 @@ // Power #if defined(RADIO_T18) -#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOB -#define PWR_ON_GPIO GPIOJ -#define PWR_ON_GPIO_PIN GPIO_Pin_1 // PJ.01 -#define PWR_SWITCH_GPIO GPIOJ -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_0 // PJ.00 -#define PWR_EXTRA_SWITCH_GPIO GPIOB -#define PWR_EXTRA_SWITCH_GPIO_PIN GPIO_Pin_0 // PB.00 + #define PWR_ON_GPIO GPIO_PIN(GPIOJ, 1) // PJ.01 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOJ, 0) // PJ.00 + #define PWR_EXTRA_SWITCH_GPIO GPIO_PIN(GPIOB, 0) // PB.00 #else -#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOJ -#define PWR_ON_GPIO GPIOJ -#define PWR_ON_GPIO_PIN GPIO_Pin_1 // PJ.01 -#define PWR_SWITCH_GPIO GPIOJ -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_0 // PJ.00 + #define PWR_ON_GPIO GPIO_PIN(GPIOJ, 1) // PJ.01 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOJ, 0) // PJ.00 #endif // USB Charger #if defined(USB_CHARGER) -#define USB_CHARGER_RCC_AHB1Periph RCC_AHB1Periph_GPIOG -#define USB_CHARGER_GPIO GPIOG -#define USB_CHARGER_GPIO_PIN GPIO_Pin_11 // PG.11 -#define USB_USBDet_GPIO_PIN GPIO_Pin_13 // PG.13 -#else -#define USB_CHARGER_RCC_AHB1Periph 0 + #define USB_CHARGER_GPIO GPIO_PIN(GPIOG, 11) // PG.11 + #define USB_USBDet_GPIO GPIO_PIN(GPIOG, 13) // PG.13 #endif // S.Port update connector #if defined(RADIO_FAMILY_T16) - #define SPORT_MAX_BAUDRATE 400000 + #define SPORT_MAX_BAUDRATE 400000 #else - #define SPORT_MAX_BAUDRATE 250000 // < 400000 + #define SPORT_MAX_BAUDRATE 250000 // < 400000 #endif #if defined(PCBX10) && !defined(RADIO_FAMILY_T16) - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOH - #define SPORT_UPDATE_PWR_GPIO GPIOH - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_13 // PH.13 -#else - #define SPORT_UPDATE_RCC_AHB1Periph 0 + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOH, 13) // PH.13 #endif // PCBREV #if defined(PCBX10) - #define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOA - #define PCBREV_GPIO GPIOH - #define PCBREV_GPIO_PIN (GPIO_Pin_7 | GPIO_Pin_8) // PH.07 | PH.08 - #define PCBREV_TOUCH_GPIO GPIOA - #define PCBREV_TOUCH_GPIO_PIN GPIO_Pin_6 // PA.06 + #define PCBREV_GPIO_1 GPIO_PIN(GPIOH, 7) // PH.07 + #define PCBREV_GPIO_2 GPIO_PIN(GPIOH, 8) // PH.08 + #define PCBREV_TOUCH_GPIO GPIO_PIN(GPIOA, 6) // PA.06 + #define PCBREV_VALUE() ((gpio_read(PCBREV_GPIO_1) | gpio_read(PCBREV_GPIO_2)) >> 7) #define PCBREV_TOUCH_GPIO_PULL_UP - #define PCBREV_VALUE() ((GPIO_ReadInputDataBit(PCBREV_GPIO, GPIO_Pin_7) + (GPIO_ReadInputDataBit(PCBREV_GPIO, GPIO_Pin_8) << 1)) * GPIO_ReadInputDataBit(PCBREV_TOUCH_GPIO, GPIO_Pin_6)) #else - #define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOI - #define PCBREV_GPIO GPIOI - #define PCBREV_GPIO_PIN GPIO_Pin_11 // PI.11 - #define PCBREV_VALUE() GPIO_ReadInputDataBit(PCBREV_GPIO, PCBREV_GPIO_PIN) + #define PCBREV_GPIO GPIO_PIN(GPIOI, 11) // PI.11 + #define PCBREV_VALUE() (gpio_read(PCBREV_GPIO) >> 11) #endif // Led #define STATUS_LEDS #if defined(PCBX12S) - #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOI - #define LED_GPIO GPIOI - #define LED_GPIO_PIN GPIO_Pin_5 // PI.05 + #define LED_GPIO GPIO_PIN(GPIOI, 5) // PI.05 #elif defined(PCBX10) - #define LED_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define LED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_2 - #define LED_GREEN_GPIO_PIN GPIO_Pin_4 - #define LED_BLUE_GPIO_PIN GPIO_Pin_5 - #define LED_GPIO_PIN (LED_RED_GPIO_PIN | LED_GREEN_GPIO_PIN | LED_BLUE_GPIO_PIN) + #define LED_RED_GPIO GPIO_PIN(GPIOE, 2) // PE.02 + #define LED_GREEN_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 5) // PE.05 #endif // Serial Port (DEBUG) #if defined(AUX_SERIAL) - #define AUX_SERIAL_GPIO GPIOB - #define AUX_SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 - #define AUX_SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 - #define AUX_SERIAL_GPIO_PinSource_TX GPIO_PinSource10 - #define AUX_SERIAL_GPIO_PinSource_RX GPIO_PinSource11 - #define AUX_SERIAL_GPIO_AF GPIO_AF_USART3 - #define AUX_SERIAL_GPIO_AF_LL LL_GPIO_AF_7 + #define AUX_SERIAL_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 + #define AUX_SERIAL_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 #define AUX_SERIAL_USART USART3 #define AUX_SERIAL_USART_IRQHandler USART3_IRQHandler #define AUX_SERIAL_USART_IRQn USART3_IRQn #define AUX_SERIAL_DMA_TX DMA1 - #define AUX_SERIAL_DMA_Stream_TX DMA1_Stream3 - #define AUX_SERIAL_DMA_Stream_TX_LL LL_DMA_STREAM_3 - #define AUX_SERIAL_DMA_Channel_TX LL_DMA_CHANNEL_4 + #define AUX_SERIAL_DMA_TX_STREAM LL_DMA_STREAM_3 + #define AUX_SERIAL_DMA_TX_CHANNEL LL_DMA_CHANNEL_4 #define AUX_SERIAL_DMA_RX DMA1 - #define AUX_SERIAL_DMA_Stream_RX DMA1_Stream1 - #define AUX_SERIAL_DMA_Stream_RX_LL LL_DMA_STREAM_1 - #define AUX_SERIAL_DMA_Channel_RX LL_DMA_CHANNEL_4 + #define AUX_SERIAL_DMA_RX_STREAM LL_DMA_STREAM_1 + #define AUX_SERIAL_DMA_RX_CHANNEL LL_DMA_CHANNEL_4 #if defined(RADIO_TX16S) - #define AUX_SERIAL_PWR_GPIO GPIOA - #define AUX_SERIAL_PWR_GPIO_PIN GPIO_Pin_15 // PA.15 + #define AUX_SERIAL_PWR_GPIO GPIO_PIN(GPIOA, 15) // PA.15 #endif #endif #if defined(AUX2_SERIAL) #if defined(PCBX12S) - #define AUX2_SERIAL_RCC_AHB1Periph RCC_AHB1Periph_GPIOA #define AUX2_SERIAL_USART UART4 - #define AUX2_SERIAL_GPIO_AF GPIO_AF_UART4 - #define AUX2_SERIAL_GPIO_AF_LL LL_GPIO_AF_8 #define AUX2_SERIAL_USART_IRQn UART4_IRQn - #define AUX2_SERIAL_USART_IRQHandler UART4_IRQHandler - #define AUX2_SERIAL_GPIO GPIOA - #define AUX2_SERIAL_GPIO_PIN_TX GPIO_Pin_0 // PA.00 - #define AUX2_SERIAL_GPIO_PIN_RX GPIO_Pin_1 // PA.01 - #define AUX2_SERIAL_GPIO_TX_PinSource GPIO_PinSource0 - #define AUX2_SERIAL_GPIO_RX_PinSource GPIO_PinSource1 + #define AUX2_SERIAL_TX_GPIO GPIO_PIN(GPIOA, 0) // PA.00 + #define AUX2_SERIAL_RX_GPIO GPIO_PIN(GPIOA, 1) // PA.01 #define AUX2_SERIAL_DMA_RX DMA1 - #define AUX2_SERIAL_DMA_Stream_RX DMA1_Stream2 - #define AUX2_SERIAL_DMA_Channel_RX LL_DMA_CHANNEL_4 - #define AUX2_SERIAL_DMA_Stream_RX_LL LL_DMA_STREAM_2 + #define AUX2_SERIAL_DMA_RX_STREAM LL_DMA_STREAM_2 + #define AUX2_SERIAL_DMA_RX_CHANNEL LL_DMA_CHANNEL_4 #else - #define AUX2_SERIAL_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_DMA2) #define AUX2_SERIAL_USART USART6 - #define AUX2_SERIAL_GPIO_AF GPIO_AF_USART6 - #define AUX2_SERIAL_GPIO_AF_LL LL_GPIO_AF_8 #define AUX2_SERIAL_USART_IRQn USART6_IRQn - #define AUX2_SERIAL_USART_IRQHandler USART6_IRQHandler #define AUX2_SERIAL_GPIO GPIOG - #define AUX2_SERIAL_GPIO_PIN_TX GPIO_Pin_14 // PG.14 - #define AUX2_SERIAL_GPIO_PIN_RX GPIO_Pin_9 // PG.09 - #define AUX2_SERIAL_GPIO_PinSource_TX GPIO_PinSource14 - #define AUX2_SERIAL_GPIO_PinSource_RX GPIO_PinSource9 + #define AUX2_SERIAL_TX_GPIO GPIO_PIN(GPIOG, 14) // PG.14 + #define AUX2_SERIAL_RX_GPIO GPIO_PIN(GPIOG, 9) // PG.09 #define AUX2_SERIAL_DMA_RX DMA2 - #define AUX2_SERIAL_DMA_Stream_RX DMA2_Stream1 // or DMA2_Stream2 - #define AUX2_SERIAL_DMA_Channel_RX LL_DMA_CHANNEL_5 - #define AUX2_SERIAL_DMA_Stream_RX_LL LL_DMA_STREAM_1 + #define AUX2_SERIAL_DMA_RX_STREAM LL_DMA_STREAM_1 // or stream 2 + #define AUX2_SERIAL_DMA_RX_CHANNEL LL_DMA_CHANNEL_5 #if !defined(RADIO_T18) - #define AUX2_SERIAL_PWR_GPIO GPIOB - #define AUX2_SERIAL_PWR_GPIO_PIN GPIO_Pin_0 // PB.00 + #define AUX2_SERIAL_PWR_GPIO GPIO_PIN(GPIOB, 0) // PB.00 #endif #endif -#else // AUX2_SERIAL - #define AUX2_SERIAL_RCC_AHB1Periph 0 #endif // Telemetry -#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) -#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_RCC_APB2Periph RCC_APB2Periph_TIM11 -#define TELEMETRY_DIR_GPIO GPIOD -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 +#define TELEMETRY_DIR_GPIO GPIO_PIN(GPIOD, 4) // PD.04 #define TELEMETRY_SET_INPUT 0 #define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_TX_GPIO GPIO_PIN(GPIOD, 5) // PD.05 +#define TELEMETRY_RX_GPIO GPIO_PIN(GPIOD, 6) // PD.06 #define TELEMETRY_USART USART2 #define TELEMETRY_DMA DMA1 #if defined(PCBX12S) @@ -559,23 +501,18 @@ #define EXTI4_IRQ_Priority 5 // USB -#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA -#define USB_GPIO GPIOA -#define USB_GPIO_PIN_VBUS LL_GPIO_PIN_9 // PA.09 -#define USB_GPIO_PIN_DM LL_GPIO_PIN_11 // PA.11 -#define USB_GPIO_PIN_DP LL_GPIO_PIN_12 // PA.12 -#define USB_GPIO_AF GPIO_AF_OTG1_FS +#define USB_GPIO_VBUS GPIO_PIN(GPIOA, 9) // PA.09 +#define USB_GPIO_DM GPIO_PIN(GPIOA, 11) // PA.11 +#define USB_GPIO_DP GPIO_PIN(GPIOA, 12) // PA.12 +#define USB_GPIO_AF GPIO_AF10 // LCD -#define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOK | RCC_AHB1Periph_DMA2D) -#define LCD_RCC_APB1Periph 0 -#define LCD_RCC_APB2Periph RCC_APB2Periph_LTDC +#define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA2D +#define LCD_RCC_APB2Periph LL_APB2_GRP1_PERIPH_LTDC #if defined(PCBX12S) - #define LCD_GPIO_NRST GPIOF - #define LCD_GPIO_PIN_NRST LL_GPIO_PIN_10 // PF.10 + #define LCD_GPIO_NRST GPIO_PIN(GPIOF, 10) // PF.10 #elif defined(PCBX10) - #define LCD_GPIO_NRST GPIOI - #define LCD_GPIO_PIN_NRST LL_GPIO_PIN_10 // PI.10 + #define LCD_GPIO_NRST GPIO_PIN(GPIOI, 10) // PI.10 #endif #if defined(PCBX10) && !defined(RADIO_T18) #define LCD_VERTICAL_INVERT @@ -585,59 +522,38 @@ // Backlight #if defined(PCBX12S) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define BACKLIGHT_GPIO GPIOA #if PCBREV >= 13 - #define BACKLIGHT_TIMER TIM5 - #define BACKLIGHT_GPIO_PIN GPIO_Pin_3 // PA.03 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource3 - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM5 - #define BACKLIGHT_RCC_APB2Periph 0 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM5 - #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) + #define BACKLIGHT_TIMER TIM5 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 3) // PA.03 + #define BACKLIGHT_GPIO_AF GPIO_AF2 + #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #else - #define BACKLIGHT_TIMER TIM8 - #define BACKLIGHT_GPIO_PIN GPIO_Pin_5 // PA.05 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource5 - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM8 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM8 - #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define BACKLIGHT_TIMER TIM8 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 5) // PA.05 + #define BACKLIGHT_GPIO_AF GPIO_AF3 + #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #endif #elif defined(PCBX10) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define BACKLIGHT_GPIO GPIOB - #define BACKLIGHT_TIMER TIM8 - #define BACKLIGHT_GPIO_PIN GPIO_Pin_1 // PB.01 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource1 - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM8 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM8 - #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define BACKLIGHT_TIMER TIM8 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOB, 1) // PB.01 + #define BACKLIGHT_GPIO_AF GPIO_AF3 + #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #endif + #if defined(RADIO_T18) - #define KEYS_BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOC - #define KEYS_BACKLIGHT_GPIO GPIOC - #define KEYS_BACKLIGHT_GPIO_PIN GPIO_Pin_4 // PC.04 - #define KEYS_BACKLIGHT_GPIO_PinSource GPIO_PinSource4 -#else - #define KEYS_BACKLIGHT_RCC_AHB1Periph 0 + #define KEYS_BACKLIGHT_GPIO GPIO_PIN(GPIOC, 4) // PC.04 #endif // SD -#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) -#define SD_RCC_APB1Periph 0 -#define SD_PRESENT_GPIO GPIOC -#define SD_PRESENT_GPIO_PIN GPIO_Pin_5 // PC.05 -#define SD_PRESENT_LL_GPIO_PIN LL_GPIO_PIN_5 // PC.05 -#define SD_SDIO_DMA DMA2 -#define SD_SDIO_DMA_STREAM DMA2_Stream3 // or Stream6 -#define SD_SDIO_DMA_CHANNEL LL_DMA_CHANNEL_4 -#define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn -#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler -#define SD_SDIO_CLK_DIV(fq) ((48000000 / (fq)) - 2) -#define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) -#define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) +#define SD_PRESENT_GPIO GPIO_PIN(GPIOC, 5) // PC.05 +#define SD_SDIO_DMA DMA2 +#define SD_SDIO_DMA_STREAM DMA2_Stream3 // or Stream6 +#define SD_SDIO_DMA_CHANNEL LL_DMA_CHANNEL_4 +#define SD_SDIO_DMA_IRQn DMA2_Stream3_IRQn +#define SD_SDIO_DMA_IRQHANDLER DMA2_Stream3_IRQHandler +#define SD_SDIO_CLK_DIV(fq) ((48000000 / (fq)) - 2) +#define SD_SDIO_INIT_CLK_DIV SD_SDIO_CLK_DIV(400000) +#define SD_SDIO_TRANSFER_CLK_DIV SD_SDIO_CLK_DIV(24000000) #define STORAGE_USE_SDIO // SPI NOR Flash @@ -695,38 +611,26 @@ // Audio #if defined(PCBX12S) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOH) - #define AUDIO_RCC_APB1Periph RCC_APB1Periph_SPI2 - #define AUDIO_SHUTDOWN_GPIO GPIOI - #define AUDIO_SHUTDOWN_GPIO_PIN GPIO_Pin_9 // PI.09 + #define AUDIO_SHUTDOWN_GPIO GPIO_PIN(GPIOI, 9) // PI.09 #define AUDIO_XDCS_GPIO GPIOI - #define AUDIO_XDCS_GPIO_PIN GPIO_Pin_0 // PI.00 + #define AUDIO_XDCS_GPIO_PIN LL_GPIO_PIN_0 // PI.00 #define AUDIO_CS_GPIO GPIOH - #define AUDIO_CS_GPIO_PIN GPIO_Pin_13 // PH.13 + #define AUDIO_CS_GPIO_PIN LL_GPIO_PIN_13 // PH.13 #define AUDIO_DREQ_GPIO GPIOH - #define AUDIO_DREQ_GPIO_PIN GPIO_Pin_14 // PH.14 + #define AUDIO_DREQ_GPIO_PIN LL_GPIO_PIN_14 // PH.14 #define AUDIO_RST_GPIO GPIOH - #define AUDIO_RST_GPIO_PIN GPIO_Pin_15 // PH.15 + #define AUDIO_RST_GPIO_PIN LL_GPIO_PIN_15 // PH.15 #define AUDIO_SPI SPI2 - #define AUDIO_SPI_GPIO_AF GPIO_AF_SPI2 + #define AUDIO_SPI_GPIO_AF LL_GPIO_AF_5 #define AUDIO_SPI_SCK_GPIO GPIOI - #define AUDIO_SPI_SCK_GPIO_PIN GPIO_Pin_1 // PI.01 - #define AUDIO_SPI_SCK_GPIO_PinSource GPIO_PinSource1 + #define AUDIO_SPI_SCK_GPIO_PIN LL_GPIO_PIN_1 // PI.01 #define AUDIO_SPI_MISO_GPIO GPIOI - #define AUDIO_SPI_MISO_GPIO_PIN GPIO_Pin_2 // PI.02 - #define AUDIO_SPI_MISO_GPIO_PinSource GPIO_PinSource2 + #define AUDIO_SPI_MISO_GPIO_PIN LL_GPIO_PIN_2 // PI.02 #define AUDIO_SPI_MOSI_GPIO GPIOI - #define AUDIO_SPI_MOSI_GPIO_PIN GPIO_Pin_3 // PI.03 - #define AUDIO_SPI_MOSI_GPIO_PinSource GPIO_PinSource3 + #define AUDIO_SPI_MOSI_GPIO_PIN LL_GPIO_PIN_3 // PI.03 #elif defined (PCBX10) - #define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) - #define AUDIO_MUTE_GPIO GPIOA - #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_7 // PA.07 - #define AUDIO_OUTPUT_GPIO GPIOA - #define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 - #define AUDIO_GPIO_AF GPIO_AF_DAC1 - #define AUDIO_GPIO_PinSource GPIO_PinSource4 + #define AUDIO_MUTE_GPIO GPIO_PIN(GPIOA, 7) // PA.07 + #define AUDIO_OUTPUT_GPIO GPIO_PIN(GPIOA, 4) // PA.04 #define AUDIO_DMA_Stream DMA1_Stream5 #define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn #define AUDIO_TIM_IRQn TIM6_DAC_IRQn @@ -750,15 +654,11 @@ #if defined(HARDWARE_TOUCH) #define TOUCH_I2C_BUS I2C_Bus_1 #define TOUCH_I2C_CLK_RATE 400000 - - #define TOUCH_INT_GPIO GPIOH - #define TOUCH_INT_GPIO_PIN LL_GPIO_PIN_2 // PH.02 - - #define TOUCH_RST_GPIO GPIOF + #define TOUCH_INT_GPIO GPIO_PIN(GPIOH, 2) // PH.02 #if defined(PCBX12S) - #define TOUCH_RST_GPIO_PIN LL_GPIO_PIN_7 // PF.7 + #define TOUCH_RST_GPIO GPIO_PIN(GPIOF, 7) // PF.7 #else - #define TOUCH_RST_GPIO_PIN LL_GPIO_PIN_10 // PF.10 + #define TOUCH_RST_GPIO GPIO_PIN(GPIOF, 10) // PF.10 #endif #define TOUCH_INT_EXTI_Line LL_EXTI_LINE_2 #define TOUCH_INT_EXTI_Port LL_SYSCFG_EXTI_PORTH @@ -816,158 +716,113 @@ // Haptic #define HAPTIC_PWM #if defined(PCBX12S) - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM9EN - #define HAPTIC_GPIO GPIOA - #define HAPTIC_GPIO_PIN GPIO_Pin_2 + #define HAPTIC_GPIO GPIO_PIN(GPIOA, 2) // PA.02 #define HAPTIC_GPIO_TIMER TIM9 - #define HAPTIC_GPIO_AF GPIO_AF_TIM9 - #define HAPTIC_GPIO_PinSource GPIO_PinSource2 + #define HAPTIC_GPIO_AF GPIO_AF3 #define HAPTIC_TIMER_OUTPUT_ENABLE TIM_CCER_CC1E #define HAPTIC_TIMER_MODE TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 #define HAPTIC_TIMER_COMPARE_VALUE HAPTIC_GPIO_TIMER->CCR1 #elif defined(PCBX10) - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM9EN - #define HAPTIC_GPIO GPIOE - #define HAPTIC_GPIO_PIN GPIO_Pin_6 // PE.06 + #define HAPTIC_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #define HAPTIC_GPIO_TIMER TIM9 - #define HAPTIC_GPIO_AF GPIO_AF_TIM9 - #define HAPTIC_GPIO_PinSource GPIO_PinSource6 + #define HAPTIC_GPIO_AF GPIO_AF3 #define HAPTIC_TIMER_OUTPUT_ENABLE TIM_CCER_CC2E #define HAPTIC_TIMER_MODE TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 #define HAPTIC_TIMER_COMPARE_VALUE HAPTIC_GPIO_TIMER->CCR2 // FlySky Hall Sticks #define FLYSKY_HALL_SERIAL_USART UART4 - #define FLYSKY_HALL_SERIAL_GPIO GPIOA #define FLYSKY_HALL_DMA_Channel LL_DMA_CHANNEL_4 - #define FLYSKY_HALL_SERIAL_TX_GPIO_PIN LL_GPIO_PIN_0 // PA.00 - #define FLYSKY_HALL_SERIAL_RX_GPIO_PIN LL_GPIO_PIN_1 // PA.01 - #define FLYSKY_HALL_SERIAL_GPIO_AF LL_GPIO_AF_8 - #define FLYSKY_HALL_SERIAL_USART_IRQHandler UART4_IRQHandler + #define FLYSKY_HALL_SERIAL_TX_GPIO GPIO_PIN(GPIOA, 0) // PA.00 + #define FLYSKY_HALL_SERIAL_RX_GPIO GPIO_PIN(GPIOA, 1) // PA.01 #define FLYSKY_HALL_SERIAL_USART_IRQn UART4_IRQn #define FLYSKY_HALL_SERIAL_DMA DMA1 #define FLYSKY_HALL_DMA_Stream_RX LL_DMA_STREAM_2 // #define FLYSKY_HALL_DMA_Stream_TX LL_DMA_STREAM_4 - #endif // Internal PXX1 Module: // -> let's assume all internal XJT modules used are either X10 or X12S type #define EXTERNAL_ANTENNA -#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) -#define INTMODULE_PWR_GPIO GPIOA -#define INTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PA.08 -#define INTMODULE_GPIO GPIOB -#define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_6 // PB.06 -#define INTMODULE_RX_GPIO_PIN LL_GPIO_PIN_7 // PB.07 +#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOA, 8) // PA.08 +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 6) // PB.06 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 7) // PB.07 #define INTMODULE_USART USART1 -#define INTMODULE_GPIO_AF LL_GPIO_AF_7 #define INTMODULE_USART_IRQn USART1_IRQn -#define INTMODULE_USART_IRQHandler USART1_IRQHandler #define INTMODULE_DMA DMA2 #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler -#define INTMODULE_DMA_FLAG_TC DMA_FLAG_TCIF7 #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 #define INTMODULE_RX_DMA DMA2 #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_2 #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 #if defined(PCBX12S) - #define INTMODULE_BOOTCMD_GPIO GPIOC - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_2 // PC.02 + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOC, 2) // PC.02 #elif defined(PCBX10) - #define INTMODULE_BOOTCMD_GPIO GPIOI - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_9 // PI.09 + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOI, 9) // PI.09 #endif #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET -#define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); // External Module -#define EXTMODULE_PWR_GPIO GPIOB -#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_3 // PB.03 -#define EXTERNAL_MODULE_PWR_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) +#define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOB, 3) // PB.03 +#define EXTERNAL_MODULE_PWR_OFF() gpio_clear(EXTMODULE_PWR_GPIO) #if defined(PCBX10) && defined(PCBREV_EXPRESS) - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) - #define EXTMODULE_TX_GPIO GPIOB - #define EXTMODULE_USART_GPIO EXTMODULE_TX_GPIO - #define EXTMODULE_TX_GPIO_PIN LL_GPIO_PIN_10 // PB.10 (TIM2_CH3) - #define EXTMODULE_RX_GPIO_PIN LL_GPIO_PIN_11 // PB.11 - #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF_TIM2 + #define EXTMODULE_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 (TIM2_CH3) + #define EXTMODULE_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 + #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF1 #define EXTMODULE_TIMER TIM2 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 #define EXTMODULE_TIMER_32BITS - #define EXTMODULE_TIMER_DMA_SIZE (DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1) #define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define EXTMODULE_TIMER_IRQn TIM2_IRQn #define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_3 - #define EXTMODULE_TIMER_DMA_STREAM DMA1_Stream1 #define EXTMODULE_TIMER_DMA DMA1 - #define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_1 + #define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_1 #define EXTMODULE_TIMER_DMA_FLAG_TC DMA_IT_TCIF1 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA1_Stream1_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA1_Stream1_IRQHandler - #define EXTMODULE_USART_GPIO_AF GPIO_AF_USART3 - #define EXTMODULE_USART_GPIO_AF_LL LL_GPIO_AF_7 #define EXTMODULE_USART USART3 #define EXTMODULE_USART_IRQn USART3_IRQn #define EXTMODULE_USART_IRQHandler USART3_IRQHandler #define EXTMODULE_USART_TX_DMA DMA1 #define EXTMODULE_USART_TX_DMA_CHANNEL LL_DMA_CHANNEL_4 - #define EXTMODULE_USART_TX_DMA_STREAM DMA1_Stream3 - #define EXTMODULE_USART_TX_DMA_STREAM_LL LL_DMA_STREAM_3 + #define EXTMODULE_USART_TX_DMA_STREAM LL_DMA_STREAM_3 #define EXTMODULE_USART_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 - #define EXTMODULE_USART_RX_DMA_STREAM DMA1_Stream1 - #define EXTMODULE_USART_RX_DMA_STREAM_LL LL_DMA_STREAM_1 + #define EXTMODULE_USART_RX_DMA_STREAM LL_DMA_STREAM_1 #elif defined(PCBX10) || PCBREV >= 13 - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define EXTMODULE_TX_GPIO GPIOA - #define EXTMODULE_TX_GPIO_PIN GPIO_Pin_10 // PA.10 (TIM1_CH3) - #define EXTMODULE_TX_GPIO_PinSource GPIO_PinSource10 - #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF_TIM1 + #define EXTMODULE_TX_GPIO GPIO_PIN(GPIOA, 10) // PA.10 (TIM1_CH3) + #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF1 #define EXTMODULE_TIMER TIM1 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 - #define EXTMODULE_TIMER_DMA_SIZE (DMA_SxCR_PSIZE_0 | DMA_SxCR_MSIZE_0) #define EXTMODULE_TIMER_IRQn TIM1_UP_TIM10_IRQn #define EXTMODULE_TIMER_IRQHandler TIM1_UP_TIM10_IRQHandler #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 - #define EXTMODULE_TIMER_DMA_STREAM DMA2_Stream5 #define EXTMODULE_TIMER_DMA DMA2 - #define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_5 + #define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_5 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream5_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler - #define EXTMODULE_TIMER_DMA_FLAG_TC DMA_IT_TCIF5 #else - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA1) - #define EXTMODULE_TX_GPIO GPIOA - #define EXTMODULE_TX_GPIO_PIN GPIO_Pin_15 // PA.15 (TIM2_CH1) - #define EXTMODULE_TX_GPIO_PinSource GPIO_PinSource15 - #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF_TIM2 + #define EXTMODULE_TX_GPIO GPIO_PIN(GPIOA, 15) // PA.15 (TIM2_CH1) + #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF1 #define EXTMODULE_TIMER TIM2 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH1 #define EXTMODULE_TIMER_32BITS - #define EXTMODULE_TIMER_DMA_SIZE (DMA_SxCR_PSIZE_1 | DMA_SxCR_MSIZE_1) #define EXTMODULE_TIMER_IRQn TIM2_IRQn #define EXTMODULE_TIMER_IRQHandler TIM2_IRQHandler #define EXTMODULE_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_3 - #define EXTMODULE_TIMER_DMA_STREAM DMA1_Stream7 #define EXTMODULE_TIMER_DMA DMA1 - #define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_7 + #define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_7 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA1_Stream7_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA1_Stream7_IRQHandler - #define EXTMODULE_TIMER_DMA_FLAG_TC DMA_IT_TCIF7 #endif // Heartbeat #define INTMODULE_HEARTBEAT -#define INTMODULE_HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD -#define INTMODULE_HEARTBEAT_GPIO GPIOD -#define INTMODULE_HEARTBEAT_GPIO_PIN LL_GPIO_PIN_12 // PD.12 / TIM4_CH1 +#define INTMODULE_HEARTBEAT_GPIO GPIO_PIN(GPIOD, 12) // PD.12 / TIM4_CH1 #define INTMODULE_HEARTBEAT_EXTI_PORT LL_SYSCFG_EXTI_PORTH #define INTMODULE_HEARTBEAT_EXTI_SYS_LINE LL_SYSCFG_EXTI_LINE12 #define INTMODULE_HEARTBEAT_EXTI_LINE LL_EXTI_LINE_12 @@ -978,22 +833,18 @@ #endif #define INTMODULE_HEARTBEAT_REUSE_INTERRUPT_ROTARY_ENCODER #if defined(INTERNAL_MODULE_PXX2) - #define INTMODULE_HEARTBEAT_TRIGGER LL_EXTI_TRIGGER_FALLING + #define INTMODULE_HEARTBEAT_TRIGGER GPIO_FALLING #else - #define INTMODULE_HEARTBEAT_TRIGGER LL_EXTI_TRIGGER_RISING + #define INTMODULE_HEARTBEAT_TRIGGER GPIO_RISING #endif // Trainer Port -#define TRAINER_GPIO GPIOC - -#define TRAINER_IN_GPIO_PIN LL_GPIO_PIN_6 // PC.06 +#define TRAINER_IN_GPIO GPIO_PIN(GPIOC, 6) // PC.06 #define TRAINER_IN_TIMER_Channel LL_TIM_CHANNEL_CH1 - -#define TRAINER_OUT_GPIO_PIN LL_GPIO_PIN_7 // PC.07 +#define TRAINER_OUT_GPIO GPIO_PIN(GPIOC, 7) // PC.07 #define TRAINER_OUT_TIMER_Channel LL_TIM_CHANNEL_CH2 -#define TRAINER_DETECT_GPIO GPIOB -#define TRAINER_DETECT_GPIO_PIN LL_GPIO_PIN_4 // PB.04 +#define TRAINER_DETECT_GPIO GPIO_PIN(GPIOB, 4) // PB.04 #if !defined(PCBX10) || defined(RADIO_FAMILY_T16) #define TRAINER_DETECT_INVERTED #endif @@ -1001,14 +852,13 @@ #define TRAINER_TIMER TIM3 #define TRAINER_TIMER_IRQn TIM3_IRQn #define TRAINER_TIMER_IRQHandler TIM3_IRQHandler -#define TRAINER_GPIO_AF LL_GPIO_AF_2 +#define TRAINER_GPIO_AF GPIO_AF2 #define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) // Trainer CPPM input on heartbeat pin #define TRAINER_MODULE_CPPM_TIMER TIM4 #define TRAINER_MODULE_CPPM_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define TRAINER_MODULE_CPPM_GPIO INTMODULE_HEARTBEAT_GPIO -#define TRAINER_MODULE_CPPM_GPIO_PIN INTMODULE_HEARTBEAT_GPIO_PIN #define TRAINER_MODULE_CPPM_TIMER_Channel LL_TIM_CHANNEL_CH1 #define TRAINER_MODULE_CPPM_TIMER_IRQn TIM4_IRQn #define TRAINER_MODULE_CPPM_TIMER_IRQHandler TIM4_IRQHandler @@ -1028,37 +878,30 @@ // Bluetooth #define STORAGE_BLUETOOTH #if defined(BLUETOOTH) -#define BT_RCC_APB2Periph RCC_APB2Periph_USART6 -#define BT_USART USART6 -#define BT_GPIO_AF LL_GPIO_AF_8 -#define BT_USART_IRQn USART6_IRQn -#define BT_USART_GPIO GPIOG -#define BT_TX_GPIO_PIN LL_GPIO_PIN_14 // PG.14 -#define BT_RX_GPIO_PIN LL_GPIO_PIN_9 // PG.09 -#define BT_USART_IRQHandler USART6_IRQHandler -#else -#define BT_RCC_APB2Periph 0 + #define BT_USART USART6 + #define BT_USART_IRQn USART6_IRQn + #define BT_USART_GPIO GPIOG + #define BT_TX_GPIO GPIO_PIN(GPIOG, 14) // PG.14 + #define BT_RX_GPIO GPIO_PIN(GPIOG, 9) // PG.09 #endif + #if defined(PCBX12S) #if PCBREV >= 13 - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOG) - #define BT_EN_GPIO GPIOI - #define BT_EN_GPIO_PIN LL_GPIO_PIN_10 // PI.10 + #define BT_EN_GPIO GPIO_PIN(GPIOI, 10) // PI.10 #else - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOG) - #define BT_EN_GPIO GPIOA - #define BT_EN_GPIO_PIN LL_GPIO_PIN_6 // PA.06 + #define BT_EN_GPIO GPIO_PIN(GPIOA, 6) // PA.06 #endif // #define BT_BRTS_GPIO GPIOG // #define BT_BRTS_GPIO_PIN GPIO_Pin_10 // PG.10 // #define BT_BCTS_GPIO GPIOG // #define BT_BCTS_GPIO_PIN GPIO_Pin_11 // PG.11 #elif defined(PCBX10) - #define BT_RCC_AHB1Periph RCC_AHB1Periph_GPIOG - #define BT_EN_GPIO GPIOG - #define BT_EN_GPIO_PIN LL_GPIO_PIN_10 // PG.10 + #define BT_EN_GPIO GPIO_PIN(GPIOG, 10) // PG.10 #endif +// SDRAM +#define SDRAM_BANK2 + #define LCD_W 480 #define LCD_H 272 #define LCD_PHYS_H LCD_H diff --git a/radio/src/targets/horus/haptic_driver.cpp b/radio/src/targets/horus/haptic_driver.cpp index d9c6180e0..25ce73b94 100644 --- a/radio/src/targets/horus/haptic_driver.cpp +++ b/radio/src/targets/horus/haptic_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "board.h" void hapticOff(void) @@ -36,16 +40,9 @@ void hapticOn(uint32_t pwmPercent) void hapticInit(void) { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HAPTIC_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HAPTIC_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(HAPTIC_GPIO, HAPTIC_GPIO_PinSource, HAPTIC_GPIO_AF); + gpio_init_af(HAPTIC_GPIO, HAPTIC_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(HAPTIC_GPIO_TIMER); HAPTIC_GPIO_TIMER->ARR = 100; HAPTIC_GPIO_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 10000 - 1; HAPTIC_GPIO_TIMER->CCMR1 = HAPTIC_TIMER_MODE; // PWM @@ -60,5 +57,4 @@ void hapticInit(void) void hapticDone(void) { hapticOff(); - RCC_AHB1PeriphClockCmd(HAPTIC_RCC_AHB1Periph, DISABLE); } diff --git a/radio/src/targets/horus/lcd_driver.cpp b/radio/src/targets/horus/lcd_driver.cpp index 6ffa7b161..1a5150816 100644 --- a/radio/src/targets/horus/lcd_driver.cpp +++ b/radio/src/targets/horus/lcd_driver.cpp @@ -19,8 +19,11 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "stm32_hal_ll.h" #include "stm32_hal.h" + #include "opentx_types.h" #include "dma2d.h" #include "hal.h" @@ -49,6 +52,8 @@ #define VFP 2 #endif +#define GPIO_AF_LTDC GPIO_AF14 + static LTDC_HandleTypeDef hltdc; static void* initialFrameBuffer = nullptr; @@ -181,72 +186,65 @@ static void startLcdRefresh(lv_disp_drv_t *disp_drv, uint16_t *buffer, inline void LCD_NRST_LOW() { - LL_GPIO_ResetOutputPin(LCD_GPIO_NRST, LCD_GPIO_PIN_NRST); + gpio_clear(LCD_GPIO_NRST); } inline void LCD_NRST_HIGH() { - LL_GPIO_SetOutputPin(LCD_GPIO_NRST, LCD_GPIO_PIN_NRST); + gpio_set(LCD_GPIO_NRST); } static void LCD_AF_GPIOConfig() { - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); - - /* GPIOs Configuration */ - /* - +------------------------+-----------------------+----------------------------+ - + LCD pins assignment + - +------------------------+-----------------------+---------------------------- - | | LCD_TFT G2 <-> PJ.09 | | - | LCD_TFT R3 <-> PJ.02 | LCD_TFT G3 <-> PJ.10 | LCD_TFT B3 <-> PJ.15 | - | LCD_TFT R4 <-> PJ.03 | LCD_TFT G4 <-> PJ.11 | LCD_TFT B4 <-> PK.03 | - | LCD_TFT R5 <-> PJ.04 | LCD_TFT G5 <-> PK.00 | LCD_TFT B5 <-> PK.04 | - | LCD_TFT R6 <-> PJ.05 | LCD_TFT G6 <-> PK.01 | LCD_TFT B6 <-> PK.05 | - | LCD_TFT R7 <-> PJ.06 | LCD_TFT G7 <-> PK.02 | LCD_TFT B7 <-> PK.06 | - ------------------------------------------------------------------------------- - | LCD_TFT HSYNC <-> PI.12 | LCDTFT VSYNC <-> PI.13 | - | LCD_TFT CLK <-> PI.14 | LCD_TFT DE <-> PK.07 /// - ----------------------------------------------------- - | LCD_CS <-> PI.10 |LCD_SCK<->PI.11 - ----------------------------------------------------- + /* GPIOs Configuration */ + /* + +------------------------+-----------------------+----------------------------+ + + LCD pins assignment + + +------------------------+-----------------------+----------------------------+ + | | LCD_TFT G2 <-> PJ.09 | | + | LCD_TFT R3 <-> PJ.02 | LCD_TFT G3 <-> PJ.10 | LCD_TFT B3 <-> PJ.15 | + | LCD_TFT R4 <-> PJ.03 | LCD_TFT G4 <-> PJ.11 | LCD_TFT B4 <-> PK.03 | + | LCD_TFT R5 <-> PJ.04 | LCD_TFT G5 <-> PK.00 | LCD_TFT B5 <-> PK.04 | + | LCD_TFT R6 <-> PJ.05 | LCD_TFT G6 <-> PK.01 | LCD_TFT B6 <-> PK.05 | + | LCD_TFT R7 <-> PJ.06 | LCD_TFT G7 <-> PK.02 | LCD_TFT B7 <-> PK.06 | + ------------------------------------------------------------------------------- + | LCD_TFT HSYNC <-> PI.12 | LCD_TFT VSYNC <-> PI.13 | + | LCD_TFT CLK <-> PI.14 | LCD_TFT DE <-> PK.07 | + -------------------------------------------------------- + | LCD_CS <-> PI.10 | LCD_SCK<->PI.11 | + -------------------------------------------------------- */ // GPIOI configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_ALTERNATE; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - GPIO_InitStructure.Alternate = LL_GPIO_AF_14; // AF LTDC - LL_GPIO_Init(GPIOI, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOI, 12), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOI, 13), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOI, 14), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOJ configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 - | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | LL_GPIO_PIN_15; - - LL_GPIO_Init(GPIOJ, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOJ, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 9), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 10), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 11), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 15), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOK configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 - | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7; - - LL_GPIO_Init(GPIOK, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOK, 0), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 1), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 7), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); } static void LCD_NRSTConfig(void) { - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_GPIO_PIN_NRST; - GPIO_InitStructure.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - - LL_GPIO_Init(LCD_GPIO_NRST, &GPIO_InitStructure); + gpio_init(LCD_GPIO_NRST, GPIO_OUT, GPIO_PIN_SPEED_LOW); } static void lcdReset(void) diff --git a/radio/src/targets/horus/led_driver.cpp b/radio/src/targets/horus/led_driver.cpp index 656f0a87c..c74297cdf 100644 --- a/radio/src/targets/horus/led_driver.cpp +++ b/radio/src/targets/horus/led_driver.cpp @@ -19,63 +19,72 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" void ledInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = LED_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(LED_GPIO, &GPIO_InitStructure); +#if defined(LED_GPIO) + gpio_init(LED_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif +#if defined(LED_RED_GPIO) + gpio_init(LED_RED_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif +#if defined(LED_GREEN_GPIO) + gpio_init(LED_GREEN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif +#if defined(LED_BLUE_GPIO) + gpio_init(LED_BLUE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); +#endif } -#if defined(PCBX12S) +#if defined(LED_GPIO) + +// Single GPIO for dual color LED void ledOff() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = LED_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(LED_GPIO, &GPIO_InitStructure); + gpio_init(LED_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); } void ledRed() { ledInit(); - GPIO_SetBits(LED_GPIO, LED_GPIO_PIN); + gpio_set(LED_GPIO); } void ledBlue() { ledInit(); - GPIO_ResetBits(LED_GPIO, LED_GPIO_PIN); + gpio_clear(LED_GPIO); } -#elif defined(PCBX10) + +#elif defined(LED_RED_GPIO) && defined(LED_GREEN_GPIO) && defined(LED_BLUE_GPIO) + void ledOff() { - GPIO_ResetBits(LED_GPIO, LED_GPIO_PIN); + gpio_clear(LED_RED_GPIO); + gpio_clear(LED_GREEN_GPIO); + gpio_clear(LED_BLUE_GPIO); } void ledRed() { ledOff(); - GPIO_SetBits(LED_GPIO, LED_RED_GPIO_PIN); + gpio_set(LED_RED_GPIO); } void ledGreen() { ledOff(); - GPIO_SetBits(LED_GPIO, LED_GREEN_GPIO_PIN); + gpio_set(LED_GREEN_GPIO); } void ledBlue() { ledOff(); - GPIO_SetBits(LED_GPIO, LED_BLUE_GPIO_PIN); + gpio_set(LED_BLUE_GPIO); } + #endif diff --git a/radio/src/targets/horus/sdram_driver.c b/radio/src/targets/horus/sdram_driver.c deleted file mode 100644 index cbca9b501..000000000 --- a/radio/src/targets/horus/sdram_driver.c +++ /dev/null @@ -1,467 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" -#include "stm32f4xx_fmc.h" - -#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b - -#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3 - -#define SDCLOCK_PERIOD FMC_SDClock_Period_2 - -#define SDRAM_TIMEOUT ((uint32_t)0xFFFF) - -/** - * @brief FMC SDRAM Mode definition register defines - */ -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/** - * @brief FMC SDRAM Memory Read Burst feature - */ -#define SDRAM_READBURST FMC_Read_Burst_Disable - -static void __Delay(__IO uint32_t nCount) -{ - __IO uint32_t index = 0; - for(index = (100000 * nCount); index != 0; index--) - { - } -} - -/** - * @brief Configures all SDRAM memory I/Os pins. - * @param None. - * @retval None. - */ -void SDRAM_GPIOConfig(void) -{ - GPIO_InitTypeDef GPIO_InitStructure; - - /* Enable GPIOs clock */ - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | - RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG|RCC_AHB1Periph_GPIOH, ENABLE); - - /*-- GPIOs Configuration -----------------------------------------------------*/ - /* - +-------------------+--------------------+--------------------+--------------------+ - + SDRAM pins assignment + - +-------------------+--------------------+--------------------+--------------------+ - | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK | - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS | - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+ - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | - +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | - | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | - | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | - | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | - +-------------------+--------------------+--------------------+ - | PB5 <-> FMC_SDCKE1| - | PB6 <-> FMC_SDNE1 | - | PH5 <-> FMC_SDNWE |/////// - +-------------------+ - - */ - - /* Common GPIO configuration */ - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* GPIOB configuration */ - GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 ; - - GPIO_Init(GPIOB, &GPIO_InitStructure); - - /* GPIOC configuration */ - GPIO_PinAFConfig(GPIOH, GPIO_PinSource5 , GPIO_AF_FMC); - - GPIO_PinAFConfig(GPIOH, GPIO_PinSource6 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6; - - GPIO_Init(GPIOH, &GPIO_InitStructure); - - /* GPIOD configuration */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | - GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | - GPIO_Pin_15; - - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* GPIOE configuration */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | - GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* GPIOF configuration */ - GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC); - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | - GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | - GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | - GPIO_Pin_14 | GPIO_Pin_15; - - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* GPIOG configuration */ - GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); - - - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | - GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; - - GPIO_Init(GPIOG, &GPIO_InitStructure); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - uint32_t timeout = SDRAM_TIMEOUT; - - /* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - __Delay(10); - - /* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 8; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(1385); - - /* Wait until the SDRAM controller is ready */ - timeout = SDRAM_TIMEOUT; - while((FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) && (timeout > 0)) - { - timeout--; - } -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * @param None. - * @retval None. - */ -void SDRAMTest_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - -/* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - __Delay(10); - -/* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - -/* Step 8 --------------------------------------------------------------------*/ - - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(1386); - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) - { - } -} - -void SDRAM_Init(void) -{ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* GPIO configuration for FMC SDRAM bank */ - SDRAM_GPIOConfig(); - - /* Enable FMC clock */ - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - - /* FMC Configuration ---------------------------------------------------------*/ - /* FMC SDRAM Bank configuration */ - /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=70 (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: min=1+ 7ns (1+1x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - - /* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD; - FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAMTest_InitSequence(); -} - -#if 0 -void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwWriteAddress; - - FMC_SDRAMWriteProtectionConfig(FMC_Bank1_SDRAM, DISABLE); - - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - for (; uwBufferSize != 0; uwBufferSize--) - { - - *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++; - - write_pointer += 4; - } - -} - -void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize) -{ - __IO uint32_t write_pointer = (uint32_t)uwReadAddress; - - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) - { - } - - for(; uwBufferSize != 0x00; uwBufferSize--) - { - *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer ); - - write_pointer += 4; - } -} -#endif diff --git a/radio/src/targets/horus/tp_gt911.cpp b/radio/src/targets/horus/tp_gt911.cpp index 0ff9630c9..43af66d1e 100644 --- a/radio/src/targets/horus/tp_gt911.cpp +++ b/radio/src/targets/horus/tp_gt911.cpp @@ -19,6 +19,8 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "stm32_hal_ll.h" #include "stm32_hal.h" #include "stm32_i2c_driver.h" @@ -38,12 +40,6 @@ #define TP_GT911_ID "911" -#define TPRST_LOW() LL_GPIO_ResetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN) -#define TPRST_HIGH() LL_GPIO_SetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN) - -#define TPINT_LOW() LL_GPIO_ResetOutputPin(TOUCH_INT_GPIO, TOUCH_INT_GPIO_PIN) -#define TPINT_HIGH() LL_GPIO_SetOutputPin(TOUCH_INT_GPIO, TOUCH_INT_GPIO_PIN) - #if defined (RADIO_T18) const uint8_t TOUCH_GT911_Cfg[] = { GT911_CFG_NUMBER, // 0x8047 Config version @@ -446,56 +442,6 @@ static void _gt911_exti_isr(void) touchEventOccured = true; } -static void TOUCH_AF_ExtiStop(void) -{ - stm32_exti_disable(TOUCH_INT_EXTI_Line); -} - -static void TOUCH_AF_ExtiConfig(void) -{ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - LL_SYSCFG_SetEXTISource(TOUCH_INT_EXTI_Port, TOUCH_INT_EXTI_SysCfgLine); - - stm32_exti_enable(TOUCH_INT_EXTI_Line, - LL_EXTI_TRIGGER_RISING, - _gt911_exti_isr); -} - -static void TOUCH_AF_GPIOConfig(void) -{ - LL_GPIO_InitTypeDef gpioInit; - LL_GPIO_StructInit(&gpioInit); - - stm32_gpio_enable_clock(TOUCH_RST_GPIO); - stm32_gpio_enable_clock(TOUCH_INT_GPIO); - - gpioInit.Mode = LL_GPIO_MODE_OUTPUT; - gpioInit.Speed = LL_GPIO_SPEED_FREQ_HIGH; - gpioInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - gpioInit.Pull = LL_GPIO_PULL_NO; - - gpioInit.Pin = TOUCH_RST_GPIO_PIN; - LL_GPIO_Init(TOUCH_RST_GPIO, &gpioInit); - LL_GPIO_ResetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); - - gpioInit.Pin = TOUCH_INT_GPIO_PIN; - LL_GPIO_Init(TOUCH_INT_GPIO, &gpioInit); - LL_GPIO_ResetOutputPin(TOUCH_INT_GPIO, TOUCH_INT_GPIO_PIN); -} - -void TOUCH_AF_INT_Change(void) -{ - LL_GPIO_InitTypeDef gpioInit; - LL_GPIO_StructInit(&gpioInit); - - gpioInit.Pin = TOUCH_INT_GPIO_PIN; - gpioInit.Mode = LL_GPIO_MODE_INPUT; - gpioInit.Speed = LL_GPIO_SPEED_FREQ_HIGH; - gpioInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - gpioInit.Pull = LL_GPIO_PULL_UP; - LL_GPIO_Init(TOUCH_INT_GPIO, &gpioInit); -} - void I2C_Init_Radio(void) { TRACE("GT911 I2C Init"); @@ -577,7 +523,7 @@ bool I2C_GT911_SendConfig(uint8_t cfgVer) void touchPanelDeInit(void) { - TOUCH_AF_ExtiStop(); + gpio_int_disable(TOUCH_INT_GPIO); touchGT911Flag = false; } @@ -588,25 +534,26 @@ bool touchPanelInit(void) uint8_t tmp[4] = {0}; if (touchGT911Flag) { - TOUCH_AF_ExtiConfig(); + gpio_init_int(TOUCH_INT_GPIO, GPIO_IN_PU, GPIO_RISING, _gt911_exti_isr); return true; } else { TRACE("Touchpanel init start ..."); - TOUCH_AF_GPIOConfig(); // SET RST=OUT INT=OUT INT=LOW + gpio_init(TOUCH_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TOUCH_INT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); I2C_Init_Radio(); - TPRST_LOW(); - TPINT_HIGH(); + gpio_clear(TOUCH_RST_GPIO); + gpio_set(TOUCH_INT_GPIO); delay_us(200); - TPRST_HIGH(); + gpio_set(TOUCH_RST_GPIO); delay_ms(6); - TPINT_LOW(); + gpio_clear(TOUCH_INT_GPIO); delay_ms(55); - TOUCH_AF_INT_Change(); // Set INT INPUT INT=LOW + gpio_init(TOUCH_INT_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); delay_ms(50); @@ -651,7 +598,7 @@ bool touchPanelInit(void) } touchGT911Flag = true; - TOUCH_AF_ExtiConfig(); + gpio_init_int(TOUCH_INT_GPIO, GPIO_IN_PU, GPIO_RISING, _gt911_exti_isr); return true; } diff --git a/radio/src/targets/horus/usb_charger_driver.cpp b/radio/src/targets/horus/usb_charger_driver.cpp index c55f86ed7..8817ecf5e 100644 --- a/radio/src/targets/horus/usb_charger_driver.cpp +++ b/radio/src/targets/horus/usb_charger_driver.cpp @@ -19,23 +19,19 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" void usbChargerInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = USB_CHARGER_GPIO_PIN | USB_USBDet_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(USB_CHARGER_GPIO, &GPIO_InitStructure); + gpio_init(USB_CHARGER_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); + gpio_init(USB_USBDet_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); } bool usbChargerLed() { - if (GPIO_ReadInputDataBit(USB_CHARGER_GPIO, USB_USBDet_GPIO_PIN) == 0) - return 0; - - return GPIO_ReadInputDataBit(USB_CHARGER_GPIO, USB_CHARGER_GPIO_PIN) == Bit_RESET; + if (!gpio_read(USB_USBDet_GPIO)) return 0; + return !gpio_read(USB_CHARGER_GPIO); } diff --git a/radio/src/targets/nv14/CMakeLists.txt b/radio/src/targets/nv14/CMakeLists.txt index a7864e2a6..4bc5964c0 100644 --- a/radio/src/targets/nv14/CMakeLists.txt +++ b/radio/src/targets/nv14/CMakeLists.txt @@ -111,13 +111,13 @@ set(FIRMWARE_TARGET_SRC board.cpp ${LCD_DRIVER} ${TOUCH_DRIVER} - sdram_driver.c battery_driver.cpp backlight_driver.cpp ) set(FIRMWARE_SRC ${FIRMWARE_SRC} + targets/common/arm/stm32/sdram_driver.cpp targets/common/arm/stm32/dma2d.cpp targets/common/arm/stm32/spi_flash.cpp targets/common/arm/stm32/diskio_spi_flash.cpp diff --git a/radio/src/targets/nv14/backlight_driver.cpp b/radio/src/targets/nv14/backlight_driver.cpp index 1533c319f..9c9269c37 100644 --- a/radio/src/targets/nv14/backlight_driver.cpp +++ b/radio/src/targets/nv14/backlight_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "opentx_types.h" #include "board.h" @@ -27,30 +31,16 @@ void backlightLowInit( void ) { - RCC_AHB1PeriphClockCmd(BACKLIGHT_RCC_AHB1Periph, ENABLE); - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_WriteBit( BACKLIGHT_GPIO, BACKLIGHT_GPIO_PIN, Bit_RESET ); + gpio_init(BACKLIGHT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_clear(BACKLIGHT_GPIO); } void backlightInit() { // PIN init - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); - // TODO review this when the timer will be chosen + stm32_timer_enable_clock(BACKLIGHT_TIMER); BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 1000000 - 1; // 10kHz (same as FrOS) BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE; // PWM mode 1 diff --git a/radio/src/targets/nv14/battery_driver.cpp b/radio/src/targets/nv14/battery_driver.cpp index acf4e0ba7..fc640578c 100644 --- a/radio/src/targets/nv14/battery_driver.cpp +++ b/radio/src/targets/nv14/battery_driver.cpp @@ -18,6 +18,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "opentx.h" #include "battery_driver.h" @@ -35,14 +39,8 @@ void battery_charge_init() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = PWR_CHARGE_FINISHED_GPIO_PIN | PWR_CHARGING_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(PWR_CHARGING_GPIO, &GPIO_InitStructure); - GPIO_SetBits(PWR_CHARGING_GPIO, PWR_CHARGE_FINISHED_GPIO_PIN | PWR_CHARGING_GPIO_PIN); + gpio_init(PWR_CHARGE_FINISHED_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); + gpio_init(PWR_CHARGING_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); } #define CHARGE_SAMPLES 10 diff --git a/radio/src/targets/nv14/battery_driver.h b/radio/src/targets/nv14/battery_driver.h index 1eace4d8c..ecc824ffa 100644 --- a/radio/src/targets/nv14/battery_driver.h +++ b/radio/src/targets/nv14/battery_driver.h @@ -39,16 +39,11 @@ enum ChargeState }; -#define PWR_CHARGE_FINISHED_GPIO GPIOB -#define PWR_CHARGE_FINISHED_GPIO_REG PWR_CHARGE_FINISHED_GPIO->IDR -#define PWR_CHARGE_FINISHED_GPIO_PIN GPIO_Pin_13 // PB.13 +#define PWR_CHARGE_FINISHED_GPIO GPIO_PIN(GPIOB, 13) // PB.13 +#define PWR_CHARGING_GPIO GPIO_PIN(GPIOB, 14) // PB.14 -#define PWR_CHARGING_GPIO GPIOB -#define PWR_CHARGING_GPIO_REG PWR_CHARGING_GPIO->IDR -#define PWR_CHARGING_GPIO_PIN GPIO_Pin_14 // PB.14 - -#define READ_CHARGE_FINISHED_STATE() GPIO_ReadInputDataBit( PWR_CHARGE_FINISHED_GPIO, PWR_CHARGE_FINISHED_GPIO_PIN ) -#define READ_CHARGING_STATE() GPIO_ReadInputDataBit( PWR_CHARGING_GPIO, PWR_CHARGING_GPIO_PIN ) +#define READ_CHARGE_FINISHED_STATE() gpio_read(PWR_CHARGE_FINISHED_GPIO) ? 1 : 0 +#define READ_CHARGING_STATE() gpio_read(PWR_CHARGING_GPIO) ? 1 : 0 extern void battery_charge_init(); extern void handle_battery_charge(uint32_t last_press_time); diff --git a/radio/src/targets/nv14/board.cpp b/radio/src/targets/nv14/board.cpp index 3258e2678..b09652023 100644 --- a/radio/src/targets/nv14/board.cpp +++ b/radio/src/targets/nv14/board.cpp @@ -18,12 +18,14 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - + #include "stm32_adc.h" +#include "stm32_gpio.h" #include "board.h" #include "boards/generic_stm32/module_ports.h" +#include "hal/gpio.h" #include "hal/adc_driver.h" #include "hal/trainer_driver.h" #include "hal/switch_driver.h" @@ -65,46 +67,16 @@ void delay_self(int count) } } -#define RCC_AHB1PeriphMinimum (PWR_RCC_AHB1Periph | \ - LCD_RCC_AHB1Periph |\ - BACKLIGHT_RCC_AHB1Periph |\ - SDRAM_RCC_AHB1Periph \ - ) -#define RCC_AHB1PeriphOther (SD_RCC_AHB1Periph |\ - AUDIO_RCC_AHB1Periph |\ - MONITOR_RCC_AHB1Periph |\ - TELEMETRY_RCC_AHB1Periph |\ - AUDIO_RCC_AHB1Periph |\ - HAPTIC_RCC_AHB1Periph |\ - INTMODULE_RCC_AHB1Periph |\ - EXTMODULE_RCC_AHB1Periph\ - ) -#define RCC_AHB3PeriphMinimum (SDRAM_RCC_AHB3Periph) - -#define RCC_APB1PeriphMinimum (BACKLIGHT_RCC_APB1Periph) - -#define RCC_APB1PeriphOther (TELEMETRY_RCC_APB1Periph) +#define RCC_AHB1PeriphMinimum (LCD_RCC_AHB1Periph) #define RCC_APB2PeriphMinimum (LCD_RCC_APB2Periph) -#define RCC_APB2PeriphOther (HAPTIC_RCC_APB2Periph |\ - AUDIO_RCC_APB2Periph \ - ) - static uint8_t boardGetPcbRev() { - GPIO_InitTypeDef GPIO_InitStructure; - - RCC_AHB1PeriphClockCmd(INTMODULE_RCC_AHB1Periph, ENABLE); - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_OD; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Pin = INTMODULE_PWR_GPIO_PIN; - GPIO_Init(INTMODULE_PWR_GPIO, &GPIO_InitStructure); + gpio_init(INTMODULE_PWR_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); delay_ms(1); // delay to let the input settle, else it does not work properly // detect NV14 vs EL18 - if (GPIO_ReadInputDataBit(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) == Bit_SET) { + if (gpio_read(INTMODULE_PWR_GPIO)) { // pull-up connected: EL18 return PCBREV_EL18; } else { @@ -115,15 +87,8 @@ static uint8_t boardGetPcbRev() void boardBootloaderInit() { -#if defined(USB_SW_PIN) - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Pin = USB_SW_PIN; - GPIO_Init(USB_SW_GPOIO, &GPIO_InitStructure); - RCC_AHB1PeriphClockCmd(USB_SW_AHB1Periph_GPIO, ENABLE); +#if defined(USB_SW_GPIO) + gpio_init(USB_SW_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif // detect NV14 vs EL18 @@ -132,14 +97,7 @@ void boardBootloaderInit() static void monitorInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; - - GPIO_InitStructure.GPIO_Pin = VBUS_MONITOR_PIN; - GPIO_Init(GPIOJ, &GPIO_InitStructure); + gpio_init(VBUS_MONITOR_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); } void boardInit() @@ -149,10 +107,8 @@ void boardInit() #endif #if !defined(SIMU) - RCC_AHB1PeriphClockCmd(RCC_AHB1PeriphMinimum | RCC_AHB1PeriphOther, ENABLE); - RCC_AHB3PeriphClockCmd(RCC_AHB3PeriphMinimum, ENABLE); - RCC_APB1PeriphClockCmd(RCC_APB1PeriphMinimum | RCC_APB1PeriphOther, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2PeriphMinimum | RCC_APB2PeriphOther, ENABLE); + LL_AHB1_GRP1_EnableClock(RCC_AHB1PeriphMinimum); + LL_APB2_GRP1_EnableClock(RCC_APB2PeriphMinimum); // enable interrupts __enable_irq(); @@ -235,13 +191,13 @@ void boardInit() lcdSetInitalFrameBuffer(lcdFront->getData()); #if defined(DEBUG) - DBGMCU_APB1PeriphConfig( +/* DBGMCU_APB1PeriphConfig( DBGMCU_IWDG_STOP | DBGMCU_TIM1_STOP | DBGMCU_TIM2_STOP | DBGMCU_TIM3_STOP | DBGMCU_TIM4_STOP | DBGMCU_TIM5_STOP | DBGMCU_TIM6_STOP | DBGMCU_TIM7_STOP | DBGMCU_TIM8_STOP | DBGMCU_TIM9_STOP | DBGMCU_TIM10_STOP | DBGMCU_TIM11_STOP | DBGMCU_TIM12_STOP | DBGMCU_TIM13_STOP | DBGMCU_TIM14_STOP, - ENABLE); + ENABLE);*/ #endif } diff --git a/radio/src/targets/nv14/board.h b/radio/src/targets/nv14/board.h index a86447cb2..2c24a2b51 100644 --- a/radio/src/targets/nv14/board.h +++ b/radio/src/targets/nv14/board.h @@ -63,9 +63,6 @@ void flashWrite(uint32_t * address, const uint32_t * buffer); uint32_t isFirmwareStart(const uint8_t * buffer); uint32_t isBootloaderStart(const uint8_t * buffer); -// SDRAM driver -void SDRAM_Init(); - enum { PCBREV_NV14 = 0, PCBREV_EL18 = 1, @@ -82,24 +79,24 @@ extern HardwareOptions hardwareOptions; #define INTERNAL_MODULE_OFF() \ do { \ if (hardwareOptions.pcbrev == PCBREV_NV14) \ - GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); \ + gpio_set(INTMODULE_PWR_GPIO); \ else \ - GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); \ + gpio_clear(INTMODULE_PWR_GPIO); \ } while (0) #define INTERNAL_MODULE_ON() \ do { \ if (hardwareOptions.pcbrev == PCBREV_NV14) \ - GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); \ + gpio_clear(INTMODULE_PWR_GPIO); \ else \ - GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN); \ + gpio_set(INTMODULE_PWR_GPIO); \ } while (0) -#define EXTERNAL_MODULE_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) -#define EXTERNAL_MODULE_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) +#define EXTERNAL_MODULE_ON() gpio_set(EXTMODULE_PWR_GPIO) +#define EXTERNAL_MODULE_OFF() gpio_clear(EXTMODULE_PWR_GPIO) -#define BLUETOOTH_MODULE_ON() GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN) -#define BLUETOOTH_MODULE_OFF() GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN) +#define BLUETOOTH_MODULE_ON() gpio_clear(BLUETOOTH_ON_GPIO) +#define BLUETOOTH_MODULE_OFF() gpio_set(BLUETOOTH_ON_GPIO) #else diff --git a/radio/src/targets/nv14/bootloader/boot_menu.cpp b/radio/src/targets/nv14/bootloader/boot_menu.cpp index 3551e9e33..9d2909df2 100644 --- a/radio/src/targets/nv14/bootloader/boot_menu.cpp +++ b/radio/src/targets/nv14/bootloader/boot_menu.cpp @@ -19,21 +19,24 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" #include "fw_version.h" #include "lcd.h" #include "translations.h" -#include "../../common/arm/stm32/bootloader/boot.h" -#include "../../common/arm/stm32/bootloader/bin_files.h" +#include "targets/common/arm/stm32/bootloader/boot.h" +#include "targets/common/arm/stm32/bootloader/bin_files.h" #include #define RADIO_MENU_LEN 2 -#define USB_SW_TO_INTERNAL_MODULE() GPIO_SetBits(USB_SW_GPOIO, USB_SW_PIN); -#define USB_SW_TO_MCU() GPIO_ResetBits(USB_SW_GPOIO, USB_SW_PIN); +#define USB_SW_TO_INTERNAL_MODULE() gpio_set(USB_SW_GPIO); +#define USB_SW_TO_MCU() gpio_clear(USB_SW_GPIO); #define DEFAULT_PADDING 28 #define DOUBLE_PADDING 56 diff --git a/radio/src/targets/nv14/hal.h b/radio/src/targets/nv14/hal.h index 355633ef1..cc8da10e4 100644 --- a/radio/src/targets/nv14/hal.h +++ b/radio/src/targets/nv14/hal.h @@ -74,9 +74,7 @@ #define KEYS_GPIO_PIN_EXIT LL_GPIO_PIN_11 // PG.11 // Monitor pin -#define MONITOR_RCC_AHB1Periph (RCC_AHB1Periph_GPIOJ) -#define VBUS_MONITOR_GPIO (GPIOJ) -#define VBUS_MONITOR_PIN (GPIO_Pin_14) +#define VBUS_MONITOR_GPIO GPIO_PIN(GPIOJ, 14) // PJ.14 // Switches #define HARDWARE_SWITCH_A @@ -174,11 +172,8 @@ } // Power -#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOI -#define PWR_ON_GPIO GPIOI -#define PWR_SWITCH_GPIO GPIOI -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_11 // PI.11 -#define PWR_ON_GPIO_PIN GPIO_Pin_14 // PI.14 +#define PWR_SWITCH_GPIO GPIO_PIN(GPIOI, 11) // PI.11 +#define PWR_ON_GPIO GPIO_PIN(GPIOI, 14) // PI.14 // S.Port update connector #define SPORT_MAX_BAUDRATE 400000 @@ -215,38 +210,21 @@ #define KEYS_BACKLIGHT_RCC_AHB1Periph 0 // Telemetry -#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_DMA1) -#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_REV_GPIO GPIOJ -#define TELEMETRY_RX_REV_GPIO_PIN GPIO_Pin_8 // PJ.08 -#define TELEMETRY_TX_REV_GPIO_PIN GPIO_Pin_7 // PJ.07 -#define TELEMETRY_DIR_GPIO GPIOJ -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_13 // PJ.13 +#define TELEMETRY_RX_REV_GPIO GPIO_PIN(GPIOJ, 8) // PJ.08 +#define TELEMETRY_TX_REV_GPIO GPIO_PIN(GPIOJ, 7) // PJ.07 +#define TELEMETRY_DIR_GPIO GPIO_PIN(GPIOJ, 13) // PJ.13 #define TELEMETRY_SET_INPUT 1 -#define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_TX_GPIO GPIO_PIN(GPIOD, 5) // PD.05 +#define TELEMETRY_RX_GPIO GPIO_PIN(GPIOD, 6) // PD.06 #define TELEMETRY_USART USART2 +#define TELEMETRY_USART_IRQn USART2_IRQn #define TELEMETRY_DMA DMA1 #define TELEMETRY_DMA_Stream_TX LL_DMA_STREAM_6 -#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 +#define TELEMETRY_DMA_Channel_TX LL_DMA_CHANNEL_4 #define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn -#define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler -#define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 // #define TELEMETRY_DMA_Stream_RX LL_DMA_STREAM_5 // #define TELEMETRY_DMA_Channel_RX LL_DMA_CHANNEL_4 -#define TELEMETRY_USART_IRQHandler USART2_IRQHandler -#define TELEMETRY_USART_IRQn USART2_IRQn -#define TELEMETRY_DIR_OUTPUT() TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN -#define TELEMETRY_DIR_INPUT() TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN -#define TELEMETRY_TX_POL_NORM() TELEMETRY_REV_GPIO->BSRRH = TELEMETRY_TX_REV_GPIO_PIN -#define TELEMETRY_TX_POL_INV() TELEMETRY_REV_GPIO->BSRRL = TELEMETRY_TX_REV_GPIO_PIN -#define TELEMETRY_RX_POL_NORM() TELEMETRY_REV_GPIO->BSRRH = TELEMETRY_RX_REV_GPIO_PIN -#define TELEMETRY_RX_POL_INV() TELEMETRY_REV_GPIO->BSRRL = TELEMETRY_RX_REV_GPIO_PIN // Software IRQ (Prio 5 -> FreeRTOS compatible) #define TELEMETRY_RX_FRAME_EXTI_LINE LL_EXTI_LINE_4 @@ -256,39 +234,28 @@ // USB #define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA #define USB_GPIO GPIOA -#define USB_GPIO_PIN_VBUS LL_GPIO_PIN_9 // PA.09 -#define USB_GPIO_PIN_DM LL_GPIO_PIN_11 // PA.11 -#define USB_GPIO_PIN_DP LL_GPIO_PIN_12 // PA.12 -#define USB_GPIO_AF GPIO_AF_OTG1_FS - -#define USB_SW_AHB1Periph_GPIO RCC_AHB1Periph_GPIOI -#define USB_SW_GPOIO GPIOI -#define USB_SW_PIN GPIO_Pin_10 +#define USB_GPIO_VBUS GPIO_PIN(GPIOA,9) // PA.09 +#define USB_GPIO_DM GPIO_PIN(GPIOA, 11) // PA.11 +#define USB_GPIO_DP GPIO_PIN(GPIOA, 12) // PA.12 +#define USB_GPIO_AF GPIO_AF10 +#define USB_SW_GPIO GPIO_PIN(GPIOI, 10) // PI.10 // LCD -#define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOK | RCC_AHB1Periph_DMA2D) -#define LCD_RCC_APB1Periph 0 -#define LCD_RCC_APB2Periph RCC_APB2Periph_LTDC -#define LCD_NRST_GPIO GPIOG -#define LCD_NRST_GPIO_PIN LL_GPIO_PIN_9 // PG.09 -#define LCD_SPI_GPIO GPIOE -#define LCD_SPI_CS_GPIO_PIN LL_GPIO_PIN_4 // PE.04 -#define LCD_SPI_SCK_GPIO_PIN LL_GPIO_PIN_2 // PE.02 -#define LCD_SPI_MISO_GPIO_PIN LL_GPIO_PIN_5 // PE.05 -#define LCD_SPI_MOSI_GPIO_PIN LL_GPIO_PIN_6 // PE.06 +#define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA2D +#define LCD_RCC_APB2Periph LL_APB2_GRP1_PERIPH_LTDC +#define LCD_NRST_GPIO GPIO_PIN(GPIOG, 9) // PG.09 +#define LCD_SPI_CS_GPIO GPIO_PIN(GPIOE, 4) // PE.04 +#define LCD_SPI_SCK_GPIO GPIO_PIN(GPIOE, 2) // PE.02 +#define LCD_SPI_MISO_GPIO GPIO_PIN(GPIOE, 5) // PE.05 +#define LCD_SPI_MOSI_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #define LTDC_IRQ_PRIO 4 #define DMA_SCREEN_IRQ_PRIO 6 // Backlight // TODO TIM3, TIM8, TIM14, review the channel in backlight_driver.cpp according to the chosen timer -#define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM2 -#define BACKLIGHT_RCC_APB2Periph 0 -#define BACKLIGHT_GPIO GPIOA -#define BACKLIGHT_GPIO_PIN GPIO_Pin_15 -#define BACKLIGHT_GPIO_PinSource GPIO_PinSource15 +#define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 15) // PA.15 #define BACKLIGHT_TIMER TIM2 -#define BACKLIGHT_GPIO_AF GPIO_AF_TIM2 +#define BACKLIGHT_GPIO_AF GPIO_AF1 #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) //used in BOOTLOADER @@ -297,11 +264,7 @@ #define ROTARY_ENCODER_RCC_APB1Periph 0 // SD card -#define SD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_DMA2) -#define SD_RCC_APB1Periph 0 -#define SD_PRESENT_GPIO GPIOH -#define SD_PRESENT_GPIO_PIN GPIO_Pin_10 // PH.10 -#define SD_PRESENT_LL_GPIO_PIN LL_GPIO_PIN_10 // PH.10 +#define SD_PRESENT_GPIO GPIO_PIN(GPIOH, 10) // PH.10 #define SD_SDIO_DMA DMA2 #define SD_SDIO_DMA_STREAM DMA2_Stream3 #define SD_SDIO_DMA_CHANNEL LL_DMA_CHANNEL_4 @@ -325,10 +288,6 @@ #define FLASH_SPI_DMA_TX_STREAM LL_DMA_STREAM_5 #define FLASH_SPI_DMA_RX_STREAM LL_DMA_STREAM_6 -// SDRAM -#define SDRAM_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH) -#define SDRAM_RCC_AHB3Periph RCC_AHB3Periph_FMC - // SPI FLASH #define EEPROM_RCC_AHB1Periph RCC_AHB1Periph_GPIOG #define EEPROM_RCC_APB1Periph RCC_APB1Periph_SPI6 @@ -345,29 +304,23 @@ #define EEPROM_SPI_MOSI_GPIO_PinSource GPIO_PinSource14 // Audio -#define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOH) -#define AUDIO_RCC_APB2Periph RCC_APB2Periph_SPI1 #define AUDIO_XDCS_GPIO GPIOH -#define AUDIO_XDCS_GPIO_PIN GPIO_Pin_14 // PH.14 +#define AUDIO_XDCS_GPIO_PIN LL_GPIO_PIN_14 // PH.14 #define AUDIO_CS_GPIO GPIOH -#define AUDIO_CS_GPIO_PIN GPIO_Pin_13 // PH.13 +#define AUDIO_CS_GPIO_PIN LL_GPIO_PIN_13 // PH.13 #define AUDIO_DREQ_GPIO GPIOH -#define AUDIO_DREQ_GPIO_PIN GPIO_Pin_15 // PH.15 +#define AUDIO_DREQ_GPIO_PIN LL_GPIO_PIN_15 // PH.15 #define AUDIO_RST_GPIO GPIOD -#define AUDIO_RST_GPIO_PIN GPIO_Pin_4 // PD.4 +#define AUDIO_RST_GPIO_PIN LL_GPIO_PIN_4 // PD.04 #define AUDIO_SPI SPI1 -#define AUDIO_SPI_GPIO_AF GPIO_AF_SPI1 +#define AUDIO_SPI_GPIO_AF LL_GPIO_AF_5 #define AUDIO_SPI_SCK_GPIO GPIOB -#define AUDIO_SPI_SCK_GPIO_PIN GPIO_Pin_3 // PB.03 -#define AUDIO_SPI_SCK_GPIO_PinSource GPIO_PinSource3 +#define AUDIO_SPI_SCK_GPIO_PIN LL_GPIO_PIN_3 // PB.03 #define AUDIO_SPI_MISO_GPIO GPIOB -#define AUDIO_SPI_MISO_GPIO_PIN GPIO_Pin_4 // PB.04 -#define AUDIO_SPI_MISO_GPIO_PinSource GPIO_PinSource4 +#define AUDIO_SPI_MISO_GPIO_PIN LL_GPIO_PIN_4 // PB.04 #define AUDIO_SPI_MOSI_GPIO GPIOB -#define AUDIO_SPI_MOSI_GPIO_PIN GPIO_Pin_5 // PB.05 -#define AUDIO_SPI_MOSI_GPIO_PinSource GPIO_PinSource5 -#define AUDIO_MUTE_GPIO GPIOH -#define AUDIO_MUTE_GPIO_PIN GPIO_Pin_8 // PH.08 audio amp control pin +#define AUDIO_SPI_MOSI_GPIO_PIN LL_GPIO_PIN_5 // PB.05 +#define AUDIO_MUTE_GPIO GPIO_PIN(GPIOH, 8) // PH.08 audio amp control pin #define AUDIO_UNMUTE_DELAY 120 // ms #define AUDIO_MUTE_DELAY 500 // ms #define INVERTED_MUTE_PIN @@ -383,11 +336,8 @@ #define TOUCH_I2C_BUS I2C_Bus_1 #define TOUCH_I2C_CLK_RATE 400000 -#define TOUCH_INT_GPIO GPIOB -#define TOUCH_INT_GPIO_PIN LL_GPIO_PIN_9 // PB.09 - -#define TOUCH_RST_GPIO GPIOB -#define TOUCH_RST_GPIO_PIN LL_GPIO_PIN_12 // PB.12 +#define TOUCH_INT_GPIO GPIO_PIN(GPIOB, 9) // PB.09 +#define TOUCH_RST_GPIO GPIO_PIN(GPIOB, 12) // PB.12 #define TOUCH_INT_EXTI_Line LL_EXTI_LINE_9 #define TOUCH_INT_EXTI_Port LL_SYSCFG_EXTI_PORTB @@ -401,46 +351,32 @@ // Haptic: TIM1_CH1 #define HAPTIC_PWM -#define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM1EN -#define HAPTIC_GPIO GPIOA -#define HAPTIC_GPIO_PIN GPIO_Pin_8 +#define HAPTIC_GPIO GPIO_PIN(GPIOA, 8) // PA.08 #define HAPTIC_GPIO_TIMER TIM1 -#define HAPTIC_GPIO_AF GPIO_AF_TIM1 -#define HAPTIC_GPIO_PinSource GPIO_PinSource8 +#define HAPTIC_GPIO_AF GPIO_AF1 #define HAPTIC_TIMER_OUTPUT_ENABLE TIM_CCER_CC1E | TIM_CCER_CC1NE; #define HAPTIC_TIMER_MODE TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE #define HAPTIC_TIMER_COMPARE_VALUE HAPTIC_GPIO_TIMER->CCR1 // Flysky Hall Stick #define FLYSKY_HALL_SERIAL_USART UART4 -#define FLYSKY_HALL_SERIAL_GPIO GPIOA #define FLYSKY_HALL_DMA_Channel LL_DMA_CHANNEL_4 -#define FLYSKY_HALL_SERIAL_TX_GPIO_PIN LL_GPIO_PIN_0 // PA.00 -#define FLYSKY_HALL_SERIAL_RX_GPIO_PIN LL_GPIO_PIN_1 // PA.01 -#define FLYSKY_HALL_SERIAL_GPIO_AF LL_GPIO_AF_8 -#define FLYSKY_HALL_SERIAL_USART_IRQHandler UART4_IRQHandler +#define FLYSKY_HALL_SERIAL_TX_GPIO GPIO_PIN(GPIOA, 0) // PA.00 +#define FLYSKY_HALL_SERIAL_RX_GPIO GPIO_PIN(GPIOA, 1) // PA.01 #define FLYSKY_HALL_SERIAL_USART_IRQn UART4_IRQn #define FLYSKY_HALL_SERIAL_DMA DMA1 #define FLYSKY_HALL_DMA_Stream_RX LL_DMA_STREAM_2 #define FLYSKY_HALL_DMA_Stream_TX LL_DMA_STREAM_4 // Internal Module -#define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_DMA1) -#define INTMODULE_PWR_GPIO GPIOH -#define INTMODULE_PWR_GPIO_PIN GPIO_Pin_9 // PH.09 -#define INTMODULE_GPIO GPIOF -#define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_7 // PF.07 -#define INTMODULE_RX_GPIO_PIN LL_GPIO_PIN_6 // PF.06 +#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOH, 9) // PH.09 +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOF, 7) // PF.07 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOF, 6) // PF.06 #define INTMODULE_USART UART7 -#define INTMODULE_GPIO_AF GPIO_AF_UART7 -#define INTMODULE_GPIO_AF_LL LL_GPIO_AF_8 #define INTMODULE_USART_IRQn UART7_IRQn -#define INTMODULE_USART_IRQHandler UART7_IRQHandler #define INTMODULE_DMA DMA1 #define INTMODULE_DMA_STREAM LL_DMA_STREAM_1 #define INTMODULE_DMA_STREAM_IRQ DMA1_Stream1_IRQn -#define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF1 #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_5 #define INTMODULE_RX_DMA DMA1 @@ -458,26 +394,16 @@ // External Module #define EXTMODULE #define EXTMODULE_PULSES -#define EXTMODULE_PWR_GPIO GPIOD -#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_11 -#define EXTMODULE_PWR_FIX_GPIO GPIOA -#define EXTMODULE_PWR_FIX_GPIO_PIN GPIO_Pin_2 // PA.02 -#define EXTMODULE_RCC_AHB1Periph \ - (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOC | \ - RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_DMA2) -#define EXTMODULE_TX_GPIO GPIOC -#define EXTMODULE_TX_GPIO_PIN LL_GPIO_PIN_6 // PC.06 -#define EXTMODULE_TX_GPIO_AF LL_GPIO_AF_3 // TIM8_CH1 -#define EXTMODULE_TX_GPIO_AF_USART GPIO_AF_USART6 -#define EXTMODULE_RX_GPIO GPIOC -#define EXTMODULE_RX_GPIO_PIN LL_GPIO_PIN_7 // PC.07 -#define EXTMODULE_RX_GPIO_AF_USART GPIO_AF_USART6 +#define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 11) // PD.11 +#define EXTMODULE_PWR_FIX_GPIO GPIO_PIN(GPIOA, 2) // PA.02 +#define EXTMODULE_TX_GPIO GPIO_PIN(GPIOC, 6) // PC.06 +#define EXTMODULE_RX_GPIO GPIO_PIN(GPIOC, 7) // PC.07 #define EXTMODULE_TIMER TIM8 +#define EXTMODULE_TIMER_TX_GPIO_AF LL_GPIO_AF_3 // TIM8_CH1 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH1 #define EXTMODULE_TIMER_IRQn TIM8_UP_TIM13_IRQn #define EXTMODULE_TIMER_IRQHandler TIM8_UP_TIM13_IRQHandler #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) -#define EXTMODULE_TIMER_TX_GPIO_AF LL_GPIO_AF_3 //USART #define EXTMODULE_USART USART6 #define EXTMODULE_USART_GPIO GPIOC @@ -485,46 +411,28 @@ #define EXTMODULE_USART_GPIO_AF_LL LL_GPIO_AF_8 #define EXTMODULE_USART_TX_DMA DMA2 #define EXTMODULE_USART_TX_DMA_CHANNEL LL_DMA_CHANNEL_5 -#define EXTMODULE_USART_TX_DMA_STREAM DMA2_Stream7 -#define EXTMODULE_USART_TX_DMA_STREAM_LL LL_DMA_STREAM_7 - +#define EXTMODULE_USART_TX_DMA_STREAM LL_DMA_STREAM_7 #define EXTMODULE_USART_RX_DMA_CHANNEL LL_DMA_CHANNEL_5 -#define EXTMODULE_USART_RX_DMA_STREAM DMA2_Stream2 -#define EXTMODULE_USART_RX_DMA_STREAM_LL LL_DMA_STREAM_2 - -#define EXTMODULE_USART_IRQHandler USART6_IRQHandler +#define EXTMODULE_USART_RX_DMA_STREAM LL_DMA_STREAM_2 #define EXTMODULE_USART_IRQn USART6_IRQn //TIMER -#define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 -#define EXTMODULE_TIMER_DMA_STREAM DMA2_Stream1 #define EXTMODULE_TIMER_DMA DMA2 -#define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_1 +#define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 +#define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_1 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream1_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA2_Stream1_IRQHandler -#define EXTMODULE_TX_INVERT_GPIO GPIOE -#define EXTMODULE_TX_INVERT_GPIO_PIN GPIO_Pin_3 // PE.03 -#define EXTMODULE_RX_INVERT_GPIO GPIOI -#define EXTMODULE_RX_INVERT_GPIO_PIN GPIO_Pin_15 // PI.15 - -#define EXTMODULE_TX_NORMAL() EXTMODULE_TX_INVERT_GPIO->BSRRH = EXTMODULE_TX_INVERT_GPIO_PIN -#define EXTMODULE_TX_INVERTED() EXTMODULE_TX_INVERT_GPIO->BSRRL = EXTMODULE_TX_INVERT_GPIO_PIN -#define EXTMODULE_RX_NORMAL() EXTMODULE_RX_INVERT_GPIO->BSRRH = EXTMODULE_RX_INVERT_GPIO_PIN -#define EXTMODULE_RX_INVERTED() EXTMODULE_RX_INVERT_GPIO->BSRRL = EXTMODULE_RX_INVERT_GPIO_PIN - -// Heartbeat (not used) -#define HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD -#define HEARTBEAT_GPIO GPIOD -#define HEARTBEAT_GPIO_PIN GPIO_Pin_12 // PD.12 +#define EXTMODULE_TX_INVERT_GPIO GPIO_PIN(GPIOE, 3) // PE.03 +#define EXTMODULE_RX_INVERT_GPIO GPIO_PIN(GPIOI, 15) // PI.15 // Trainer Port #define TRAINER_GPIO GPIOD -#define TRAINER_IN_GPIO_PIN LL_GPIO_PIN_12 // PD.12 +#define TRAINER_IN_GPIO GPIO_PIN(GPIOD, 12) // PD.12 #define TRAINER_IN_TIMER_Channel LL_TIM_CHANNEL_CH1 -#define TRAINER_OUT_GPIO_PIN LL_GPIO_PIN_13 // PD.13 +#define TRAINER_OUT_GPIO GPIO_PIN(GPIOD, 13) // PD.13 #define TRAINER_OUT_TIMER_Channel LL_TIM_CHANNEL_CH2 #define TRAINER_TIMER TIM4 @@ -532,33 +440,19 @@ #define TRAINER_TIMER_IRQHandler TIM4_IRQHandler #define TRAINER_GPIO_AF LL_GPIO_AF_2 #define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - //ROTARY emulation for trims as buttons #define ROTARY_ENCODER_NAVIGATION // Bluetooth -#define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOH) -#define BT_RCC_APB1Periph (RCC_APB1Periph_USART3) -#define BT_RCC_APB2Periph 0 - +#define BLUETOOTH_ON_GPIO GPIO_PIN(GPIOI, 8) // PI.8 #define BT_USART USART3 -#define BT_GPIO_AF GPIO_AF_USART3 #define BT_USART_IRQn USART3_IRQn #define BT_GPIO_TXRX GPIOB -#define BT_TX_GPIO_PIN GPIO_Pin_10 // PB.10 -#define BT_RX_GPIO_PIN GPIO_Pin_11 // PB.11 -#define BT_TX_GPIO_PinSource GPIO_PinSource10 -#define BT_RX_GPIO_PinSource GPIO_PinSource11 -#define BT_USART_IRQHandler USART3_IRQHandler - -#define BT_EN_GPIO GPIOI -#define BT_EN_GPIO_PIN GPIO_Pin_8 // PI.08 - -#define BT_CONNECTED_GPIO GPIOJ -#define BT_CONNECTED_GPIO_PIN GPIO_Pin_1 // PJ.10 - -#define BT_CMD_MODE_GPIO GPIOH -#define BT_CMD_MODE_GPIO_PIN GPIO_Pin_6 // PH.6 +#define BT_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 +#define BT_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 +#define BT_EN_GPIO GPIO_PIN(GPIOI, 8) // PI.08 +#define BT_CONNECTED_GPIO GPIO_PIN(GPIOJ, 10) // PJ.10 +#define BT_CMD_MODE_GPIO GPIO_PIN(GPIOH, 6) // PH.06 // Millisecond timer #define MS_TIMER TIM14 @@ -571,6 +465,9 @@ #define MIXER_SCHEDULER_TIMER_IRQn TIM8_BRK_TIM12_IRQn #define MIXER_SCHEDULER_TIMER_IRQHandler TIM8_BRK_TIM12_IRQHandler +// SDRAM +#define SDRAM_BANK1 + #define LCD_W 320 #define LCD_H 480 diff --git a/radio/src/targets/nv14/haptic_driver.cpp b/radio/src/targets/nv14/haptic_driver.cpp index d8fc8f809..7a9b79a5e 100644 --- a/radio/src/targets/nv14/haptic_driver.cpp +++ b/radio/src/targets/nv14/haptic_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "board.h" void hapticOff(void) @@ -36,16 +40,9 @@ void hapticOn(uint32_t pwmPercent) void hapticInit(void) { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HAPTIC_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HAPTIC_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(HAPTIC_GPIO, HAPTIC_GPIO_PinSource, HAPTIC_GPIO_AF); + gpio_init_af(HAPTIC_GPIO, HAPTIC_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(HAPTIC_GPIO_TIMER); HAPTIC_GPIO_TIMER->ARR = 100; HAPTIC_GPIO_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 10000 - 1; HAPTIC_GPIO_TIMER->CCMR1 = HAPTIC_TIMER_MODE; // PWM @@ -59,5 +56,4 @@ void hapticInit(void) void hapticDone(void) { hapticOff(); - RCC_AHB1PeriphClockCmd(HAPTIC_RCC_AHB1Periph, DISABLE); } diff --git a/radio/src/targets/nv14/lcd_driver.cpp b/radio/src/targets/nv14/lcd_driver.cpp index b61c52bb2..62cd7bc25 100644 --- a/radio/src/targets/nv14/lcd_driver.cpp +++ b/radio/src/targets/nv14/lcd_driver.cpp @@ -21,9 +21,12 @@ #include "stm32_hal_ll.h" #include "stm32_hal.h" + #include "opentx_types.h" #include "dma2d.h" #include "hal.h" +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "delays_driver.h" #include "debug.h" #include "lcd.h" @@ -32,6 +35,8 @@ static LTDC_HandleTypeDef hltdc; static void* initialFrameBuffer = nullptr; +#define GPIO_AF_LTDC GPIO_AF14 + static volatile uint8_t _frame_addr_reloaded = 0; static void startLcdRefresh(lv_disp_drv_t *disp_drv, uint16_t *buffer, @@ -83,67 +88,64 @@ enum ENUM_IO_MODE IO_MODE_ANALOG }; -static void LCD_AF_GPIOConfig(void) { - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); + +static void LCD_AF_GPIOConfig(void) +{ + /* GPIOs Configuration */ /* - ----------------------------------------------------------------------------- - LCD_CLK <-> PG.07 | LCD_HSYNC <-> PI.12 | LCD_R3 <-> PJ.02 | LCD_G5 <-> PK.00 - | LCD VSYNC <-> PI.13 | LCD_R4 <-> PJ.03 | LCD_G6 <-> PK.01 - | | LCD_R5 <-> PJ.04 | LCD_G7 <-> PK.02 - | | LCD_R6 <-> PJ.05 | LCD_B4 <-> PK.03 - | | LCD_R7 <-> PJ.06 | LCD_B5 <-> PK.04 - | | LCD_G2 <-> PJ.09 | LCD_B6 <-> PK.05 - | | LCD_G3 <-> PJ.10 | LCD_B7 <-> PK.06 - | | LCD_G4 <-> PJ.11 | LCD_DE <-> PK.07 - | | LCD_B3 <-> PJ.15 | - */ + +---------------------+---------------------+------------------+------------------+ + + LCD pins assignment + + +---------------------+---------------------+------------------+------------------+ + | LCD_CLK <-> PG.07 | LCD_HSYNC <-> PI.12 | LCD_R3 <-> PJ.02 | LCD_G5 <-> PK.00 | + | LCD VSYNC <-> PI.13 | LCD_R4 <-> PJ.03 | LCD_G6 <-> PK.01 | | + | | LCD_R5 <-> PJ.04 | LCD_G7 <-> PK.02 | | + | | LCD_R6 <-> PJ.05 | LCD_B4 <-> PK.03 | | + | | LCD_R7 <-> PJ.06 | LCD_B5 <-> PK.04 | | + | | LCD_G2 <-> PJ.09 | LCD_B6 <-> PK.05 | | + | | LCD_G3 <-> PJ.10 | LCD_B7 <-> PK.06 | | + | | LCD_G4 <-> PJ.11 | LCD_DE <-> PK.07 | | + | | LCD_B3 <-> PJ.15 | | | + +---------------------+---------------------+------------------+------------------+ + */ // GPIOG configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_7; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_ALTERNATE; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - GPIO_InitStructure.Alternate = LL_GPIO_AF_14; // AF LTDC - LL_GPIO_Init(GPIOG, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOG, 7), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOI configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_12 | LL_GPIO_PIN_13; - LL_GPIO_Init(GPIOI, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOI, 12), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOI, 13), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOJ configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | LL_GPIO_PIN_15; - LL_GPIO_Init(GPIOJ, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOJ, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 9), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 10), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 11), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 15), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOK configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7; - LL_GPIO_Init(GPIOK, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOK, 0), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 1), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 7), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); } -static void lcdSpiConfig(void) { - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_SPI_SCK_GPIO_PIN | LCD_SPI_MOSI_GPIO_PIN; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_SPI_CS_GPIO_PIN; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_UP; - LL_GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_NRST_GPIO_PIN; - LL_GPIO_Init(LCD_NRST_GPIO, &GPIO_InitStructure); +static void lcdSpiConfig(void) +{ + gpio_init(LCD_SPI_SCK_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_SPI_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_SPI_CS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_NRST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); /* Set the chip select pin aways low */ - LCD_CS_LOW(); + CLR_LCD_CS(); } void lcdDelay() { @@ -154,25 +156,25 @@ unsigned char LCD_ReadByteOnFallingEdge(void) { unsigned int i; unsigned char ReceiveData = 0; - LCD_MOSI_HIGH(); - LCD_MOSI_AS_INPUT(); + SET_LCD_DATA(); + SET_LCD_DATA_INPUT(); for (i = 0; i < 8; i++) { LCD_DELAY(); - LCD_SCK_HIGH(); + SET_LCD_CLK(); LCD_DELAY(); LCD_DELAY(); ReceiveData <<= 1; - LCD_SCK_LOW(); + CLR_LCD_CLK(); LCD_DELAY(); LCD_DELAY(); - if (LCD_READ_DATA_PIN()) { + if (READ_LCD_DATA_PIN()) { ReceiveData |= 0x01; } } - LCD_MOSI_AS_OUTPUT(); + SET_LCD_DATA_OUTPUT(); return (ReceiveData); } @@ -213,22 +215,22 @@ unsigned char LCD_ReadByte(void) { unsigned int i; unsigned char ReceiveData = 0; - LCD_MOSI_HIGH(); - LCD_MOSI_AS_INPUT(); + SET_LCD_DATA(); + SET_LCD_DATA_INPUT(); for (i = 0; i < 8; i++) { - LCD_SCK_LOW(); + CLR_LCD_CLK(); LCD_DELAY(); LCD_DELAY(); ReceiveData <<= 1; - LCD_SCK_HIGH(); + SET_LCD_CLK(); LCD_DELAY(); LCD_DELAY(); - if (LCD_READ_DATA_PIN()) { + if (READ_LCD_DATA_PIN()) { ReceiveData |= 0x01; } } - LCD_SCK_LOW(); - LCD_MOSI_AS_OUTPUT(); + CLR_LCD_CLK(); + SET_LCD_DATA_OUTPUT(); return (ReceiveData); } @@ -1075,7 +1077,7 @@ unsigned int LCD_ST7796S_ReadID(void) { lcdWriteCommand( 0XD3 ); - LCD_MOSI_AS_INPUT(); + SET_LCD_DATA_INPUT(); LCD_SCK_LOW(); LCD_DELAY(); LCD_DELAY(); diff --git a/radio/src/targets/nv14/lcd_driver.h b/radio/src/targets/nv14/lcd_driver.h index 4d0e45bee..6f0820f00 100644 --- a/radio/src/targets/nv14/lcd_driver.h +++ b/radio/src/targets/nv14/lcd_driver.h @@ -50,22 +50,30 @@ extern lcdSpiInitFucPtr lcdOnFunction; #define SET_IO_INPUT( PORT, PIN ) LL_GPIO_SetPinMode( PORT, PIN, LL_GPIO_MODE_INPUT ) #define SET_IO_OUTPUT( PORT, PIN ) LL_GPIO_SetPinMode( PORT, PIN, LL_GPIO_MODE_OUTPUT ) -#define LCD_NRST_HIGH() LL_GPIO_SetOutputPin(LCD_NRST_GPIO, LCD_NRST_GPIO_PIN) -#define LCD_NRST_LOW() LL_GPIO_ResetOutputPin(LCD_NRST_GPIO, LCD_NRST_GPIO_PIN) +#define LCD_NRST_HIGH() gpio_write(LCD_NRST_GPIO, 1) +#define LCD_NRST_LOW() gpio_write(LCD_NRST_GPIO, 0) -#define LCD_CS_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_CS_GPIO_PIN) -#define LCD_CS_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_CS_GPIO_PIN) +#define LCD_CS_HIGH() gpio_write(LCD_SPI_CS_GPIO, 1) +#define LCD_CS_LOW() gpio_write(LCD_SPI_CS_GPIO, 0) -#define LCD_SCK_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_SCK_GPIO_PIN) -#define LCD_SCK_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_SCK_GPIO_PIN) +#define LCD_SCK_HIGH() gpio_write(LCD_SPI_SCK_GPIO, 1) +#define LCD_SCK_LOW() gpio_write(LCD_SPI_SCK_GPIO, 0) -#define LCD_MOSI_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) -#define LCD_MOSI_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) +#define LCD_MOSI_HIGH() gpio_write(LCD_SPI_MOSI_GPIO, 1) +#define LCD_MOSI_LOW() gpio_write(LCD_SPI_MOSI_GPIO, 0) -#define LCD_MOSI_AS_INPUT() SET_IO_INPUT( LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN ) -#define LCD_MOSI_AS_OUTPUT() SET_IO_OUTPUT( LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN ) +#define SET_LCD_CS() LCD_CS_HIGH() +#define CLR_LCD_CS() LCD_CS_LOW() + +#define SET_LCD_CLK() LCD_SCK_HIGH() +#define CLR_LCD_CLK() LCD_SCK_LOW() + +#define SET_LCD_DATA() gpio_write(LCD_SPI_MOSI_GPIO, 1) +#define CLR_LCD_DATA() gpio_write(LCD_SPI_MOSI_GPIO, 0) +#define SET_LCD_DATA_INPUT() gpio_init(LCD_SPI_MOSI_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW) +#define SET_LCD_DATA_OUTPUT() gpio_init(LCD_SPI_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW) +#define READ_LCD_DATA_PIN() gpio_read(LCD_SPI_MOSI_GPIO) -#define LCD_READ_DATA_PIN() LL_GPIO_IsInputPinSet(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) #if 1 diff --git a/radio/src/targets/nv14/sdram_driver.c b/radio/src/targets/nv14/sdram_driver.c deleted file mode 100644 index 2cc88ae84..000000000 --- a/radio/src/targets/nv14/sdram_driver.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" -#include "stm32f4xx_fmc.h" - -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_FULL_PAGE ((uint16_t)0x0007) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_1 ((uint16_t)0x0010) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -void SDRAM_GPIOConfig(void) -{ - /* - ------------------------------------------------------------------------------------------------------------------------------------------------ - PC3 <-> FMC_SDCKE0 | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | PH3 <-> FMC_SDNE0 | PI0 <-> FMC_D24 - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | PH5 <-> FMC_SDNWE | PI1 <-> FMC_D25 - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG4 <-> FMC_BA0 | PH8 <-> FMC_D16 | PI2 <-> FMC_D26 - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG5 <-> FMC_BA1 | PH9 <-> FMC_D17 | PI3 <-> FMC_D27 - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 | PG8 <-> FMC_SDCLK | PH10 <-> FMC_D18 | PI4 <-> FMC_NBL2 - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | PG15 <-> FMC_NCAS | PH11 <-> FMC_D19 | PI5 <-> FMC_NBL3 - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | | PH12 <-> FMC_D20 | PI6 <-> FMC_D28 - | | PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | | PH13 <-> FMC_D21 | PI7 <-> FMC_D29 - | | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | | PH14 <-> FMC_D22 | PI9 <-> FMC_D30 - | | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | | PH15 <-> FMC_D23 | PI10 <-> FMC_D31 - | | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | | | - */ - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* GPIOC configuration */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3 , GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* GPIOD configuration */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* GPIOE configuration */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* GPIOF configuration */ - GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource2, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource3, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource4, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource5, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource11, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource13, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* GPIOG configuration */ - GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /* GPIOH configuration */ - GPIO_PinAFConfig(GPIOH, GPIO_PinSource3, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOH, GPIO_PinSource5, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5; - GPIO_Init(GPIOH, &GPIO_InitStructure); -} - -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - - /* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - delay_ms(100); - - /* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 8 --------------------------------------------------------------------*/ - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(683);//904 - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } -} - - -void SDRAM_Init(void) -{ - //delay funcion needed - delaysInit(); - // Clocks must be enabled here, because the sdramInit is called before main - RCC_AHB1PeriphClockCmd(SDRAM_RCC_AHB1Periph, ENABLE); - RCC_AHB3PeriphClockCmd(SDRAM_RCC_AHB3Periph, ENABLE); - - /* GPIO configuration for FMC SDRAM bank */ - SDRAM_GPIOConfig(); - - /* FMC Configuration ---------------------------------------------------------*/ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM Bank configuration */ - /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=70 (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: min=1+ 7ns (1+1x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - - /* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank1_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; - FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_Enable; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAM_InitSequence(); -} diff --git a/radio/src/targets/nv14/touch_driver.cpp b/radio/src/targets/nv14/touch_driver.cpp index b688e2cec..568f4806f 100644 --- a/radio/src/targets/nv14/touch_driver.cpp +++ b/radio/src/targets/nv14/touch_driver.cpp @@ -19,6 +19,8 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "stm32_hal_ll.h" #include "stm32_hal.h" #include "stm32_i2c_driver.h" @@ -66,46 +68,6 @@ static void _cst836u_exti_isr(void) touchEventOccured = true; } -static void TOUCH_AF_ExtiStop(void) -{ - stm32_exti_disable(TOUCH_INT_EXTI_Line); -} - -static void TOUCH_AF_ExtiConfig(void) -{ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - LL_SYSCFG_SetEXTISource(TOUCH_INT_EXTI_Port, TOUCH_INT_EXTI_SysCfgLine); - - stm32_exti_enable(TOUCH_INT_EXTI_Line, - LL_EXTI_TRIGGER_FALLING, - _cst836u_exti_isr); -} - -static void TOUCH_AF_GPIOConfig(void) -{ - LL_GPIO_InitTypeDef gpioInit; - LL_GPIO_StructInit(&gpioInit); - - stm32_gpio_enable_clock(TOUCH_RST_GPIO); - stm32_gpio_enable_clock(TOUCH_INT_GPIO); - - gpioInit.Mode = LL_GPIO_MODE_OUTPUT; - gpioInit.Speed = LL_GPIO_SPEED_FREQ_LOW; - gpioInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - gpioInit.Pull = LL_GPIO_PULL_NO; - - gpioInit.Pin = TOUCH_RST_GPIO_PIN; - LL_GPIO_Init(TOUCH_RST_GPIO, &gpioInit); - LL_GPIO_SetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); - - gpioInit.Pin = TOUCH_INT_GPIO_PIN; - gpioInit.Mode = LL_GPIO_MODE_INPUT; - gpioInit.Pull = LL_GPIO_PULL_UP; - gpioInit.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; - LL_GPIO_Init(TOUCH_INT_GPIO, &gpioInit); - LL_GPIO_SetOutputPin(TOUCH_INT_GPIO, TOUCH_INT_GPIO_PIN); -} - void I2C_Init_Radio(void) { TRACE("CST836U I2C Init"); @@ -397,9 +359,9 @@ static uint8_t cst836u_TS_DetectTouch() void TouchReset() { - LL_GPIO_ResetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); + gpio_clear(TOUCH_RST_GPIO); delay_ms(10); - LL_GPIO_SetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); + gpio_set(TOUCH_RST_GPIO); delay_ms(300); } @@ -433,12 +395,11 @@ void detectTouchController() void TouchInit(void) { - TOUCH_AF_GPIOConfig(); + gpio_init(TOUCH_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); I2C_Init_Radio(); TouchReset(); detectTouchController(); - TOUCH_AF_ExtiConfig(); - + gpio_init_int(TOUCH_INT_GPIO, GPIO_IN_PU, GPIO_FALLING, _cst836u_exti_isr); tc->printDebugInfo(); } diff --git a/radio/src/targets/pl18/CMakeLists.txt b/radio/src/targets/pl18/CMakeLists.txt index 9dbe8911d..8bfbdc8e6 100644 --- a/radio/src/targets/pl18/CMakeLists.txt +++ b/radio/src/targets/pl18/CMakeLists.txt @@ -115,11 +115,11 @@ set(FIRMWARE_TARGET_SRC battery_driver.cpp backlight_driver.cpp led_driver.cpp - sdram_driver.c ) set(FIRMWARE_SRC ${FIRMWARE_SRC} + targets/common/arm/stm32/sdram_driver.cpp targets/common/arm/stm32/audio_dac_driver.cpp targets/common/arm/stm32/dma2d.cpp targets/common/arm/stm32/spi_flash.cpp diff --git a/radio/src/targets/pl18/backlight_driver.cpp b/radio/src/targets/pl18/backlight_driver.cpp index 3ddd078c2..3996e0926 100644 --- a/radio/src/targets/pl18/backlight_driver.cpp +++ b/radio/src/targets/pl18/backlight_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "opentx_types.h" #include "board.h" @@ -27,30 +31,17 @@ void backlightLowInit( void ) { - RCC_AHB1PeriphClockCmd(BACKLIGHT_RCC_AHB1Periph, ENABLE); - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_WriteBit( BACKLIGHT_GPIO, BACKLIGHT_GPIO_PIN, Bit_RESET ); + gpio_init(BACKLIGHT_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_clear(BACKLIGHT_GPIO); } void backlightInit() { // PIN init - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); // TODO review this when the timer will be chosen + stm32_timer_enable_clock(BACKLIGHT_TIMER); BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 1000000 - 1; // 10kHz (same as FrOS) BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE; // PWM mode 1 @@ -81,7 +72,7 @@ void lcdOff() { backlightEnable(0); } -void lcdOn(){ +void lcdOn() { if(lcdOnFunction) lcdOnFunction(); else lcdInit(); backlightEnable(BACKLIGHT_LEVEL_MAX); diff --git a/radio/src/targets/pl18/battery_driver.cpp b/radio/src/targets/pl18/battery_driver.cpp index 7141628b4..1a93916a0 100644 --- a/radio/src/targets/pl18/battery_driver.cpp +++ b/radio/src/targets/pl18/battery_driver.cpp @@ -260,34 +260,20 @@ bool isChargerActive() void battery_charge_init() { - GPIO_InitTypeDef GPIO_InitStructure; - - // Input pins - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - // USB charger status pins - GPIO_InitStructure.GPIO_Pin = UCHARGER_GPIO_PIN; - GPIO_Init(UCHARGER_GPIO, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = UCHARGER_CHARGE_END_GPIO_PIN; - GPIO_Init(UCHARGER_CHARGE_END_GPIO, &GPIO_InitStructure); + gpio_init(UCHARGER_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + gpio_init(UCHARGER_CHARGE_END_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); #if defined(WIRELESS_CHARGER) // Wireless charger status pins - GPIO_InitStructure.GPIO_Pin = WCHARGER_GPIO_PIN; - GPIO_Init(WCHARGER_GPIO, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = WCHARGER_CHARGE_END_GPIO_PIN; - GPIO_Init(WCHARGER_CHARGE_END_GPIO, &GPIO_InitStructure); + gpio_init(WCHARGER_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + gpio_init(WCHARGER_CHARGE_END_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); + #endif - // Output pins - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; // USB charger control pins - GPIO_InitStructure.GPIO_Pin = UCHARGER_EN_GPIO_PIN; - GPIO_Init(UCHARGER_EN_GPIO, &GPIO_InitStructure); + gpio_init(UCHARGER_EN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); // USB charger state init ENABLE_UCHARGER(); @@ -297,10 +283,8 @@ void battery_charge_init() #if defined(WIRELESS_CHARGER) // Wireless charger control pins - GPIO_InitStructure.GPIO_Pin = WCHARGER_EN_GPIO_PIN; - GPIO_Init(WCHARGER_EN_GPIO, &GPIO_InitStructure); - GPIO_InitStructure.GPIO_Pin = WCHARGER_I_CONTROL_GPIO_PIN; - GPIO_Init(WCHARGER_I_CONTROL_GPIO, &GPIO_InitStructure); + gpio_init(WCHARGER_EN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(WCHARGER_I_CONTROL_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); // Wireless charger state init ENABLE_WCHARGER(); @@ -308,7 +292,6 @@ void battery_charge_init() wCharger.hasCharger = !IS_WCHARGER_ACTIVE(); // Init for sampling count works wCharger.isChargerDetectionReady = false; resetChargeEndDetection(&wCharger); - #endif } diff --git a/radio/src/targets/pl18/battery_driver.h b/radio/src/targets/pl18/battery_driver.h index 6fdd651d5..60460686c 100644 --- a/radio/src/targets/pl18/battery_driver.h +++ b/radio/src/targets/pl18/battery_driver.h @@ -31,6 +31,9 @@ #include "board.h" #include "hal.h" +#include "hal/gpio.h" +#include "stm32_gpio.h" + enum ChargeState { CHARGE_UNKNOWN, @@ -39,17 +42,17 @@ enum ChargeState CHARGE_FINISHED }; -#define IS_UCHARGER_ACTIVE() GPIO_ReadInputDataBit(UCHARGER_GPIO, UCHARGER_GPIO_PIN) -#define IS_UCHARGER_CHARGE_END_ACTIVE() GPIO_ReadInputDataBit(UCHARGER_CHARGE_END_GPIO, UCHARGER_CHARGE_END_GPIO_PIN) -#define ENABLE_UCHARGER() GPIO_SetBits(UCHARGER_EN_GPIO, UCHARGER_EN_GPIO_PIN) -#define DISABLE_UCHARGER() GPIO_ResetBits(UCHARGER_EN_GPIO, UCHARGER_EN_GPIO_PIN) +#define IS_UCHARGER_ACTIVE() gpio_read(UCHARGER_GPIO) ? 1 : 0 +#define IS_UCHARGER_CHARGE_END_ACTIVE() gpio_read(UCHARGER_CHARGE_END_GPIO) ? 1 : 0 +#define ENABLE_UCHARGER() gpio_set(UCHARGER_EN_GPIO) +#define DISABLE_UCHARGER() gpio_clear(UCHARGER_EN_GPIO) -#define IS_WCHARGER_ACTIVE() GPIO_ReadInputDataBit(WCHARGER_GPIO, WCHARGER_GPIO_PIN) -#define IS_WCHARGER_CHARGE_END_ACTIVE() GPIO_ReadInputDataBit(WCHARGER_CHARGE_END_GPIO, WCHARGER_CHARGE_END_GPIO_PIN) -#define ENABLE_WCHARGER() GPIO_SetBits(WCHARGER_EN_GPIO, WCHARGER_EN_GPIO_PIN) -#define DISABLE_WCHARGER() GPIO_ResetBits(WCHARGER_EN_GPIO, WCHARGER_EN_GPIO_PIN) -#define WCHARGER_CURRENT_LOW() GPIO_ResetBits(WCHARGER_I_CONTROL_GPIO, WCHARGER_I_CONTROL_GPIO_PIN) -#define WCHARGER_CURRENT_HIGH() GPIO_SetBits(WCHARGER_I_CONTROL_GPIO, WCHARGER_I_CONTROL_GPIO_PIN) +#define IS_WCHARGER_ACTIVE() gpio_read(WCHARGER_GPIO) ? 1 : 0 +#define IS_WCHARGER_CHARGE_END_ACTIVE() gpio_read(WCHARGER_CHARGE_END_GPIO) ? 1 : 0 +#define ENABLE_WCHARGER() gpio_set(WCHARGER_EN_GPIO) +#define DISABLE_WCHARGER() gpio_clear(WCHARGER_EN_GPIO) +#define WCHARGER_CURRENT_LOW() gpio_set(WCHARGER_I_CONTROL_GPIO) +#define WCHARGER_CURRENT_HIGH() gpio_clear(WCHARGER_I_CONTROL_GPIO) extern void battery_charge_init(); extern void handle_battery_charge(uint32_t last_press_time); diff --git a/radio/src/targets/pl18/board.cpp b/radio/src/targets/pl18/board.cpp index dc64dbb29..c3fe9a69f 100644 --- a/radio/src/targets/pl18/board.cpp +++ b/radio/src/targets/pl18/board.cpp @@ -20,6 +20,7 @@ */ #include "stm32_adc.h" +#include "stm32_gpio.h" #include "stm32_gpio_driver.h" #include "stm32_ws2812.h" @@ -34,6 +35,7 @@ #include "hal/abnormal_reboot.h" #include "hal/watchdog_driver.h" #include "hal/usb_driver.h" +#include "hal/gpio.h" #include "globals.h" #include "sdcard.h" @@ -72,24 +74,8 @@ void delay_self(int count) for (; count > 0; count--); } } -#define RCC_AHB1PeriphMinimum (PWR_RCC_AHB1Periph |\ - LCD_RCC_AHB1Periph |\ - BACKLIGHT_RCC_AHB1Periph |\ - SDRAM_RCC_AHB1Periph \ - ) -#define RCC_AHB1PeriphOther (AUDIO_RCC_AHB1Periph |\ - TELEMETRY_RCC_AHB1Periph |\ - HAPTIC_RCC_AHB1Periph |\ - INTMODULE_RCC_AHB1Periph |\ - EXTMODULE_RCC_AHB1Periph \ - ) -#define RCC_AHB3PeriphMinimum (SDRAM_RCC_AHB3Periph) -#define RCC_APB1PeriphMinimum (BACKLIGHT_RCC_APB1Periph) -#define RCC_APB1PeriphOther (TELEMETRY_RCC_APB1Periph |\ - AUDIO_RCC_APB1Periph \ - ) +#define RCC_AHB1PeriphMinimum (LCD_RCC_AHB1Periph) #define RCC_APB2PeriphMinimum (LCD_RCC_APB2Periph) -#define RCC_APB2PeriphOther (HAPTIC_RCC_APB2Periph) void ledStripOff() { @@ -102,14 +88,7 @@ void ledStripOff() void boardBootloaderInit() { // USB charger status pins - stm32_gpio_enable_clock(UCHARGER_GPIO); - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_InitStructure.GPIO_Pin = UCHARGER_GPIO_PIN; - GPIO_Init(UCHARGER_GPIO, &GPIO_InitStructure); + gpio_init(UCHARGER_GPIO, GPIO_IN, GPIO_PIN_SPEED_LOW); } void boardInit() @@ -119,11 +98,8 @@ void boardInit() #endif #if !defined(SIMU) - RCC_AHB1PeriphClockCmd(RCC_AHB1PeriphMinimum | RCC_AHB1PeriphOther, ENABLE); - RCC_AHB3PeriphClockCmd(RCC_AHB3PeriphMinimum, ENABLE); - RCC_APB1PeriphClockCmd(RCC_APB1PeriphMinimum | RCC_APB1PeriphOther, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2PeriphMinimum | RCC_APB2PeriphOther, ENABLE); - + LL_AHB1_GRP1_EnableClock(RCC_AHB1PeriphMinimum); + LL_APB2_GRP1_EnableClock(RCC_APB2PeriphMinimum); // enable interrupts __enable_irq(); #endif @@ -195,13 +171,13 @@ void boardInit() lcdSetInitalFrameBuffer(lcdFront->getData()); #if defined(DEBUG) - DBGMCU_APB1PeriphConfig( +/* DBGMCU_APB1PeriphConfig( DBGMCU_IWDG_STOP | DBGMCU_TIM1_STOP | DBGMCU_TIM2_STOP | DBGMCU_TIM3_STOP | DBGMCU_TIM4_STOP | DBGMCU_TIM5_STOP | DBGMCU_TIM6_STOP | DBGMCU_TIM7_STOP | DBGMCU_TIM8_STOP | DBGMCU_TIM9_STOP | DBGMCU_TIM10_STOP | DBGMCU_TIM11_STOP | DBGMCU_TIM12_STOP | DBGMCU_TIM13_STOP | DBGMCU_TIM14_STOP, - ENABLE); + ENABLE);*/ #endif } @@ -263,8 +239,7 @@ int usbPlugged() static uint8_t debouncedState = 0; static uint8_t lastState = 0; - uint8_t state = GPIO_ReadInputDataBit(UCHARGER_GPIO, UCHARGER_GPIO_PIN); - + uint8_t state = gpio_read(UCHARGER_GPIO) ? 1 : 0; if (state == lastState) debouncedState = state; else diff --git a/radio/src/targets/pl18/board.h b/radio/src/targets/pl18/board.h index 461c1f820..184a6f012 100644 --- a/radio/src/targets/pl18/board.h +++ b/radio/src/targets/pl18/board.h @@ -63,18 +63,18 @@ uint32_t isFirmwareStart(const uint8_t * buffer); uint32_t isBootloaderStart(const uint8_t * buffer); // SDRAM driver -void SDRAM_Init(); +extern "C" void SDRAM_Init(); // Pulses driver #if !defined(SIMU) -#define INTERNAL_MODULE_ON() GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) -#define INTERNAL_MODULE_OFF() GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) -#define EXTERNAL_MODULE_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) -#define EXTERNAL_MODULE_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) +#define INTERNAL_MODULE_ON() gpio_set(INTMODULE_PWR_GPIO) +#define INTERNAL_MODULE_OFF() gpio_clear(INTMODULE_PWR_GPIO); +#define EXTERNAL_MODULE_ON() gpio_set(EXTMODULE_PWR_GPIO) +#define EXTERNAL_MODULE_OFF() gpio_clear(EXTMODULE_PWR_GPIO) #define EXTERNAL_MODULE_PWR_OFF EXTERNAL_MODULE_OFF -#define BLUETOOTH_MODULE_ON() GPIO_ResetBits(BT_EN_GPIO, BT_EN_GPIO_PIN) -#define BLUETOOTH_MODULE_OFF() GPIO_SetBits(BT_EN_GPIO, BT_EN_GPIO_PIN) +#define BLUETOOTH_MODULE_ON() gpio_clear(BLUETOOTH_ON_GPIO) +#define BLUETOOTH_MODULE_OFF() gpio_set(BLUETOOTH_ON_GPIO) #define IS_INTERNAL_MODULE_ON() (false) #define IS_EXTERNAL_MODULE_ON() (GPIO_ReadInputDataBit(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) == Bit_SET) diff --git a/radio/src/targets/pl18/extmodule_helper.cpp b/radio/src/targets/pl18/extmodule_helper.cpp deleted file mode 100644 index dbb02e90b..000000000 --- a/radio/src/targets/pl18/extmodule_helper.cpp +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) EdgeTX - * - * Based on code named - * opentx - https://github.com/opentx/opentx - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" - -void EXTERNAL_MODULE_ON() -{ - GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); -} - -void EXTERNAL_MODULE_OFF() -{ - GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN); -} - -void extModuleInit() -{ - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = EXTMODULE_TX_INVERT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(EXTMODULE_TX_INVERT_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = EXTMODULE_RX_INVERT_GPIO_PIN; - GPIO_Init(EXTMODULE_RX_INVERT_GPIO, &GPIO_InitStructure); - - EXTMODULE_TX_INVERTED(); - EXTMODULE_RX_INVERTED(); -} diff --git a/radio/src/targets/pl18/hal.h b/radio/src/targets/pl18/hal.h index c819089bb..71a4a0dcd 100644 --- a/radio/src/targets/pl18/hal.h +++ b/radio/src/targets/pl18/hal.h @@ -305,38 +305,21 @@ #endif // Power -#define PWR_RCC_AHB1Periph RCC_AHB1Periph_GPIOI -#define PWR_ON_GPIO GPIOI -#define PWR_SWITCH_GPIO GPIOI -#define PWR_SWITCH_GPIO_PIN GPIO_Pin_11 // PI.11 -#define PWR_ON_GPIO_PIN GPIO_Pin_14 // PI.14 +#define PWR_SWITCH_GPIO GPIO_PIN(GPIOI, 11) // PI.11 +#define PWR_ON_GPIO GPIO_PIN(GPIOI, 14) // PI.14 // Chargers (USB and wireless) -#define CHARGER_RCC_AHB1Periph ( RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI ) +#define UCHARGER_GPIO GPIO_PIN(GPIOB, 14) // PB.14 input -#define UCHARGER_GPIO GPIOB -#define UCHARGER_GPIO_PIN GPIO_Pin_14 // PB.14 input +#define UCHARGER_CHARGE_END_GPIO GPIO_PIN(GPIOB, 13) // PB.13 input -#define UCHARGER_CHARGE_END_GPIO GPIOB -#define UCHARGER_CHARGE_END_GPIO_PIN GPIO_Pin_13 // PB.13 input - -#define UCHARGER_EN_GPIO GPIOG -#define UCHARGER_EN_GPIO_PIN GPIO_Pin_3 // PG.03 output +#define UCHARGER_EN_GPIO GPIO_PIN(GPIOG, 3) // PG.03 output #if defined (WIRELESS_CHARGER) - - #define WCHARGER_GPIO GPIOI - #define WCHARGER_GPIO_PIN GPIO_Pin_9 // PI.09 input - - #define WCHARGER_CHARGE_END_GPIO GPIOI - #define WCHARGER_CHARGE_END_GPIO_PIN GPIO_Pin_10 // PI.10 input - - #define WCHARGER_EN_GPIO GPIOH - #define WCHARGER_EN_GPIO_PIN GPIO_Pin_4 // PH.04 output - - #define WCHARGER_I_CONTROL_GPIO GPIOH - #define WCHARGER_I_CONTROL_GPIO_PIN GPIO_Pin_13 // PH.13 output - + #define WCHARGER_GPIO GPIO_PIN(GPIOI, 9) // PI.09 input + #define WCHARGER_CHARGE_END_GPIO GPIO_PIN(GPIOI, 10) // PI.10 input + #define WCHARGER_EN_GPIO GPIO_PIN(GPIOH, 4) // PH.04 output + #define WCHARGER_I_CONTROL_GPIO GPIO_PIN(GPIOH, 13) // PH.13 output #endif // TODO! Check IOLL1 to PI.01 connectivity! @@ -376,29 +359,23 @@ // Telemetry #define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_DMA1) #define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_REV_GPIO GPIOJ -#define TELEMETRY_RX_REV_GPIO_PIN GPIO_Pin_8 // PJ.08 -#define TELEMETRY_TX_REV_GPIO_PIN GPIO_Pin_7 // PJ.07 -#define TELEMETRY_DIR_GPIO GPIOJ -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_13 // PJ.13 +#define TELEMETRY_RX_REV_GPIO GPIO_PIN(GPIOJ, 8) // PJ.08 +#define TELEMETRY_TX_REV_GPIO GPIO_PIN(GPIOJ, 7) // PJ.07 +#define TELEMETRY_DIR_GPIO GPIO_PIN(GPIOJ, 13) // PJ.13 #define TELEMETRY_SET_INPUT 1 -#define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_TX_GPIO GPIO_PIN(GPIOD, 5) // PD.05 +#define TELEMETRY_RX_GPIO GPIO_PIN(GPIOD, 6) // PD.06 #define TELEMETRY_USART USART2 +#define TELEMETRY_USART_IRQn USART2_IRQn #define TELEMETRY_DMA DMA1 #define TELEMETRY_DMA_Stream_TX LL_DMA_STREAM_6 -#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 +#define TELEMETRY_DMA_Channel_TX LL_DMA_CHANNEL_4 #define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn #define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler #define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 // #define TELEMETRY_DMA_Stream_RX LL_DMA_STREAM_5 // #define TELEMETRY_DMA_Channel_RX LL_DMA_CHANNEL_4 #define TELEMETRY_USART_IRQHandler USART2_IRQHandler -#define TELEMETRY_USART_IRQn USART2_IRQn #define TELEMETRY_DIR_OUTPUT() TELEMETRY_DIR_GPIO->BSRRH = TELEMETRY_DIR_GPIO_PIN #define TELEMETRY_DIR_INPUT() TELEMETRY_DIR_GPIO->BSRRL = TELEMETRY_DIR_GPIO_PIN @@ -415,36 +392,28 @@ // USB #define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA #define USB_GPIO GPIOA -// #define USB_GPIO_PIN_VBUS LL_GPIO_PIN_9 // PA.09 -#define USB_GPIO_PIN_ID LL_GPIO_PIN_10 // PA.10 -#define USB_GPIO_PIN_DM LL_GPIO_PIN_11 // PA.11 -#define USB_GPIO_PIN_DP LL_GPIO_PIN_12 // PA.12 -#define USB_GPIO_AF GPIO_AF_OTG1_FS +// #define USB_GPIO_VBUS GPIO_PIN(GPIOA,9) // PA.09 +#define USB_GPIO_DM GPIO_PIN(GPIOA, 11) // PA.11 +#define USB_GPIO_DP GPIO_PIN(GPIOA, 12) // PA.12 +#define USB_GPIO_AF GPIO_AF10 // LCD -#define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOJ | RCC_AHB1Periph_GPIOK | RCC_AHB1Periph_DMA2D) -#define LCD_RCC_APB1Periph 0 -#define LCD_RCC_APB2Periph RCC_APB2Periph_LTDC -#define LCD_NRST_GPIO GPIOG -#define LCD_NRST_GPIO_PIN LL_GPIO_PIN_9 // PG.09 -#define LCD_SPI_GPIO GPIOE -#define LCD_SPI_CS_GPIO_PIN LL_GPIO_PIN_4 // PE.04 -#define LCD_SPI_SCK_GPIO_PIN LL_GPIO_PIN_2 // PE.02 -#define LCD_SPI_MISO_GPIO_PIN LL_GPIO_PIN_5 // PE.05 -#define LCD_SPI_MOSI_GPIO_PIN LL_GPIO_PIN_6 // PE.06 +#define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA2D +#define LCD_RCC_APB2Periph LL_APB2_GRP1_PERIPH_LTDC +#define LCD_NRST_GPIO GPIO_PIN(GPIOG, 9) // PG.09 +#define LCD_SPI_CS_GPIO GPIO_PIN(GPIOE, 4) // PE.04 +#define LCD_SPI_SCK_GPIO GPIO_PIN(GPIOE, 2) // PE.02 +#define LCD_SPI_MISO_GPIO GPIO_PIN(GPIOE, 5) // PE.05 +#define LCD_SPI_MOSI_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #define LTDC_IRQ_PRIO 4 #define DMA_SCREEN_IRQ_PRIO 6 // Backlight // TODO TIM3, TIM8, TIM14, review the channel in backlight_driver.cpp according to the chosen timer -#define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM2 #define BACKLIGHT_RCC_APB2Periph 0 -#define BACKLIGHT_GPIO GPIOA -#define BACKLIGHT_GPIO_PIN GPIO_Pin_15 -#define BACKLIGHT_GPIO_PinSource GPIO_PinSource15 +#define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 15) #define BACKLIGHT_TIMER TIM2 -#define BACKLIGHT_GPIO_AF GPIO_AF_TIM2 +#define BACKLIGHT_GPIO_AF GPIO_AF1 #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) //used in BOOTLOADER @@ -473,9 +442,7 @@ // Audio #define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) -#define AUDIO_OUTPUT_GPIO GPIOA -#define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 -#define AUDIO_GPIO_PinSource GPIO_PinSource4 +#define AUDIO_OUTPUT_GPIO GPIO_PIN(GPIOA, 4) // PA.04 #define AUDIO_DMA_Stream DMA1_Stream5 #define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn #define AUDIO_TIM_IRQn TIM6_DAC_IRQn @@ -494,10 +461,8 @@ // Touch #define TOUCH_I2C_BUS I2C_Bus_1 #define TOUCH_I2C_CLK_RATE 400000 -#define TOUCH_INT_GPIO GPIOB -#define TOUCH_INT_GPIO_PIN LL_GPIO_PIN_9 // PB.09 -#define TOUCH_RST_GPIO GPIOB -#define TOUCH_RST_GPIO_PIN LL_GPIO_PIN_12 // PB.12 +#define TOUCH_INT_GPIO GPIO_PIN(GPIOB, 9) // PB.09 +#define TOUCH_RST_GPIO GPIO_PIN(GPIOB, 12) // PB.12 #define TOUCH_INT_EXTI_Line LL_EXTI_LINE_9 #define TOUCH_INT_EXTI_Port LL_SYSCFG_EXTI_PORTB #define TOUCH_INT_EXTI_SysCfgLine LL_SYSCFG_EXTI_LINE9 @@ -510,23 +475,18 @@ // Haptic: TIM1_CH1 #define HAPTIC_PWM -#define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA -#define HAPTIC_RCC_APB2Periph RCC_APB2ENR_TIM1EN -#define HAPTIC_GPIO GPIOA -#define HAPTIC_GPIO_PIN GPIO_Pin_8 +#define HAPTIC_GPIO GPIO_PIN(GPIOA, 8) // PA.08 #define HAPTIC_GPIO_TIMER TIM1 -#define HAPTIC_GPIO_AF GPIO_AF_TIM1 -#define HAPTIC_GPIO_PinSource GPIO_PinSource8 +#define HAPTIC_GPIO_AF GPIO_AF1 #define HAPTIC_TIMER_OUTPUT_ENABLE TIM_CCER_CC1E | TIM_CCER_CC1NE; #define HAPTIC_TIMER_MODE TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1PE #define HAPTIC_TIMER_COMPARE_VALUE HAPTIC_GPIO_TIMER->CCR1 // Flysky Hall Stick #define FLYSKY_HALL_SERIAL_USART UART4 -#define FLYSKY_HALL_SERIAL_GPIO GPIOA #define FLYSKY_HALL_DMA_Channel LL_DMA_CHANNEL_4 -#define FLYSKY_HALL_SERIAL_TX_GPIO_PIN LL_GPIO_PIN_0 // PA.00 -#define FLYSKY_HALL_SERIAL_RX_GPIO_PIN LL_GPIO_PIN_1 // PA.01 +#define FLYSKY_HALL_SERIAL_TX_GPIO GPIO_PIN(GPIOA, 0) // PA.00 +#define FLYSKY_HALL_SERIAL_RX_GPIO GPIO_PIN(GPIOA, 1) // PA.01 #define FLYSKY_HALL_SERIAL_GPIO_AF LL_GPIO_AF_8 #define FLYSKY_HALL_RCC_AHB1Periph RCC_AHB1Periph_DMA1 @@ -540,9 +500,8 @@ // LED Strip #define LED_STRIP_LENGTH 4 -#define LED_STRIP_GPIO GPIOH -#define LED_STRIP_GPIO_PIN_DATA LL_GPIO_PIN_12 // PH.12 / TIM5_CH3 -#define LED_STRIP_GPIO_PIN_AF LL_GPIO_AF_2 // TIM3/4/5 +#define LED_STRIP_GPIO GPIO_PIN(GPIOH, 12) // PH.12 / TIM5_CH3 +#define LED_STRIP_GPIO_AF LL_GPIO_AF_2 // TIM3/4/5 #define LED_STRIP_TIMER TIM5 #define LED_STRIP_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define LED_STRIP_TIMER_CHANNEL LL_TIM_CHANNEL_CH3 @@ -559,11 +518,9 @@ // Internal Module #if defined(RADIO_PL18) #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_DMA1) -#define INTMODULE_PWR_GPIO GPIOI -#define INTMODULE_PWR_GPIO_PIN GPIO_Pin_0 // PI.00 -#define INTMODULE_GPIO GPIOF -#define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_7 // PF.07 -#define INTMODULE_RX_GPIO_PIN LL_GPIO_PIN_6 // PF.06 +#define INTMODULE_PWR_GPIO GPIO_PIN(GPIOI, 0) // PI.00 +#define INTMODULE_TX_GPIO GPIO_PIN(GPIOF, 7) // PF.07 +#define INTMODULE_RX_GPIO GPIO_PIN(GPIOF, 6) // PF.06 #define INTMODULE_USART UART7 #define INTMODULE_GPIO_AF LL_GPIO_AF_8 #define INTMODULE_USART_IRQn UART7_IRQn @@ -590,17 +547,11 @@ // External Module #define EXTMODULE #define EXTMODULE_PULSES -#define EXTMODULE_PWR_GPIO GPIOD -#define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_11 // PD.11 -#define EXTMODULE_RCC_AHB1Periph \ - (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOC | \ - RCC_AHB1Periph_GPIOI | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_DMA2) -#define EXTMODULE_TX_GPIO GPIOC -#define EXTMODULE_TX_GPIO_PIN LL_GPIO_PIN_6 // PC.06 +#define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 11) // PD.11 +#define EXTMODULE_TX_GPIO GPIO_PIN(GPIOC, 6) // PC.06 +#define EXTMODULE_RX_GPIO GPIO_PIN(GPIOC, 7) // PC.07 #define EXTMODULE_TX_GPIO_AF LL_GPIO_AF_3 // TIM8_CH1 #define EXTMODULE_TX_GPIO_AF_USART GPIO_AF_USART6 -#define EXTMODULE_RX_GPIO GPIOC -#define EXTMODULE_RX_GPIO_PIN LL_GPIO_PIN_7 // PC.07 #define EXTMODULE_RX_GPIO_AF_USART GPIO_AF_USART6 #define EXTMODULE_TIMER TIM8 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH1 @@ -615,28 +566,23 @@ #define EXTMODULE_USART_GPIO_AF_LL LL_GPIO_AF_8 #define EXTMODULE_USART_TX_DMA DMA2 #define EXTMODULE_USART_TX_DMA_CHANNEL LL_DMA_CHANNEL_5 -#define EXTMODULE_USART_TX_DMA_STREAM DMA2_Stream7 -#define EXTMODULE_USART_TX_DMA_STREAM_LL LL_DMA_STREAM_7 +#define EXTMODULE_USART_TX_DMA_STREAM LL_DMA_STREAM_7 #define EXTMODULE_USART_RX_DMA_CHANNEL LL_DMA_CHANNEL_5 -#define EXTMODULE_USART_RX_DMA_STREAM DMA2_Stream2 -#define EXTMODULE_USART_RX_DMA_STREAM_LL LL_DMA_STREAM_2 +#define EXTMODULE_USART_RX_DMA_STREAM LL_DMA_STREAM_2 #define EXTMODULE_USART_IRQHandler USART6_IRQHandler #define EXTMODULE_USART_IRQn USART6_IRQn //TIMER #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 -#define EXTMODULE_TIMER_DMA_STREAM DMA2_Stream1 #define EXTMODULE_TIMER_DMA DMA2 -#define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_1 +#define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_1 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream1_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA2_Stream1_IRQHandler -#define EXTMODULE_TX_INVERT_GPIO GPIOE -#define EXTMODULE_TX_INVERT_GPIO_PIN GPIO_Pin_3 // PE.03 -#define EXTMODULE_RX_INVERT_GPIO GPIOI -#define EXTMODULE_RX_INVERT_GPIO_PIN GPIO_Pin_15 // PI.15 +#define EXTMODULE_TX_INVERT_GPIO GPIO_PIN(GPIOE, 3) // PE.03 +#define EXTMODULE_RX_INVERT_GPIO GPIO_PIN(GPIOI, 15) // PI.15 #define EXTMODULE_TX_NORMAL() EXTMODULE_TX_INVERT_GPIO->BSRRH = EXTMODULE_TX_INVERT_GPIO_PIN #define EXTMODULE_TX_INVERTED() EXTMODULE_TX_INVERT_GPIO->BSRRL = EXTMODULE_TX_INVERT_GPIO_PIN @@ -644,12 +590,11 @@ #define EXTMODULE_RX_INVERTED() EXTMODULE_RX_INVERT_GPIO->BSRRL = EXTMODULE_RX_INVERT_GPIO_PIN // Trainer Port -#define TRAINER_GPIO GPIOD -#define TRAINER_IN_GPIO_PIN LL_GPIO_PIN_12 // PD.12 +#define TRAINER_IN_GPIO GPIO_PIN(GPIOD, 12) // PD.12 #define TRAINER_IN_TIMER_Channel LL_TIM_CHANNEL_CH1 -#define TRAINER_OUT_GPIO_PIN LL_GPIO_PIN_13 // PD.13 +#define TRAINER_OUT_GPIO GPIO_PIN(GPIOD, 13) // PD.13 #define TRAINER_OUT_TIMER_Channel LL_TIM_CHANNEL_CH2 #define TRAINER_TIMER TIM4 @@ -696,6 +641,9 @@ #define MIXER_SCHEDULER_TIMER_IRQn TIM8_BRK_TIM12_IRQn #define MIXER_SCHEDULER_TIMER_IRQHandler TIM8_BRK_TIM12_IRQHandler +// SDRAM +#define SDRAM_BANK1 + #define LCD_W 480 #define LCD_H 320 diff --git a/radio/src/targets/pl18/haptic_driver.cpp b/radio/src/targets/pl18/haptic_driver.cpp index d8fc8f809..be233d91d 100644 --- a/radio/src/targets/pl18/haptic_driver.cpp +++ b/radio/src/targets/pl18/haptic_driver.cpp @@ -20,6 +20,10 @@ */ #include "board.h" +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + void hapticOff(void) { @@ -36,16 +40,9 @@ void hapticOn(uint32_t pwmPercent) void hapticInit(void) { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HAPTIC_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HAPTIC_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(HAPTIC_GPIO, HAPTIC_GPIO_PinSource, HAPTIC_GPIO_AF); + gpio_init_af(HAPTIC_GPIO, HAPTIC_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(HAPTIC_GPIO_TIMER); HAPTIC_GPIO_TIMER->ARR = 100; HAPTIC_GPIO_TIMER->PSC = (PERI2_FREQUENCY * TIMER_MULT_APB2) / 10000 - 1; HAPTIC_GPIO_TIMER->CCMR1 = HAPTIC_TIMER_MODE; // PWM @@ -59,5 +56,4 @@ void hapticInit(void) void hapticDone(void) { hapticOff(); - RCC_AHB1PeriphClockCmd(HAPTIC_RCC_AHB1Periph, DISABLE); } diff --git a/radio/src/targets/pl18/lcd_driver.cpp b/radio/src/targets/pl18/lcd_driver.cpp index cf1b097aa..cfc41b1e8 100644 --- a/radio/src/targets/pl18/lcd_driver.cpp +++ b/radio/src/targets/pl18/lcd_driver.cpp @@ -24,6 +24,8 @@ #include "opentx_types.h" #include "dma2d.h" #include "hal.h" +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "delays_driver.h" #include "debug.h" #include "lcd.h" @@ -36,6 +38,8 @@ static volatile uint16_t lcd_phys_h = LCD_PHYS_H; static LTDC_HandleTypeDef hltdc; static void* initialFrameBuffer = nullptr; +#define GPIO_AF_LTDC GPIO_AF14 + static volatile uint8_t _frame_addr_reloaded = 0; static void startLcdRefresh(lv_disp_drv_t *disp_drv, uint16_t *buffer, @@ -79,65 +83,64 @@ enum ENUM_IO_MODE IO_MODE_ANALOG }; -static void LCD_AF_GPIOConfig(void) { + +static void LCD_AF_GPIOConfig(void) +{ + /* GPIOs Configuration */ /* - ----------------------------------------------------------------------------- - LCD_CLK <-> PG.07 | LCD_HSYNC <-> PI.12 | LCD_R3 <-> PJ.02 | LCD_G5 <-> PK.00 - | LCD VSYNC <-> PI.13 | LCD_R4 <-> PJ.03 | LCD_G6 <-> PK.01 - | | LCD_R5 <-> PJ.04 | LCD_G7 <-> PK.02 - | | LCD_R6 <-> PJ.05 | LCD_B4 <-> PK.03 - | | LCD_R7 <-> PJ.06 | LCD_B5 <-> PK.04 - | | LCD_G2 <-> PJ.09 | LCD_B6 <-> PK.05 - | | LCD_G3 <-> PJ.10 | LCD_B7 <-> PK.06 - | | LCD_G4 <-> PJ.11 | LCD_DE <-> PK.07 - | | LCD_B3 <-> PJ.15 | + +---------------------+---------------------+------------------+------------------+ + + LCD pins assignment + + +---------------------+---------------------+------------------+------------------+ + | LCD_CLK <-> PG.07 | LCD_HSYNC <-> PI.12 | LCD_R3 <-> PJ.02 | LCD_G5 <-> PK.00 | + | LCD VSYNC <-> PI.13 | LCD_R4 <-> PJ.03 | LCD_G6 <-> PK.01 | | + | | LCD_R5 <-> PJ.04 | LCD_G7 <-> PK.02 | | + | | LCD_R6 <-> PJ.05 | LCD_B4 <-> PK.03 | | + | | LCD_R7 <-> PJ.06 | LCD_B5 <-> PK.04 | | + | | LCD_G2 <-> PJ.09 | LCD_B6 <-> PK.05 | | + | | LCD_G3 <-> PJ.10 | LCD_B7 <-> PK.06 | | + | | LCD_G4 <-> PJ.11 | LCD_DE <-> PK.07 | | + | | LCD_B3 <-> PJ.15 | | | + +---------------------+---------------------+------------------+------------------+ */ - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); - // GPIOG configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_7; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_ALTERNATE; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - GPIO_InitStructure.Alternate = LL_GPIO_AF_14; // AF LTDC - LL_GPIO_Init(GPIOG, &GPIO_InitStructure); - + gpio_init_af(GPIO_PIN(GPIOG, 7), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + // GPIOI configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_12 | LL_GPIO_PIN_13; - LL_GPIO_Init(GPIOI, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOI, 12), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOI, 13), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOJ configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | LL_GPIO_PIN_15; - LL_GPIO_Init(GPIOJ, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOJ, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 9), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 10), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 11), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOJ, 15), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); // GPIOK configuration - GPIO_InitStructure.Pin = LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7; - LL_GPIO_Init(GPIOK, &GPIO_InitStructure); + gpio_init_af(GPIO_PIN(GPIOK, 0), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 1), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 2), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 3), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 4), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 5), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 6), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); + gpio_init_af(GPIO_PIN(GPIOK, 7), GPIO_AF_LTDC, GPIO_PIN_SPEED_LOW); } -static void lcdSpiConfig(void) { - LL_GPIO_InitTypeDef GPIO_InitStructure; - LL_GPIO_StructInit(&GPIO_InitStructure); +static void lcdSpiConfig(void) +{ + gpio_init(LCD_SPI_SCK_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_SPI_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_SPI_CS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_NRST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); - GPIO_InitStructure.Pin = LCD_SPI_SCK_GPIO_PIN | LCD_SPI_MOSI_GPIO_PIN; - GPIO_InitStructure.Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStructure.Mode = LL_GPIO_MODE_OUTPUT; - GPIO_InitStructure.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStructure.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_SPI_CS_GPIO_PIN; - GPIO_InitStructure.Pull = LL_GPIO_PULL_UP; - LL_GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.Pin = LCD_NRST_GPIO_PIN; - LL_GPIO_Init(LCD_NRST_GPIO, &GPIO_InitStructure); - - /* Set the chip select pin always low */ - LCD_CS_LOW(); + /* Set the chip select pin aways low */ + CLR_LCD_CS(); } void lcdDelay() { @@ -145,13 +148,13 @@ void lcdDelay() { } static void lcdReset() { - LCD_NRST_HIGH(); + SET_LCD_NRST(); delay_ms(1); - LCD_NRST_LOW(); // RESET(); + CLR_LCD_NRST(); // RESET(); delay_ms(100); - LCD_NRST_HIGH(); + SET_LCD_NRST(); delay_ms(100); } @@ -159,106 +162,106 @@ unsigned char LCD_ReadByteOnFallingEdge(void) { unsigned int i; unsigned char ReceiveData = 0; - LCD_MOSI_HIGH(); - LCD_MOSI_AS_INPUT(); + SET_LCD_DATA(); + SET_LCD_DATA_INPUT(); for (i = 0; i < 8; i++) { lcdDelay(); - LCD_SCK_HIGH(); + SET_LCD_CLK(); lcdDelay(); lcdDelay(); ReceiveData <<= 1; - LCD_SCK_LOW(); + CLR_LCD_CLK(); lcdDelay(); lcdDelay(); - if (LCD_READ_DATA_PIN()) { + if (READ_LCD_DATA_PIN()) { ReceiveData |= 0x01; } } - LCD_MOSI_AS_OUTPUT(); + SET_LCD_DATA_OUTPUT(); return (ReceiveData); } static void lcdWriteByte(uint8_t data_enable, uint8_t byte) { - LCD_SCK_LOW(); + CLR_LCD_CLK(); if (data_enable) { - LCD_MOSI_HIGH(); + SET_LCD_DATA(); } else { - LCD_MOSI_LOW(); + CLR_LCD_DATA(); } lcdDelay(); - LCD_SCK_HIGH(); + SET_LCD_CLK(); for (int i = 0; i < 8; i++) { lcdDelay(); - LCD_SCK_LOW(); + CLR_LCD_CLK(); if (byte & 0x80) { - LCD_MOSI_HIGH(); + SET_LCD_DATA(); } else { - LCD_MOSI_LOW(); + CLR_LCD_DATA(); } lcdDelay(); - LCD_SCK_HIGH(); + SET_LCD_CLK(); byte <<= 1; } lcdDelay(); - LCD_SCK_LOW(); + CLR_LCD_CLK(); } unsigned char LCD_ReadByte(void) { unsigned int i; unsigned char ReceiveData = 0; - LCD_MOSI_HIGH(); - LCD_MOSI_AS_INPUT(); + SET_LCD_DATA(); + SET_LCD_DATA_INPUT(); for (i = 0; i < 8; i++) { - LCD_SCK_LOW(); + CLR_LCD_CLK(); lcdDelay(); ReceiveData <<= 1; - LCD_SCK_HIGH(); + SET_LCD_CLK(); lcdDelay(); - if (LCD_READ_DATA_PIN()) { + if (READ_LCD_DATA_PIN()) { ReceiveData |= 0x01; } } - LCD_SCK_LOW(); - LCD_MOSI_AS_OUTPUT(); + CLR_LCD_CLK(); + SET_LCD_DATA_OUTPUT(); return (ReceiveData); } unsigned char LCD_ReadRegister(unsigned char Register) { unsigned char ReadData = 0; - LCD_CS_LOW(); + CLR_LCD_CS(); lcdWriteByte(0, Register); lcdDelay(); lcdDelay(); ReadData = LCD_ReadByte(); - LCD_CS_HIGH(); + SET_LCD_CS(); lcdDelay(); return (ReadData); } void lcdWriteCommand(uint8_t command) { - LCD_CS_LOW(); + CLR_LCD_CS(); lcdWriteByte(0, command); - LCD_CS_HIGH(); + SET_LCD_CS(); lcdDelay(); } void lcdWriteData(uint8_t data) { - LCD_CS_LOW(); + CLR_LCD_CS(); lcdWriteByte(1, data); - LCD_CS_HIGH(); + SET_LCD_CS(); lcdDelay(); } @@ -1274,11 +1277,11 @@ unsigned int LCD_ST7796S_ReadID(void) { lcdWriteCommand( 0XD3 ); - LCD_MOSI_AS_INPUT(); - LCD_SCK_LOW(); + SET_LCD_DATA_INPUT(); + CLR_LCD_CLK(); lcdDelay(); lcdDelay(); - LCD_SCK_HIGH(); + SET_LCD_CLK(); lcdDelay(); lcdDelay(); diff --git a/radio/src/targets/pl18/lcd_driver.h b/radio/src/targets/pl18/lcd_driver.h index a8211d274..839f5e08f 100644 --- a/radio/src/targets/pl18/lcd_driver.h +++ b/radio/src/targets/pl18/lcd_driver.h @@ -44,25 +44,20 @@ extern lcdSpiInitFucPtr lcdInitFunction; extern lcdSpiInitFucPtr lcdOffFunction; extern lcdSpiInitFucPtr lcdOnFunction; -#define SET_IO_INPUT( PORT, PIN ) LL_GPIO_SetPinMode( PORT, PIN, LL_GPIO_MODE_INPUT ) -#define SET_IO_OUTPUT( PORT, PIN ) LL_GPIO_SetPinMode( PORT, PIN, LL_GPIO_MODE_OUTPUT ) +#define SET_LCD_NRST() gpio_write(LCD_NRST_GPIO, 1) +#define CLR_LCD_NRST() gpio_write(LCD_NRST_GPIO, 0) -#define LCD_NRST_HIGH() LL_GPIO_SetOutputPin(LCD_NRST_GPIO, LCD_NRST_GPIO_PIN) -#define LCD_NRST_LOW() LL_GPIO_ResetOutputPin(LCD_NRST_GPIO, LCD_NRST_GPIO_PIN) +#define SET_LCD_CS() gpio_write(LCD_SPI_CS_GPIO, 1) +#define CLR_LCD_CS() gpio_write(LCD_SPI_CS_GPIO, 0) -#define LCD_CS_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_CS_GPIO_PIN) -#define LCD_CS_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_CS_GPIO_PIN) +#define SET_LCD_CLK() gpio_write(LCD_SPI_SCK_GPIO, 1) +#define CLR_LCD_CLK() gpio_write(LCD_SPI_SCK_GPIO, 0) -#define LCD_SCK_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_SCK_GPIO_PIN) -#define LCD_SCK_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_SCK_GPIO_PIN) - -#define LCD_MOSI_HIGH() LL_GPIO_SetOutputPin(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) -#define LCD_MOSI_LOW() LL_GPIO_ResetOutputPin(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) - -#define LCD_MOSI_AS_INPUT() SET_IO_INPUT( LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN ) -#define LCD_MOSI_AS_OUTPUT() SET_IO_OUTPUT( LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN ) - -#define LCD_READ_DATA_PIN() LL_GPIO_IsInputPinSet(LCD_SPI_GPIO, LCD_SPI_MOSI_GPIO_PIN) +#define SET_LCD_DATA() gpio_write(LCD_SPI_MOSI_GPIO, 1) +#define CLR_LCD_DATA() gpio_write(LCD_SPI_MOSI_GPIO, 0) +#define SET_LCD_DATA_INPUT() gpio_init(LCD_SPI_MOSI_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW) +#define SET_LCD_DATA_OUTPUT() gpio_init(LCD_SPI_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW) +#define READ_LCD_DATA_PIN() gpio_read(LCD_SPI_MOSI_GPIO) #if 1 diff --git a/radio/src/targets/pl18/sdram_driver.c b/radio/src/targets/pl18/sdram_driver.c deleted file mode 100644 index 2cc88ae84..000000000 --- a/radio/src/targets/pl18/sdram_driver.c +++ /dev/null @@ -1,257 +0,0 @@ -/* - * Copyright (C) OpenTX - * - * Based on code named - * th9x - http://code.google.com/p/th9x - * er9x - http://code.google.com/p/er9x - * gruvin9x - http://code.google.com/p/gruvin9x - * - * License GPLv2: http://www.gnu.org/licenses/gpl-2.0.html - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "board.h" -#include "stm32f4xx_fmc.h" - -#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001) -#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002) -#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004) -#define SDRAM_MODEREG_BURST_FULL_PAGE ((uint16_t)0x0007) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define SDRAM_MODEREG_CAS_LATENCY_1 ((uint16_t)0x0010) -#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020) -#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -void SDRAM_GPIOConfig(void) -{ - /* - ------------------------------------------------------------------------------------------------------------------------------------------------ - PC3 <-> FMC_SDCKE0 | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 | PH3 <-> FMC_SDNE0 | PI0 <-> FMC_D24 - | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 | PH5 <-> FMC_SDNWE | PI1 <-> FMC_D25 - | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG4 <-> FMC_BA0 | PH8 <-> FMC_D16 | PI2 <-> FMC_D26 - | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG5 <-> FMC_BA1 | PH9 <-> FMC_D17 | PI3 <-> FMC_D27 - | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 | PG8 <-> FMC_SDCLK | PH10 <-> FMC_D18 | PI4 <-> FMC_NBL2 - | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 | PG15 <-> FMC_NCAS | PH11 <-> FMC_D19 | PI5 <-> FMC_NBL3 - | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS | | PH12 <-> FMC_D20 | PI6 <-> FMC_D28 - | | PE12 <-> FMC_D9 | PF12 <-> FMC_A6 | | PH13 <-> FMC_D21 | PI7 <-> FMC_D29 - | | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 | | PH14 <-> FMC_D22 | PI9 <-> FMC_D30 - | | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 | | PH15 <-> FMC_D23 | PI10 <-> FMC_D31 - | | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 | | | - */ - - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - - /* GPIOC configuration */ - GPIO_PinAFConfig(GPIOC, GPIO_PinSource3 , GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 ; - GPIO_Init(GPIOC, &GPIO_InitStructure); - - /* GPIOD configuration */ - GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOD, &GPIO_InitStructure); - - /* GPIOE configuration */ - GPIO_PinAFConfig(GPIOE, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource7, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource8, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource9, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource10, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource11, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource12, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource13, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOE, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOE, &GPIO_InitStructure); - - /* GPIOF configuration */ - GPIO_PinAFConfig(GPIOF, GPIO_PinSource0, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource1, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource2, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource3, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource4, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource5, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource11, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource12, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource13, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource14, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOF, GPIO_PinSource15, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15; - GPIO_Init(GPIOF, &GPIO_InitStructure); - - /* GPIOG configuration */ - GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15; - GPIO_Init(GPIOG, &GPIO_InitStructure); - - /* GPIOH configuration */ - GPIO_PinAFConfig(GPIOH, GPIO_PinSource3, GPIO_AF_FMC); - GPIO_PinAFConfig(GPIOH, GPIO_PinSource5, GPIO_AF_FMC); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_5; - GPIO_Init(GPIOH, &GPIO_InitStructure); -} - -void SDRAM_InitSequence(void) -{ - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - uint32_t tmpr = 0; - - /* Step 3 --------------------------------------------------------------------*/ - /* Configure a clock configuration enable command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 4 --------------------------------------------------------------------*/ - /* Insert 100 ms delay */ - delay_ms(100); - - /* Step 5 --------------------------------------------------------------------*/ - /* Configure a PALL (precharge all) command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 6 --------------------------------------------------------------------*/ - /* Configure a Auto-Refresh command */ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the first command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the second command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 7 --------------------------------------------------------------------*/ - /* Program the external memory mode register */ - tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | - SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | - SDRAM_MODEREG_CAS_LATENCY_3 | - SDRAM_MODEREG_OPERATING_MODE_STANDARD | - SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; - - /* Configure a load Mode register command*/ - FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode; - FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank1; - FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1; - FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr; - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } - /* Send the command */ - FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - /* Step 8 --------------------------------------------------------------------*/ - /* Set the refresh rate counter */ - /* (15.62 us x Freq) - 20 */ - /* Set the device refresh counter */ - FMC_SetRefreshCount(683);//904 - /* Wait until the SDRAM controller is ready */ - while(FMC_GetFlagStatus(FMC_Bank1_SDRAM, FMC_FLAG_Busy) != RESET) { - } -} - - -void SDRAM_Init(void) -{ - //delay funcion needed - delaysInit(); - // Clocks must be enabled here, because the sdramInit is called before main - RCC_AHB1PeriphClockCmd(SDRAM_RCC_AHB1Periph, ENABLE); - RCC_AHB3PeriphClockCmd(SDRAM_RCC_AHB3Periph, ENABLE); - - /* GPIO configuration for FMC SDRAM bank */ - SDRAM_GPIOConfig(); - - /* FMC Configuration ---------------------------------------------------------*/ - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM Bank configuration */ - /* Timing configuration for 90 Mhz of SD clock frequency (168Mhz/2) */ - /* TMRD: 2 Clock cycles */ - FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2; - /* TXSR: min=70ns (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7; - /* TRAS: min=42ns (4x11.11ns) max=120k (ns) */ - FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4; - /* TRC: min=70 (7x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7; - /* TWR: min=1+ 7ns (1+1x11.11ns) */ - FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2; - /* TRP: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2; - /* TRCD: 20ns => 2x11.11ns */ - FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2; - - /* FMC SDRAM control configuration */ - FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank1_SDRAM; - /* Row addressing: [7:0] */ - FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - /* Column addressing: [11:0] */ - FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b; - FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; - FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3; - FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable; - FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2; - FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_Enable; - FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1; - FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure; - - /* FMC SDRAM bank initialization */ - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - /* FMC SDRAM device initialization sequence */ - SDRAM_InitSequence(); -} diff --git a/radio/src/targets/pl18/touch_driver.cpp b/radio/src/targets/pl18/touch_driver.cpp index c672aa925..983f4c24c 100644 --- a/radio/src/targets/pl18/touch_driver.cpp +++ b/radio/src/targets/pl18/touch_driver.cpp @@ -19,6 +19,8 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "stm32_hal_ll.h" #include "stm32_hal.h" #include "stm32_i2c_driver.h" @@ -108,49 +110,11 @@ static void _touch_exti_isr(void) touchEventOccured = true; } -static void _touch_exti_stop(void) -{ - stm32_exti_disable(TOUCH_INT_EXTI_Line); -} - -static void _touch_exti_config(void) -{ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - LL_SYSCFG_SetEXTISource(TOUCH_INT_EXTI_Port, TOUCH_INT_EXTI_SysCfgLine); - - stm32_exti_enable(TOUCH_INT_EXTI_Line, LL_EXTI_TRIGGER_FALLING, _touch_exti_isr); -} - -static void _touch_gpio_config(void) -{ - LL_GPIO_InitTypeDef gpioInit; - LL_GPIO_StructInit(&gpioInit); - - stm32_gpio_enable_clock(TOUCH_RST_GPIO); - stm32_gpio_enable_clock(TOUCH_INT_GPIO); - - gpioInit.Mode = LL_GPIO_MODE_OUTPUT; - gpioInit.Speed = LL_GPIO_SPEED_FREQ_LOW; - gpioInit.OutputType = LL_GPIO_OUTPUT_PUSHPULL; - gpioInit.Pull = LL_GPIO_PULL_NO; - - gpioInit.Pin = TOUCH_RST_GPIO_PIN; - LL_GPIO_Init(TOUCH_RST_GPIO, &gpioInit); - LL_GPIO_SetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); - - gpioInit.Pin = TOUCH_INT_GPIO_PIN; - gpioInit.Mode = LL_GPIO_MODE_INPUT; - gpioInit.Pull = LL_GPIO_PULL_UP; - gpioInit.OutputType = LL_GPIO_OUTPUT_OPENDRAIN; - LL_GPIO_Init(TOUCH_INT_GPIO, &gpioInit); - LL_GPIO_SetOutputPin(TOUCH_INT_GPIO, TOUCH_INT_GPIO_PIN); -} - static void _touch_reset() { - LL_GPIO_ResetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); + gpio_clear(TOUCH_RST_GPIO); delay_ms(10); - LL_GPIO_SetOutputPin(TOUCH_RST_GPIO, TOUCH_RST_GPIO_PIN); + gpio_set(TOUCH_RST_GPIO); delay_ms(300); } @@ -356,16 +320,16 @@ void _detect_touch_controller() void touchPanelDeInit() { - _touch_exti_stop(); + gpio_int_disable(TOUCH_INT_GPIO); } bool touchPanelInit() { - _touch_gpio_config(); + gpio_init(TOUCH_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); _i2c_init(); _touch_reset(); _detect_touch_controller(); - _touch_exti_config(); + gpio_init_int(TOUCH_INT_GPIO, GPIO_IN_PU, GPIO_FALLING, _touch_exti_isr); tcd->printDebugInfo(); diff --git a/radio/src/targets/simu/simpgmspace.cpp b/radio/src/targets/simu/simpgmspace.cpp index 50635fc90..6c081e48d 100644 --- a/radio/src/targets/simu/simpgmspace.cpp +++ b/radio/src/targets/simu/simpgmspace.cpp @@ -114,10 +114,9 @@ uint16_t getTmr2MHz() return simuTimerMicros() * 2; } -// return 2ms resolution to match CoOS settings -uint64_t CoGetOSTime(void) +uint32_t timersGetMsTick(void) { - return simuTimerMicros() / 2000; + return simuTimerMicros() / 1000; } void simuInit() diff --git a/radio/src/targets/taranis/CMakeLists.txt b/radio/src/targets/taranis/CMakeLists.txt index 139b0fc9c..8ddf80739 100644 --- a/radio/src/targets/taranis/CMakeLists.txt +++ b/radio/src/targets/taranis/CMakeLists.txt @@ -601,7 +601,7 @@ if(PCB STREQUAL XLITE OR PCB STREQUAL XLITES OR PCBREV STREQUAL COMMANDO8) targets/common/arm/stm32/sticks_pwm_driver.cpp) endif() -if(PCBREV STREQUAL MT12) +if(PCBREV STREQUAL MT12 OR PCBREV STREQUAL T14) set(FIRMWARE_SRC ${FIRMWARE_SRC} targets/common/arm/stm32/stm32_ws2812.cpp diff --git a/radio/src/targets/taranis/backlight_driver.cpp b/radio/src/targets/taranis/backlight_driver.cpp index a5d8e90cd..4785e9a61 100644 --- a/radio/src/targets/taranis/backlight_driver.cpp +++ b/radio/src/targets/taranis/backlight_driver.cpp @@ -19,9 +19,13 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "board.h" -#if !defined(BACKLIGHT_GPIO) +#if !defined(BACKLIGHT_GPIO) && (!defined(BACKLIGHT_GPIO_1) || !defined(BACKLIGHT_GPIO_2)) // no backlight void backlightInit() {} void backlightEnable(uint8_t level) {} @@ -31,15 +35,9 @@ #elif defined(PCBX9E) void backlightInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1|BACKLIGHT_GPIO_PIN_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); + gpio_init_af(BACKLIGHT_GPIO_1, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + gpio_init_af(BACKLIGHT_GPIO_2, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM @@ -74,15 +72,9 @@ uint8_t isBacklightEnabled() #elif defined(PCBX9DP) void backlightInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN_1 | BACKLIGHT_GPIO_PIN_2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_1, BACKLIGHT_GPIO_AF_1); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource_2, BACKLIGHT_GPIO_AF_1); + gpio_init_af(BACKLIGHT_GPIO_1, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + gpio_init_af(BACKLIGHT_GPIO_2, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2; // PWM @@ -118,14 +110,9 @@ uint8_t isBacklightEnabled() #elif defined(PCBX7) || defined(PCBXLITE) || defined(PCBX9LITE) void backlightInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + #if defined(BACKLIGHT_BDTR) // TODO perhaps it can be always done BACKLIGHT_TIMER->BDTR = BACKLIGHT_BDTR; // Enable outputs #endif @@ -164,14 +151,9 @@ uint8_t isBacklightEnabled() #else void backlightInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = BACKLIGHT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(BACKLIGHT_GPIO, &GPIO_InitStructure); - GPIO_PinAFConfig(BACKLIGHT_GPIO, BACKLIGHT_GPIO_PinSource, BACKLIGHT_GPIO_AF); + gpio_init_af(BACKLIGHT_GPIO, BACKLIGHT_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(BACKLIGHT_TIMER); + BACKLIGHT_TIMER->ARR = 100; BACKLIGHT_TIMER->PSC = BACKLIGHT_TIMER_FREQ / 50000 - 1; // 20us * 100 = 2ms => 500Hz BACKLIGHT_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2; // PWM diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp index 8f0b680e5..d264e8dbd 100644 --- a/radio/src/targets/taranis/board.cpp +++ b/radio/src/targets/taranis/board.cpp @@ -19,6 +19,8 @@ * GNU General Public License for more details. */ +#include "stm32_hal_ll.h" +#include "stm32_gpio.h" #include "stm32_ws2812.h" #include "hal/adc_driver.h" @@ -27,6 +29,7 @@ #include "hal/module_port.h" #include "hal/abnormal_reboot.h" #include "hal/usb_driver.h" +#include "hal/gpio.h" #include "board.h" #include "boards/generic_stm32/module_ports.h" @@ -66,35 +69,8 @@ HardwareOptions hardwareOptions; void boardInit() { - RCC_AHB1PeriphClockCmd(PWR_RCC_AHB1Periph | - PCBREV_RCC_AHB1Periph | - LCD_RCC_AHB1Periph | - AUDIO_RCC_AHB1Periph | - BACKLIGHT_RCC_AHB1Periph | - HAPTIC_RCC_AHB1Periph | - INTMODULE_RCC_AHB1Periph | - EXTMODULE_RCC_AHB1Periph | - TELEMETRY_RCC_AHB1Periph | - SPORT_UPDATE_RCC_AHB1Periph | - BT_RCC_AHB1Periph | - USB_CHARGER_RCC_AHB1Periph, - ENABLE); - - RCC_APB1PeriphClockCmd(ROTARY_ENCODER_RCC_APB1Periph | - LCD_RCC_APB1Periph | - AUDIO_RCC_APB1Periph | - BACKLIGHT_RCC_APB1Periph | - HAPTIC_RCC_APB1Periph | - TELEMETRY_RCC_APB1Periph | - BT_RCC_APB1Periph, - ENABLE); - - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG | - BACKLIGHT_RCC_APB2Periph | - HAPTIC_RCC_APB2Periph | - BT_RCC_APB2Periph | - TELEMETRY_RCC_APB2Periph, - ENABLE); + LL_APB1_GRP1_EnableClock(AUDIO_RCC_APB1Periph); + LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG); #if defined(BLUETOOTH) && !defined(PCBX9E) bluetoothInit(BLUETOOTH_DEFAULT_BAUDRATE, true); @@ -229,7 +205,9 @@ void boardInit() #endif #if defined(DEBUG) - DBGMCU_APB1PeriphConfig(DBGMCU_IWDG_STOP|DBGMCU_TIM1_STOP|DBGMCU_TIM2_STOP|DBGMCU_TIM3_STOP|DBGMCU_TIM6_STOP|DBGMCU_TIM8_STOP|DBGMCU_TIM10_STOP|DBGMCU_TIM13_STOP|DBGMCU_TIM14_STOP, ENABLE); + // Freeze timers & watchdog when core is halted + DBGMCU->APB1FZ = 0x00E009FF; + DBGMCU->APB2FZ = 0x00070003; #endif #if defined(PWR_BUTTON_PRESS) @@ -322,61 +300,61 @@ void boardOff() #if defined(AUDIO_SPEAKER_ENABLE_GPIO) void initSpeakerEnable() { - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_InitStructure.GPIO_Pin = AUDIO_SPEAKER_ENABLE_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(AUDIO_SPEAKER_ENABLE_GPIO, &GPIO_InitStructure); + gpio_init(AUDIO_SPEAKER_ENABLE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); } void enableSpeaker() { - GPIO_SetBits(AUDIO_SPEAKER_ENABLE_GPIO, AUDIO_SPEAKER_ENABLE_GPIO_PIN); + gpio_set(AUDIO_SPEAKER_ENABLE_GPIO); } void disableSpeaker() { - GPIO_ResetBits(AUDIO_SPEAKER_ENABLE_GPIO, AUDIO_SPEAKER_ENABLE_GPIO_PIN); + gpio_clear(AUDIO_SPEAKER_ENABLE_GPIO); } #endif #if defined(HEADPHONE_TRAINER_SWITCH_GPIO) void initHeadphoneTrainerSwitch() { - GPIO_InitTypeDef GPIO_InitStructure; - - GPIO_InitStructure.GPIO_Pin = HEADPHONE_TRAINER_SWITCH_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(HEADPHONE_TRAINER_SWITCH_GPIO, &GPIO_InitStructure); + gpio_init(HEADPHONE_TRAINER_SWITCH_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); } void enableHeadphone() { - GPIO_ResetBits(HEADPHONE_TRAINER_SWITCH_GPIO, HEADPHONE_TRAINER_SWITCH_GPIO_PIN); + gpio_clear(HEADPHONE_TRAINER_SWITCH_GPIO); } void enableTrainer() { - GPIO_SetBits(HEADPHONE_TRAINER_SWITCH_GPIO, HEADPHONE_TRAINER_SWITCH_GPIO_PIN); + gpio_set(HEADPHONE_TRAINER_SWITCH_GPIO); } #endif #if defined(JACK_DETECT_GPIO) void initJackDetect(void) { - GPIO_InitTypeDef GPIO_InitStructure; + gpio_init(JACK_DETECT_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); +} - GPIO_InitStructure.GPIO_Pin = JACK_DETECT_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(JACK_DETECT_GPIO, &GPIO_InitStructure); +bool isJackPlugged() +{ + // debounce + static bool debounced_state = 0; + static bool last_state = 0; + + if (gpio_read(JACK_DETECT_GPIO)) { + if (!last_state) { + debounced_state = false; + } + last_state = false; + } + else { + if (last_state) { + debounced_state = true; + } + last_state = true; + } + return debounced_state; } #endif diff --git a/radio/src/targets/taranis/board.h b/radio/src/targets/taranis/board.h index 4091ea04b..6a6cd88b8 100644 --- a/radio/src/targets/taranis/board.h +++ b/radio/src/targets/taranis/board.h @@ -68,8 +68,8 @@ uint32_t isFirmwareStart(const uint8_t * buffer); uint32_t isBootloaderStart(const uint8_t * buffer); // Pulses driver -#define INTERNAL_MODULE_ON() GPIO_SetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) -#define INTERNAL_MODULE_OFF() GPIO_ResetBits(INTMODULE_PWR_GPIO, INTMODULE_PWR_GPIO_PIN) +#define INTERNAL_MODULE_ON() gpio_set(INTMODULE_PWR_GPIO) +#define INTERNAL_MODULE_OFF() gpio_clear(INTMODULE_PWR_GPIO) #if (defined(INTERNAL_MODULE_PXX1) || defined(INTERNAL_MODULE_PXX2)) && (!defined(PCBX9LITE) || defined(PCBX9LITES)) #define HARDWARE_INTERNAL_RAS @@ -83,7 +83,7 @@ uint32_t isBootloaderStart(const uint8_t * buffer); #if defined(TRAINER_DETECT_GPIO) // Trainer detect is a switch on the jack - #define TRAINER_CONNECTED() (GPIO_ReadInputDataBit(TRAINER_DETECT_GPIO, TRAINER_DETECT_GPIO_PIN) == TRAINER_DETECT_GPIO_PIN_VALUE) + #define TRAINER_CONNECTED() (gpio_read(TRAINER_DETECT_GPIO) == TRAINER_DETECT_GPIO_PIN_VALUE) #elif defined(PCBXLITES) // Trainer is on the same connector than Headphones enum JackState diff --git a/radio/src/targets/taranis/dwt.h b/radio/src/targets/taranis/dwt.h index c906c04cf..0622e5008 100644 --- a/radio/src/targets/taranis/dwt.h +++ b/radio/src/targets/taranis/dwt.h @@ -1,3 +1,4 @@ +#if 0 /* * Copyright (C) EdgeTX * @@ -160,4 +161,5 @@ typedef struct #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#endif diff --git a/radio/src/targets/taranis/hal.h b/radio/src/targets/taranis/hal.h index ed6417ebe..172404602 100644 --- a/radio/src/targets/taranis/hal.h +++ b/radio/src/targets/taranis/hal.h @@ -216,8 +216,8 @@ #if defined(PCBX9E) #define ROTARY_ENCODER_NAVIGATION #define ROTARY_ENCODER_GPIO GPIOD - #define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_12 // PD.12 - #define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_13 // PD.13 + #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_12 // PD.12 + #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_13 // PD.13 #define ROTARY_ENCODER_POSITION() (ROTARY_ENCODER_GPIO->IDR >> 12) & 0x03 #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_12 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_13 @@ -232,8 +232,8 @@ #elif defined(RADIO_X9DP2019) #define ROTARY_ENCODER_NAVIGATION #define ROTARY_ENCODER_GPIO GPIOE - #define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_10 // PE.10 - #define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_11 // PE.11 + #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_10 // PE.10 + #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_11 // PE.11 #define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 9) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 11) & 0x01)) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_10 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_11 @@ -248,8 +248,8 @@ #elif defined(RADIO_X7) || defined(RADIO_X7ACCESS) || defined(RADIO_TPRO) || defined(RADIO_TPROV2) || defined(RADIO_FAMILY_T20) #define ROTARY_ENCODER_NAVIGATION #define ROTARY_ENCODER_GPIO GPIOE - #define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_9 // PE.09 - #define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_11 // PE.11 + #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_9 // PE.09 + #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_11 // PE.11 #define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 10) & 0x02) + ((ROTARY_ENCODER_GPIO->IDR >> 9) & 0x01)) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_9 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_11 @@ -269,8 +269,8 @@ #elif defined(PCBX9LITE) #define ROTARY_ENCODER_NAVIGATION #define ROTARY_ENCODER_GPIO GPIOE - #define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_10 // PE.10 - #define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_12 // PE.12 + #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_10 // PE.10 + #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_12 // PE.12 #define ROTARY_ENCODER_POSITION() (((ROTARY_ENCODER_GPIO->IDR >> 12) & 0x01) + ((ROTARY_ENCODER_GPIO->IDR >> 9) & 0x02)) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_10 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_12 @@ -285,8 +285,8 @@ #elif defined(RADIO_TX12) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_ZORRO) || defined(RADIO_MT12) || defined(RADIO_POCKET) || defined(RADIO_T14) #define ROTARY_ENCODER_NAVIGATION #define ROTARY_ENCODER_GPIO GPIOE - #define ROTARY_ENCODER_GPIO_PIN_A GPIO_Pin_9 // PE.09 - #define ROTARY_ENCODER_GPIO_PIN_B GPIO_Pin_10 // PE.10 + #define ROTARY_ENCODER_GPIO_PIN_A LL_GPIO_PIN_9 // PE.9 + #define ROTARY_ENCODER_GPIO_PIN_B LL_GPIO_PIN_10 // PE.10 #define ROTARY_ENCODER_POSITION() ((ROTARY_ENCODER_GPIO->IDR >> 9) & 0x03) #define ROTARY_ENCODER_EXTI_LINE1 LL_EXTI_LINE_9 #define ROTARY_ENCODER_EXTI_LINE2 LL_EXTI_LINE_10 @@ -312,12 +312,9 @@ #endif #if defined(ROTARY_ENCODER_NAVIGATION) - #define ROTARY_ENCODER_RCC_APB1Periph RCC_APB1Periph_TIM5 #define ROTARY_ENCODER_TIMER TIM5 #define ROTARY_ENCODER_TIMER_IRQn TIM5_IRQn #define ROTARY_ENCODER_TIMER_IRQHandler TIM5_IRQHandler -#else - #define ROTARY_ENCODER_RCC_APB1Periph 0 #endif // Trims @@ -1446,7 +1443,7 @@ #define PWM_STICKS #define PWM_TIMER TIM5 #define PWM_GPIO GPIOA - #define PWM_GPIO_AF LL_GPIO_AF_2 + #define PWM_GPIO_AF GPIO_AF2 #define PWM_IRQHandler TIM5_IRQHandler #define PWM_IRQn TIM5_IRQn #define PWM_GPIOA_PINS (ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV | ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH) @@ -1499,7 +1496,7 @@ #define PWM_IRQHandler TIM5_IRQHandler #define PWM_TIMER TIM5 #define PWM_GPIO GPIOA - #define PWM_GPIO_AF GPIO_AF_TIM5 + #define PWM_GPIO_AF GPIO_AF2 #define PWM_IRQn TIM5_IRQn #define PWM_GPIOA_PINS (ADC_GPIO_PIN_STICK_RV | ADC_GPIO_PIN_STICK_RH | ADC_GPIO_PIN_STICK_LH | ADC_GPIO_PIN_STICK_LV) #define STICK_PWM_CHANNEL_LH 1 @@ -1733,172 +1730,123 @@ #endif // PWR and LED driver -#define PWR_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG) #if defined(PCBX9LITE) - #define PWR_SWITCH_GPIO GPIOA - #define PWR_SWITCH_GPIO_PIN GPIO_Pin_7 // PA.07 - #define PWR_ON_GPIO GPIOA - #define PWR_ON_GPIO_PIN GPIO_Pin_6 // PA.06 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOA, 7) // PA.07 + #define PWR_ON_GPIO GPIO_PIN(GPIOA, 6) // PA.06 #elif defined(PCBXLITE) - #define PWR_SWITCH_GPIO GPIOA - #define PWR_SWITCH_GPIO_PIN GPIO_Pin_7 // PA.07 - #define PWR_ON_GPIO GPIOE - #define PWR_ON_GPIO_PIN GPIO_Pin_9 // PE.09 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOA, 7) // PA.07 + #define PWR_ON_GPIO GPIO_PIN(GPIOE, 9) // PE.09 #elif defined(RADIO_COMMANDO8) - #define PWR_SWITCH_GPIO GPIOD - #define PWR_SWITCH_GPIO_PIN GPIO_Pin_11 // PD.11 - #define PWR_ON_GPIO GPIOD - #define PWR_ON_GPIO_PIN GPIO_Pin_10 // PD.10 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOD, 11) // PD.11 + #define PWR_ON_GPIO GPIO_PIN(GPIOD, 10) // PD.10 #elif defined(RADIO_FAMILY_T20) - #define PWR_SWITCH_GPIO GPIOG - #define PWR_SWITCH_GPIO_PIN GPIO_Pin_5 // PG.05 - #define PWR_ON_GPIO GPIOG - #define PWR_ON_GPIO_PIN GPIO_Pin_6 // PG.06 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOG, 5) // PG.05 + #define PWR_ON_GPIO GPIO_PIN(GPIOG, 6) // PG.06 #else - #define PWR_SWITCH_GPIO GPIOD - #define PWR_SWITCH_GPIO_PIN GPIO_Pin_1 // PD.01 - #define PWR_ON_GPIO GPIOD - #define PWR_ON_GPIO_PIN GPIO_Pin_0 // PD.00 + #define PWR_SWITCH_GPIO GPIO_PIN(GPIOD, 1) // PD.01 + #define PWR_ON_GPIO GPIO_PIN(GPIOD, 0) // PD.00 #endif #if defined(RADIO_X9DP2019) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_ResetBits - #define GPIO_LED_GPIO_OFF GPIO_SetBits - #define LED_RED_GPIO GPIOA - #define LED_RED_GPIO_PIN GPIO_Pin_13 // PA.13 + #define GPIO_LED_GPIO_ON gpio_clear + #define GPIO_LED_GPIO_OFF gpio_set + #define LED_RED_GPIO GPIO_PIN(GPIOA, 13) #elif defined(PCBXLITES) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_ResetBits - #define GPIO_LED_GPIO_OFF GPIO_SetBits - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_6 // PE.06 - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_4 // PE.04 + #define GPIO_LED_GPIO_ON gpio_clear + #define GPIO_LED_GPIO_OFF gpio_set + #define LED_RED_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #elif defined(PCBXLITE) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_ResetBits - #define GPIO_LED_GPIO_OFF GPIO_SetBits - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_6 // PE.06 - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_4 // PE.04 - #define LED_GREEN_GPIO GPIOE - #define LED_GREEN_GPIO_PIN GPIO_Pin_5 // PE.05 + #define GPIO_LED_GPIO_ON gpio_clear + #define GPIO_LED_GPIO_OFF gpio_set + #define LED_GREEN_GPIO GPIO_PIN(GPIOE, 5) // PE.05 + #define LED_RED_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #elif defined(PCBX7ACCESS) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_BLUE_GPIO GPIOB - #define LED_BLUE_GPIO_PIN GPIO_Pin_1 // PB.01 - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_4 // PC.04 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_BLUE_GPIO GPIO_PIN(GPIOB, 1) // PB.01 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 4) // PC.04 #elif defined(RADIO_T8) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_4 // PC.04 - #define LED_BLUE_GPIO GPIOC - #define LED_BLUE_GPIO_PIN GPIO_Pin_5 // PC.05 - #define LED_GREEN_GPIO GPIOB - #define LED_GREEN_GPIO_PIN GPIO_Pin_1 // PB.01 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOB, 1) // PB.01 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 4) // PC.04 + #define LED_BLUE_GPIO GPIO_PIN(GPIOC, 5) // PC.05 #elif defined(RADIO_COMMANDO8) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_2 // PC.02 - #define LED_BLUE_GPIO GPIOC - #define LED_BLUE_GPIO_PIN GPIO_Pin_1 // PC.01 - #define LED_GREEN_GPIO GPIOC - #define LED_GREEN_GPIO_PIN GPIO_Pin_0 // PC.00 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOC, 0) // PC.00 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 2) // PC.02 + #define LED_BLUE_GPIO GPIO_PIN(GPIOC, 1) // PC.01 #elif defined(RADIO_ZORRO) || defined(RADIO_POCKET) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_GREEN_GPIO GPIOE - #define LED_GREEN_GPIO_PIN GPIO_Pin_2 // PE.02 - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_13 // PE.13 - #define LED_BLUE_GPIO GPIOA - #define LED_BLUE_GPIO_PIN GPIO_Pin_7 // PA.07 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOE, 2) // PE.02 + #define LED_RED_GPIO GPIO_PIN(GPIOE, 13) // PE.13 + #define LED_BLUE_GPIO GPIO_PIN(GPIOA, 7) // PA.07 #elif defined(RADIO_T14) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_2 // PE.02 - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_13 // PE.13 - #define LED_GREEN_GPIO GPIOA - #define LED_GREEN_GPIO_PIN GPIO_Pin_7 // PA.07 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_RED_GPIO GPIO_PIN(GPIOE, 2) // PE.02 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 13) // PE.13 + #define LED_GREEN_GPIO GPIO_PIN(GPIOA, 7) // PA.07 #elif defined(RADIO_TLITE) || defined(RADIO_TPRO) || defined(RADIO_TPROV2) || defined(RADIO_TX12) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_GREEN_GPIO GPIOB - #define LED_GREEN_GPIO_PIN GPIO_Pin_1 // PB.01 - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_5 // PC.05 - #define LED_BLUE_GPIO GPIOC - #define LED_BLUE_GPIO_PIN GPIO_Pin_4 // PC.04 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOB, 1) // PB.01 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 5) // PC.05 + #define LED_BLUE_GPIO GPIO_PIN(GPIOC, 4) // PC.04 #elif defined(RADIO_FAMILY_T20) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_GREEN_GPIO GPIOG - #define LED_GREEN_GPIO_PIN GPIO_Pin_1 // PG.01 - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_5 // PC.05 - #define LED_BLUE_GPIO GPIOC - #define LED_BLUE_GPIO_PIN GPIO_Pin_4 // PC.04 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOG, 1) // PG.01 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 5) // PC.05 + #define LED_BLUE_GPIO GPIO_PIN(GPIOC, 4) // PC.04 #elif defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_MT12) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_GREEN_GPIO GPIOA - #define LED_GREEN_GPIO_PIN GPIO_Pin_7 // PA.07 - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_13 // PE.13 - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_2 // PE.02 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOA, 7) // PA.07 + #define LED_RED_GPIO GPIO_PIN(GPIOE, 13) // PE.13 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 2) // PE.02 #elif defined(PCBX7) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_GREEN_GPIO GPIOC - #define LED_GREEN_GPIO_PIN GPIO_Pin_4 // PC.04 - #define LED_RED_GPIO GPIOC - #define LED_RED_GPIO_PIN GPIO_Pin_5 // PC.05 - #define LED_BLUE_GPIO GPIOB - #define LED_BLUE_GPIO_PIN GPIO_Pin_1 // PB.01 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOC, 4) // PC.04 + #define LED_RED_GPIO GPIO_PIN(GPIOC, 5) // PC.05 + #define LED_BLUE_GPIO GPIO_PIN(GPIOB, 1) // PB.01 #elif defined(PCBX9LITES) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_5 // PE.05 - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_6 // PE.06 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_RED_GPIO GPIO_PIN(GPIOE, 5) // PE.05 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #elif defined(PCBX9LITE) #define STATUS_LEDS - #define GPIO_LED_GPIO_ON GPIO_SetBits - #define GPIO_LED_GPIO_OFF GPIO_ResetBits - #define LED_RED_GPIO GPIOE - #define LED_RED_GPIO_PIN GPIO_Pin_5 // PE.05 - #define LED_GREEN_GPIO GPIOE - #define LED_GREEN_GPIO_PIN GPIO_Pin_4 // PE.04 - #define LED_BLUE_GPIO GPIOE - #define LED_BLUE_GPIO_PIN GPIO_Pin_6 // PE.06 + #define GPIO_LED_GPIO_ON gpio_set + #define GPIO_LED_GPIO_OFF gpio_clear + #define LED_GREEN_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define LED_RED_GPIO GPIO_PIN(GPIOE, 5) // PE.05 + #define LED_BLUE_GPIO GPIO_PIN(GPIOE, 6) // PE.06 #endif #if defined(RADIO_MT12) #define LED_STRIP_LENGTH 7 - #define LED_STRIP_GPIO GPIOA - #define LED_STRIP_GPIO_PIN_DATA LL_GPIO_PIN_8 // PA.08 / TIM1_CH1 - #define LED_STRIP_GPIO_PIN_AF LL_GPIO_AF_1 // TIM1 / TIM2 + #define LED_STRIP_GPIO GPIO_PIN(GPIOA, 8) // PA.08 / TIM1_CH1 + #define LED_STRIP_GPIO_AF LL_GPIO_AF_1 // TIM1 / TIM2 #define LED_STRIP_TIMER TIM1 #define LED_STRIP_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define LED_STRIP_TIMER_CHANNEL LL_TIM_CHANNEL_CH1 @@ -1908,31 +1856,42 @@ #define LED_STRIP_TIMER_DMA_IRQn DMA2_Stream5_IRQn #define LED_STRIP_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler #define LED_STRIP_REFRESH_PERIOD 50 //ms +#elif defined(RADIO_T14) + #define LED_STRIP_LENGTH 1 + #define LED_STRIP_GPIO GPIO_PIN(GPIOA, 10) // PA.10 / TIM1_CH3 + #define LED_STRIP_GPIO_AF LL_GPIO_AF_1 + #define LED_STRIP_TIMER TIM1 + #define LED_STRIP_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define LED_STRIP_TIMER_CHANNEL LL_TIM_CHANNEL_CH3 + #define LED_STRIP_TIMER_DMA DMA2 + #define LED_STRIP_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 + #define LED_STRIP_TIMER_DMA_STREAM LL_DMA_STREAM_5 + #define LED_STRIP_TIMER_DMA_IRQn DMA2_Stream5_IRQn + #define LED_STRIP_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler + #define LED_STRIP_REFRESH_PERIOD 50 //ms #endif #if defined(FUNCTION_SWITCHES) #if defined(RADIO_FAMILY_T20) - #define FS_RCC_AHB1Periph RCC_AHB1Periph_GPIOF #define GPIO_FSLED_GPIO_ON GPIO_SetBits #define GPIO_FSLED_GPIO_OFF GPIO_ResetBits #define FSLED_GPIO GPIOF - #define FSLED_GPIO_PIN_1 GPIO_Pin_10 - #define FSLED_GPIO_PIN_2 GPIO_Pin_9 - #define FSLED_GPIO_PIN_3 GPIO_Pin_8 - #define FSLED_GPIO_PIN_4 GPIO_Pin_7 - #define FSLED_GPIO_PIN_5 GPIO_Pin_6 - #define FSLED_GPIO_PIN_6 GPIO_Pin_13 + #define FSLED_GPIO_PIN_1 GPIO_PIN(FSLED_GPIO, 10) + #define FSLED_GPIO_PIN_2 GPIO_PIN(FSLED_GPIO, 9) + #define FSLED_GPIO_PIN_3 GPIO_PIN(FSLED_GPIO, 8) + #define FSLED_GPIO_PIN_4 GPIO_PIN(FSLED_GPIO, 7) + #define FSLED_GPIO_PIN_5 GPIO_PIN(FSLED_GPIO, 6) + #define FSLED_GPIO_PIN_6 GPIO_PIN(FSLED_GPIO, 13) #else - #define FS_RCC_AHB1Periph RCC_AHB1Periph_GPIOF #define GPIO_FSLED_GPIO_ON GPIO_SetBits #define GPIO_FSLED_GPIO_OFF GPIO_ResetBits #define FSLED_GPIO GPIOF - #define FSLED_GPIO_PIN_1 GPIO_Pin_5 - #define FSLED_GPIO_PIN_2 GPIO_Pin_4 - #define FSLED_GPIO_PIN_3 GPIO_Pin_3 - #define FSLED_GPIO_PIN_4 GPIO_Pin_2 - #define FSLED_GPIO_PIN_5 GPIO_Pin_1 - #define FSLED_GPIO_PIN_6 GPIO_Pin_0 + #define FSLED_GPIO_PIN_1 GPIO_PIN(FSLED_GPIO, 5) + #define FSLED_GPIO_PIN_2 GPIO_PIN(FSLED_GPIO, 4) + #define FSLED_GPIO_PIN_3 GPIO_PIN(FSLED_GPIO, 3) + #define FSLED_GPIO_PIN_4 GPIO_PIN(FSLED_GPIO, 2) + #define FSLED_GPIO_PIN_5 GPIO_PIN(FSLED_GPIO, 1) + #define FSLED_GPIO_PIN_6 GPIO_PIN(FSLED_GPIO, 0) #endif #endif @@ -1942,287 +1901,204 @@ #endif #if defined(PCBXLITE) || defined(PCBX9LITE) #if defined(PCBXLITES) || defined(PCBX9LITE) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOA - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_15 // PA.15 + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOA, 15) // PA.15 #else - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOD - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_9 // PD.09 + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 9) // PD.09 #endif - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 - #define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 - #define INTMODULE_GPIO_PinSource_TX GPIO_PinSource6 - #define INTMODULE_GPIO_PinSource_RX GPIO_PinSource7 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 6) // PB.06 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 7) // PB.07 + #define INTMODULE_USART USART1 + #define INTMODULE_USART_IRQn USART1_IRQn + #define INTMODULE_DMA DMA2 + #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 + #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn + #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler + #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 + #if defined(PCBXLITES) + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOC, 8) // PC.08 + #define INTMODULE_BOOTCMD_DEFAULT 1 // SET + #endif +#elif defined(RADIO_X9DP2019) + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOA, 7) // PA.07 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 6) // PB.06 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 7) // PB.07 + #define INTMODULE_USART USART1 + #define INTMODULE_USART_IRQn USART1_IRQn + #define INTMODULE_DMA DMA2 + #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 + #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn + #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler + #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 +#elif defined(RADIO_X7ACCESS) + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOA, 7) // PC.05 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 6) // PB.06 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 7) // PB.07 #define INTMODULE_USART USART1 - #define INTMODULE_GPIO_AF LL_GPIO_AF_7 #define INTMODULE_USART_IRQHandler USART1_IRQHandler #define INTMODULE_USART_IRQn USART1_IRQn #define INTMODULE_DMA DMA2 #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler - #define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 - #define INTMODULE_DMA_CHANNEL DMA_Channel_4 - #if defined(PCBXLITES) - #define INTMODULE_BOOTCMD_GPIO GPIOC - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_8 // PC.08 - #define INTMODULE_BOOTCMD_DEFAULT 1 // SET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_SetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); - #endif -#elif defined(RADIO_X9DP2019) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOA - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_7 // PA.07 - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 - #define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 - #define INTMODULE_GPIO_PinSource_TX GPIO_PinSource6 - #define INTMODULE_GPIO_PinSource_RX GPIO_PinSource7 - #define INTMODULE_USART USART1 - #define INTMODULE_GPIO_AF LL_GPIO_AF_7 - #define INTMODULE_USART_IRQHandler USART1_IRQHandler - #define INTMODULE_USART_IRQn USART1_IRQn - #define INTMODULE_DMA DMA2 - #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 - #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn - #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler - #define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 - #define INTMODULE_DMA_CHANNEL DMA_Channel_4 -#elif defined(RADIO_X7ACCESS) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOC - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_5 // PC.05 - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 - #define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 - #define INTMODULE_GPIO_PinSource_TX GPIO_PinSource6 - #define INTMODULE_GPIO_PinSource_RX GPIO_PinSource7 - #define INTMODULE_USART USART1 - #define INTMODULE_GPIO_AF LL_GPIO_AF_7 - #define INTMODULE_USART_IRQHandler USART1_IRQHandler - #define INTMODULE_USART_IRQn USART1_IRQn - #define INTMODULE_DMA DMA2 - #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 - #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn - #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler - #define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 - #define INTMODULE_DMA_CHANNEL DMA_Channel_4 -#elif defined(RADIO_ZORRO) || defined(RADIO_POCKET) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_MT12) || defined(RADIO_T20V2) || defined(RADIO_T14) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOC + #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 +#elif defined(RADIO_ZORRO) || defined(RADIO_POCKET) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_MT12) || defined(RADIO_T20V2) || defined(RADIO_T14) #if defined(RADIO_T20V2) - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_6 // PC.06 - #define INTMODULE_BOOTCMD_GPIO GPIOE - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_4 // PE.04 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOC, 6) // PC.06 #else - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_4 // PC.04 #if defined(RADIO_T14) - #define INTMODULE_BOOTCMD_GPIO GPIOE - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_14 // PE.14 + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOE, 14) // PE.14 #else - #define INTMODULE_BOOTCMD_GPIO GPIOB - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_1 // PB.01 + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOB, 1) // PB.01 #endif + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOC, 4) // PC.04 #endif - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN GPIO_Pin_6 // PB.06 - #define INTMODULE_RX_GPIO_PIN GPIO_Pin_7 // PB.07 - #define INTMODULE_GPIO_PinSource_TX GPIO_PinSource6 - #define INTMODULE_GPIO_PinSource_RX GPIO_PinSource7 - #define INTMODULE_USART USART1 - #define INTMODULE_GPIO_AF LL_GPIO_AF_7 - #define INTMODULE_USART_IRQHandler USART1_IRQHandler - #define INTMODULE_USART_IRQn USART1_IRQn - #define INTMODULE_DMA DMA2 - #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 + #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 6) // PB.06 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 7) // PB.07 + #define INTMODULE_USART USART1 + #define INTMODULE_USART_IRQHandler USART1_IRQHandler + #define INTMODULE_USART_IRQn USART1_IRQn + #define INTMODULE_DMA DMA2 + #define INTMODULE_DMA_STREAM LL_DMA_STREAM_7 #define INTMODULE_DMA_STREAM_IRQ DMA2_Stream7_IRQn #define INTMODULE_DMA_STREAM_IRQHandler DMA2_Stream7_IRQHandler - #define INTMODULE_DMA_FLAG_TC DMA_IT_TCIF7 - #define INTMODULE_DMA_CHANNEL DMA_Channel_4 - #define INTMODULE_RX_DMA DMA2 - #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_2 - #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); + #define INTMODULE_DMA_CHANNEL LL_DMA_CHANNEL_4 + #define INTMODULE_RX_DMA DMA2 + #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_2 + #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 #elif defined(PCBX9E) || defined(PCBX9DP) || defined(RADIO_X7) - #define INTMODULE_PULSES - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOC - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_6 // PC.06 - #define INTMODULE_TX_GPIO GPIOA - #define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_10 // PA.10 - #define INTMODULE_TX_GPIO_AF LL_GPIO_AF_1 - #define INTMODULE_TIMER TIM1 - #define INTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 - #define INTMODULE_TIMER_IRQn TIM1_UP_TIM10_IRQn - #define INTMODULE_TIMER_IRQHandler TIM1_UP_TIM10_IRQHandler - #define INTMODULE_TIMER_DMA DMA2 - #define INTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 - #define INTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_5 - #define INTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream5_IRQn - #define INTMODULE_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler - #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOC, 6) // PC.06 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOA, 10) // PA.10 + #define INTMODULE_TX_GPIO_AF LL_GPIO_AF_1 + #define INTMODULE_TIMER TIM1 + #define INTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 + #define INTMODULE_TIMER_IRQn TIM1_UP_TIM10_IRQn + #define INTMODULE_TIMER_IRQHandler TIM1_UP_TIM10_IRQHandler + #define INTMODULE_TIMER_DMA DMA2 + #define INTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 + #define INTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_5 + #define INTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream5_IRQn + #define INTMODULE_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler + #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #elif (defined(RADIO_FAMILY_JUMPER_T12) && defined(HARDWARE_INTERNAL_MODULE)) || defined(RADIO_TX12) || defined(RADIO_T8) || defined(RADIO_TPRO) || defined(RADIO_TPROV2) || defined(RADIO_T20) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA1) - #define INTMODULE_PWR_GPIO GPIOC - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_6 // PC.06 - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_10 // PB.10 - #define INTMODULE_RX_GPIO_PIN LL_GPIO_PIN_11 // PB.11 - #define INTMODULE_USART USART3 - #define INTMODULE_GPIO_AF LL_GPIO_AF_7 - #define INTMODULE_USART_IRQn USART3_IRQn - #define INTMODULE_USART_IRQHandler USART3_IRQHandler + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOC, 6) // PC.06 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 + #define INTMODULE_USART USART3 + #define INTMODULE_USART_IRQn USART3_IRQn // DMA1_Stream3 is already used by SDIO // #define INTMODULE_DMA NULL // #define INTMODULE_DMA_CHANNEL 0 // #define INTMODULE_DMA_STREAM 0 - #define INTMODULE_RX_DMA DMA1 - #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_1 - #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 + #define INTMODULE_RX_DMA DMA1 + #define INTMODULE_RX_DMA_STREAM LL_DMA_STREAM_1 + #define INTMODULE_RX_DMA_CHANNEL LL_DMA_CHANNEL_4 #if defined(RADIO_TLITE) - #define INTMODULE_BOOTCMD_GPIO GPIOA - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_5 // PA.05 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOA, 5) // PA.05 + #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET #elif defined(RADIO_TPRO) || defined(RADIO_TPROV2) - #define INTMODULE_BOOTCMD_GPIO GPIOF - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_11 // PF.11 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOF, 11) // PF.11 + #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET #elif defined(RADIO_FAMILY_T20) - #define INTMODULE_BOOTCMD_GPIO GPIOE - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_4 // PE.04 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOE, 4) // PE.04 + #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET #elif defined(RADIO_LR3PRO) - #define INTMODULE_BOOTCMD_GPIO GPIOB - #define INTMODULE_BOOTCMD_GPIO_PIN GPIO_Pin_5 // PB.05 - #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET - #define INIT_INTMODULE_BOOTCMD_PIN() GPIO_ResetBits(INTMODULE_BOOTCMD_GPIO, INTMODULE_BOOTCMD_GPIO_PIN); + #define INTMODULE_BOOTCMD_GPIO GPIO_PIN(GPIOB, 5) // PB.05 + #define INTMODULE_BOOTCMD_DEFAULT 0 // RESET #endif #elif defined(RADIO_COMMANDO8) - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOF | RCC_AHB1Periph_DMA1) - #define INTMODULE_RCC_APB1Periph (RCC_APB1Periph_USART3 | RCC_APB1Periph_TIM2) - #define INTMODULE_RCC_APB2Periph 0 - #define INTMODULE_PWR_GPIO GPIOE - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PE.08 - #define INTMODULE_GPIO GPIOB - #define INTMODULE_TX_GPIO_PIN GPIO_Pin_10 // PB.10 - #define INTMODULE_RX_GPIO_PIN GPIO_Pin_11 // PB.11 - #define INTMODULE_GPIO_PinSource_TX GPIO_PinSource10 - #define INTMODULE_GPIO_PinSource_RX GPIO_PinSource11 - #define INTMODULE_USART USART3 - #define INTMODULE_GPIO_AF GPIO_AF_USART3 - #define INTMODULE_GPIO_AF_LL LL_GPIO_AF_7 - #define INTMODULE_USART_IRQn USART3_IRQn - #define INTMODULE_USART_IRQHandler USART3_IRQHandler + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOE, 8) // PE.08 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 + #define INTMODULE_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 + #define INTMODULE_USART USART3 + #define INTMODULE_USART_IRQn USART3_IRQn // // DMA1_Stream3 is already used by SDIO // #define INTMODULE_DMA NULL // #define INTMODULE_DMA_CHANNEL 0 // #define INTMODULE_DMA_STREAM 0 #else - #define INTMODULE_PULSES - #define INTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) - #define INTMODULE_PWR_GPIO GPIOD - #define INTMODULE_PWR_GPIO_PIN GPIO_Pin_15 // PD.15 - #define INTMODULE_TX_GPIO GPIOA - #define INTMODULE_TX_GPIO_PIN LL_GPIO_PIN_10 // PA.10 - #define INTMODULE_TX_GPIO_AF LL_GPIO_AF_1 - #define INTMODULE_TIMER TIM1 - #define INTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 - #define INTMODULE_TIMER_IRQn TIM1_UP_TIM10_IRQn - #define INTMODULE_TIMER_IRQHandler TIM1_UP_TIM10_IRQHandler - #define INTMODULE_TIMER_DMA DMA2 - #define INTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 - #define INTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_5 - #define INTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream5_IRQn - #define INTMODULE_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler - #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) + #define INTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 15) // PD.15 + #define INTMODULE_TX_GPIO GPIO_PIN(GPIOA, 10) // PA.10 + #define INTMODULE_TX_GPIO_AF LL_GPIO_AF_1 + #define INTMODULE_TIMER TIM1 + #define INTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH3 + #define INTMODULE_TIMER_IRQn TIM1_UP_TIM10_IRQn + #define INTMODULE_TIMER_IRQHandler TIM1_UP_TIM10_IRQHandler + #define INTMODULE_TIMER_DMA DMA2 + #define INTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_6 + #define INTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_5 + #define INTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream5_IRQn + #define INTMODULE_TIMER_DMA_IRQHandler DMA2_Stream5_IRQHandler + #define INTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #endif // External Module #if defined(PCBXLITE) || defined(PCBX9LITE) || defined(RADIO_X9DP2019) || defined(PCBX7ACCESS) || defined(RADIO_ZORRO) || defined(RADIO_POCKET) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_MT12) || defined(RADIO_T14) #if defined(RADIO_X9DP2019) || defined(RADIO_X7ACCESS) || defined(RADIO_ZORRO)|| defined(RADIO_POCKET) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_MT12)|| defined(RADIO_T14) - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) - #define EXTMODULE_PWR_GPIO GPIOD - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PD.08 + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 8) // PD.08 #elif defined(PCBX9LITE) - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_DMA2) - #define EXTMODULE_PWR_GPIO GPIOA - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PA.08 + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOA, 8) // PA.08 #else - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) - #define EXTMODULE_PWR_GPIO GPIOD - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_11 // PD.11 + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 11) // PD.11 #endif - #define EXTERNAL_MODULE_PWR_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) - #define EXTERNAL_MODULE_PWR_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) - #define IS_EXTERNAL_MODULE_ON() (GPIO_ReadInputDataBit(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) == Bit_SET) - #define EXTMODULE_TX_GPIO GPIOC - #define EXTMODULE_USART_GPIO EXTMODULE_TX_GPIO - #define EXTMODULE_TX_GPIO_PIN LL_GPIO_PIN_6 // PC.06 - #define EXTMODULE_RX_GPIO_PIN LL_GPIO_PIN_7 // PC.07 + #define EXTERNAL_MODULE_PWR_ON() gpio_set(EXTMODULE_PWR_GPIO) + #define EXTERNAL_MODULE_PWR_OFF() gpio_clear(EXTMODULE_PWR_GPIO) + #define IS_EXTERNAL_MODULE_ON() gpio_read(EXTMODULE_PWR_GPIO) + #define EXTMODULE_TX_GPIO GPIO_PIN(GPIOC, 6) // PC.06 + #define EXTMODULE_RX_GPIO GPIO_PIN(GPIOC, 7) // PC.07 #define EXTMODULE_TIMER TIM8 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH1 #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define EXTMODULE_TIMER_IRQn TIM8_UP_TIM13_IRQn #define EXTMODULE_TIMER_IRQHandler TIM8_UP_TIM13_IRQHandler - #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF_TIM8 // TIM8_CH1 + #define EXTMODULE_TIMER_TX_GPIO_AF LL_GPIO_AF_3 // TIM8_CH1 #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 - #define EXTMODULE_TIMER_DMA_STREAM DMA2_Stream1 #define EXTMODULE_TIMER_DMA DMA2 - #define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_1 + #define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_1 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream1_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA2_Stream1_IRQHandler - #define EXTMODULE_USART_GPIO_AF GPIO_AF_USART6 - #define EXTMODULE_USART_GPIO_AF_LL LL_GPIO_AF_8 #define EXTMODULE_USART USART6 #define EXTMODULE_USART_IRQn USART6_IRQn #define EXTMODULE_USART_IRQHandler USART6_IRQHandler #define EXTMODULE_USART_TX_DMA DMA2 #define EXTMODULE_USART_TX_DMA_CHANNEL LL_DMA_CHANNEL_5 - #define EXTMODULE_USART_TX_DMA_STREAM DMA2_Stream6 - #define EXTMODULE_USART_TX_DMA_STREAM_LL LL_DMA_STREAM_6 + #define EXTMODULE_USART_TX_DMA_STREAM LL_DMA_STREAM_6 #define EXTMODULE_USART_RX_DMA_CHANNEL LL_DMA_CHANNEL_5 - #define EXTMODULE_USART_RX_DMA_STREAM DMA2_Stream1 - #define EXTMODULE_USART_RX_DMA_STREAM_LL LL_DMA_STREAM_1 + #define EXTMODULE_USART_RX_DMA_STREAM LL_DMA_STREAM_1 #else - #define EXTMODULE_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA2) #if defined(RADIO_COMMANDO8) - #define EXTMODULE_RF_SWITCH_GPIO GPIOE //Antenna switching port - #define EXTMODULE_RF_SWITCH_GPIO_PIN GPIO_Pin_7 //Antenna switching pin //PE.07 - #define EXTMODULE_PWR_GPIO GPIOE //External tuner power port //PE.02 - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_2 //External tuner power pin - #define EXTERNAL_MODULE_PWR_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN|EXTMODULE_RF_SWITCH_GPIO_PIN) - #define EXTERNAL_MODULE_PWR_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN|EXTMODULE_RF_SWITCH_GPIO_PIN) + #define EXTMODULE_RF_SWITCH_GPIO GPIO_PIN(GPIOE, 7) // Antenna switching: PE.07 + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOE, 2) // External tuner power: PE.02 + #define EXTERNAL_MODULE_PWR_ON() \ + do { \ + gpio_set(EXTMODULE_PWR_GPIO); \ + gpio_set(EXTMODULE_RF_SWITCH_GPIO); \ + } while (0) + #define EXTERNAL_MODULE_PWR_OFF() \ + do { \ + gpio_clear(EXTMODULE_PWR_GPIO); \ + gpio_clear(EXTMODULE_RF_SWITCH_GPIO); \ + } while (0) #elif defined(RADIO_FAMILY_T20) - #define EXTMODULE_PWR_GPIO GPIOB - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_1 // PB.01 - #define EXTERNAL_MODULE_PWR_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) - #define EXTERNAL_MODULE_PWR_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOB, 1) // PB.01 + #define EXTERNAL_MODULE_PWR_ON() gpio_set(EXTMODULE_PWR_GPIO) + #define EXTERNAL_MODULE_PWR_OFF() gpio_clear(EXTMODULE_PWR_GPIO) #else - #define EXTMODULE_PWR_GPIO GPIOD - #define EXTMODULE_PWR_GPIO_PIN GPIO_Pin_8 // PD.08 - #define EXTERNAL_MODULE_PWR_ON() GPIO_SetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) - #define EXTERNAL_MODULE_PWR_OFF() GPIO_ResetBits(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) + #define EXTMODULE_PWR_GPIO GPIO_PIN(GPIOD, 8) // PD.08 + #define EXTERNAL_MODULE_PWR_ON() gpio_set(EXTMODULE_PWR_GPIO) + #define EXTERNAL_MODULE_PWR_OFF() gpio_clear(EXTMODULE_PWR_GPIO) #endif - #define IS_EXTERNAL_MODULE_ON() (GPIO_ReadInputDataBit(EXTMODULE_PWR_GPIO, EXTMODULE_PWR_GPIO_PIN) == Bit_SET) - #define EXTMODULE_TX_GPIO GPIOA - #define EXTMODULE_TX_GPIO_PIN GPIO_Pin_7 - #define EXTMODULE_TX_GPIO_PinSource GPIO_PinSource7 // PA.07 + #define IS_EXTERNAL_MODULE_ON() gpio_read(EXTMODULE_PWR_GPIO) + #define EXTMODULE_TX_GPIO GPIO_PIN(GPIOA, 7) // PA.07 #define EXTMODULE_TIMER TIM8 #define EXTMODULE_TIMER_Channel LL_TIM_CHANNEL_CH1N - #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF_TIM8 // TIM8_CH1N + #define EXTMODULE_TIMER_TX_GPIO_AF GPIO_AF3 // TIM8_CH1N #define EXTMODULE_TIMER_IRQn TIM8_UP_TIM13_IRQn #define EXTMODULE_TIMER_IRQHandler TIM8_UP_TIM13_IRQHandler - #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 - #define EXTMODULE_TIMER_DMA_STREAM DMA2_Stream1 #define EXTMODULE_TIMER_DMA DMA2 - #define EXTMODULE_TIMER_DMA_STREAM_LL LL_DMA_STREAM_1 + #define EXTMODULE_TIMER_DMA_STREAM LL_DMA_STREAM_1 + #define EXTMODULE_TIMER_DMA_CHANNEL LL_DMA_CHANNEL_7 #define EXTMODULE_TIMER_DMA_STREAM_IRQn DMA2_Stream1_IRQn #define EXTMODULE_TIMER_DMA_IRQHandler DMA2_Stream1_IRQHandler #define EXTMODULE_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) @@ -2231,17 +2107,15 @@ // Trainer Port #if defined(PCBXLITES) || defined(PCBX9LITE) // on these 2 radios the trainer port already uses DMA1_Stream6, we won't use the DMA - #define TRAINER_GPIO GPIOD - #define TRAINER_IN_GPIO_PIN LL_GPIO_PIN_13 // PD.13 + #define TRAINER_IN_GPIO GPIO_PIN(GPIOD, 13) // PD.13 #define TRAINER_IN_TIMER_Channel LL_TIM_CHANNEL_CH2 - #define TRAINER_OUT_GPIO_PIN LL_GPIO_PIN_12 // PD.12 + #define TRAINER_OUT_GPIO GPIO_PIN(GPIOD, 12) // PD.12 #define TRAINER_OUT_TIMER_Channel LL_TIM_CHANNEL_CH1 -#if defined(PCBX9LITE) - #define TRAINER_DETECT_GPIO GPIOD - #define TRAINER_DETECT_GPIO_PIN LL_GPIO_PIN_11 // PD.11 -#endif + #if defined(PCBX9LITE) + #define TRAINER_DETECT_GPIO GPIO_PIN(GPIOD, 11) // PD.11 + #endif #define TRAINER_TIMER TIM4 - #define TRAINER_GPIO_AF GPIO_AF_TIM4 // TIM4_CH1 (Out) + TIM4_CH2 (In) + #define TRAINER_GPIO_AF GPIO_AF2 // TIM4_CH1 (Out) + TIM4_CH2 (In) #define TRAINER_TIMER_IRQn TIM4_IRQn #define TRAINER_TIMER_IRQHandler TIM4_IRQHandler #define TRAINER_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) @@ -2250,20 +2124,16 @@ #define TRAINER_TIMER_IRQn TIM4_IRQn #define TRAINER_TIMER_IRQHandler TIM4_IRQHandler #else - #define TRAINER_GPIO GPIOC - #define TRAINER_IN_GPIO_PIN LL_GPIO_PIN_8 // PC.08 + #define TRAINER_IN_GPIO GPIO_PIN(GPIOC, 8) // PC.08 #define TRAINER_IN_TIMER_Channel LL_TIM_CHANNEL_CH3 - #define TRAINER_OUT_GPIO_PIN LL_GPIO_PIN_9 // PC.09 + #define TRAINER_OUT_GPIO GPIO_PIN(GPIOC, 9) // PC.09 #define TRAINER_OUT_TIMER_Channel LL_TIM_CHANNEL_CH4 #if defined(RADIO_FAMILY_T20) - #define TRAINER_DETECT_GPIO GPIOE - #define TRAINER_DETECT_GPIO_PIN LL_GPIO_PIN_8 // PE.03 + #define TRAINER_DETECT_GPIO GPIO_PIN(GPIOE, 3) // PE.03 #elif defined(RADIO_MT12) - #define TRAINER_DETECT_GPIO GPIOD - #define TRAINER_DETECT_GPIO_PIN LL_GPIO_PIN_14 // PD.14 + #define TRAINER_DETECT_GPIO GPIO_PIN(GPIOD, 14) // PD.14 #else - #define TRAINER_DETECT_GPIO GPIOA - #define TRAINER_DETECT_GPIO_PIN LL_GPIO_PIN_8 // PA.08 + #define TRAINER_DETECT_GPIO GPIO_PIN(GPIOA, 8) // PA.08 #endif #if !defined(RADIO_X9DP2019) && !defined(RADIO_X7ACCESS) #define TRAINER_DETECT_INVERTED @@ -2281,51 +2151,29 @@ #else #define HARDWARE_TRAINER_AUX_SERIAL #define AUX_SERIAL_GPIO GPIOB - #define AUX_SERIAL_GPIO_PIN_TX GPIO_Pin_10 // PB.10 - #define AUX_SERIAL_GPIO_PIN_RX GPIO_Pin_11 // PB.11 - #define AUX_SERIAL_GPIO_PinSource_TX GPIO_PinSource10 - #define AUX_SERIAL_GPIO_PinSource_RX GPIO_PinSource11 - #define AUX_SERIAL_GPIO_AF GPIO_AF_USART3 - #define AUX_SERIAL_GPIO_AF_LL LL_GPIO_AF_7 + #define AUX_SERIAL_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 + #define AUX_SERIAL_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 #define AUX_SERIAL_USART USART3 - #define AUX_SERIAL_USART_IRQHandler USART3_IRQHandler #define AUX_SERIAL_USART_IRQn USART3_IRQn #define AUX_SERIAL_DMA_RX DMA1 - #define AUX_SERIAL_DMA_Stream_RX DMA1_Stream1 - #define AUX_SERIAL_DMA_Stream_RX_LL LL_DMA_STREAM_1 - #define AUX_SERIAL_DMA_Channel_RX DMA_Channel_4 + #define AUX_SERIAL_DMA_RX_STREAM LL_DMA_STREAM_1 + #define AUX_SERIAL_DMA_RX_CHANNEL LL_DMA_CHANNEL_4 #endif -// No aux2 on taranis -#define AUX2_SERIAL_RCC_AHB1Periph 0 -#define AUX2_SERIAL_RCC_APB1Periph 0 -#define AUX2_SERIAL_RCC_APB2Periph 0 - // Telemetry -#define TELEMETRY_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) -#define TELEMETRY_RCC_APB1Periph RCC_APB1Periph_USART2 -#define TELEMETRY_RCC_APB2Periph RCC_APB2Periph_TIM11 -#define TELEMETRY_DIR_GPIO GPIOD -#define TELEMETRY_DIR_GPIO_PIN GPIO_Pin_4 // PD.04 -#if defined(PCBXLITE) || defined(PCBX9LITE) || defined(RADIO_X9DP2019) || defined(RADIO_X7ACCESS) - #define TELEMETRY_DIR_OUTPUT() LL_GPIO_ResetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN) - #define TELEMETRY_DIR_INPUT() LL_GPIO_SetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN) +#define TELEMETRY_DIR_GPIO GPIO_PIN(GPIOD, 4) // PD.04 +#if defined(PCBXLITE) || defined(PCBX9LITE) || defined(RADIO_X9DP2019) || \ + defined(RADIO_X7ACCESS) #define TELEMETRY_SET_INPUT 1 #else - #define TELEMETRY_DIR_OUTPUT() LL_GPIO_SetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN) - #define TELEMETRY_DIR_INPUT() LL_GPIO_ResetOutputPin(TELEMETRY_DIR_GPIO, TELEMETRY_DIR_GPIO_PIN) #define TELEMETRY_SET_INPUT 0 #endif -#define TELEMETRY_GPIO GPIOD -#define TELEMETRY_TX_GPIO_PIN GPIO_Pin_5 // PD.05 -#define TELEMETRY_RX_GPIO_PIN GPIO_Pin_6 // PD.06 -#define TELEMETRY_GPIO_PinSource_TX GPIO_PinSource5 -#define TELEMETRY_GPIO_PinSource_RX GPIO_PinSource6 -#define TELEMETRY_GPIO_AF GPIO_AF_USART2 +#define TELEMETRY_TX_GPIO GPIO_PIN(GPIOD, 5) // PD.05 +#define TELEMETRY_RX_GPIO GPIO_PIN(GPIOD, 6) // PD.06 #define TELEMETRY_USART USART2 #define TELEMETRY_DMA DMA1 #define TELEMETRY_DMA_Stream_TX LL_DMA_STREAM_6 -#define TELEMETRY_DMA_Channel_TX DMA_Channel_4 +#define TELEMETRY_DMA_Channel_TX LL_DMA_CHANNEL_4 #define TELEMETRY_DMA_TX_Stream_IRQ DMA1_Stream6_IRQn #define TELEMETRY_DMA_TX_IRQHandler DMA1_Stream6_IRQHandler #define TELEMETRY_DMA_TX_FLAG_TC DMA_IT_TCIF6 @@ -2344,7 +2192,6 @@ #define EXTI9_5_IRQ_Priority TELEMETRY_EXTI_PRIO #define TELEMETRY_TIMER TIM11 -#define TELEMETRY_TIMER_PRESCALER () #define TELEMETRY_TIMER_IRQn TIM1_TRG_COM_TIM11_IRQn #define TELEMETRY_TIMER_IRQHandler TIM1_TRG_COM_TIM11_IRQHandler @@ -2355,75 +2202,44 @@ // PCBREV #if defined(RADIO_X7) - #define PCBREV_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define PCBREV_GPIO GPIOA - #define PCBREV_GPIO_PIN GPIO_Pin_14 // PA.14 + #define PCBREV_GPIO_PIN GPIO_PIN(GPIOA, 14) // PA.14 #define PCBREV_GPIO_PULL_DOWN - #define PCBREV_VALUE() GPIO_ReadInputDataBit(PCBREV_GPIO, PCBREV_GPIO_PIN) -#else - #define PCBREV_RCC_AHB1Periph 0 + #define PCBREV_VALUE() (gpio_read(PCBREV_GPIO) >> 14) #endif // USB Charger #if defined(USB_CHARGER) - #define USB_CHARGER_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define USB_CHARGER_GPIO GPIOB - #define USB_CHARGER_GPIO_PIN GPIO_Pin_5 // PB.05 -#else - #define USB_CHARGER_RCC_AHB1Periph 0 + #define USB_CHARGER_GPIO GPIO_PIN(GPIOB, 5) #endif // S.Port update connector #if defined(PCBXLITE) #define SPORT_MAX_BAUDRATE 250000 // not tested - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define SPORT_UPDATE_PWR_GPIO GPIOD - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_8 // PD.08 - #define GPIO_SPORT_UPDATE_PWR_GPIO_ON GPIO_SetBits - #define GPIO_SPORT_UPDATE_PWR_GPIO_OFF GPIO_ResetBits + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOD, 8) // PD.08 #elif defined(PCBX7ACCESS) #define SPORT_MAX_BAUDRATE 400000 - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define SPORT_UPDATE_PWR_GPIO GPIOB - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_3 // PB.03 - #define GPIO_SPORT_UPDATE_PWR_GPIO_ON GPIO_SetBits - #define GPIO_SPORT_UPDATE_PWR_GPIO_OFF GPIO_ResetBits + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOB, 3) // PB.03 #elif defined(RADIO_X7) #define SPORT_MAX_BAUDRATE 250000 // < 400000 - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define SPORT_UPDATE_PWR_GPIO GPIOB - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_2 // PB.02 - #define GPIO_SPORT_UPDATE_PWR_GPIO_ON GPIO_SetBits - #define GPIO_SPORT_UPDATE_PWR_GPIO_OFF GPIO_ResetBits + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOB, 3) // PB.02 #elif defined(PCBX9LITE) #define SPORT_MAX_BAUDRATE 250000 // not tested - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define SPORT_UPDATE_PWR_GPIO GPIOE - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_15 // PE.15 - #define GPIO_SPORT_UPDATE_PWR_GPIO_ON GPIO_SetBits - #define GPIO_SPORT_UPDATE_PWR_GPIO_OFF GPIO_ResetBits + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOE, 15) // PE.15 #elif defined(RADIO_X9DP2019) #define SPORT_MAX_BAUDRATE 400000 - #define SPORT_UPDATE_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define SPORT_UPDATE_PWR_GPIO GPIOA - #define SPORT_UPDATE_PWR_GPIO_PIN GPIO_Pin_14 // PA.14 - #define GPIO_SPORT_UPDATE_PWR_GPIO_ON GPIO_SetBits - #define GPIO_SPORT_UPDATE_PWR_GPIO_OFF GPIO_ResetBits + #define SPORT_UPDATE_PWR_GPIO GPIO_PIN(GPIOA, 14) // PA.14 #else #define SPORT_MAX_BAUDRATE 400000 - #define SPORT_UPDATE_RCC_AHB1Periph 0 #endif // Heartbeat for iXJT / ISRM synchro -#define INTMODULE_HEARTBEAT_TRIGGER LL_EXTI_TRIGGER_FALLING +#define INTMODULE_HEARTBEAT_TRIGGER GPIO_FALLING #if !defined(HARDWARE_EXTERNAL_MODULE) // No heartbeat #elif defined(PCBXLITE) #define INTMODULE_HEARTBEAT - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define INTMODULE_HEARTBEAT_GPIO GPIOD - #define INTMODULE_HEARTBEAT_GPIO_PIN LL_GPIO_PIN_15 // PD.15 + #define INTMODULE_HEARTBEAT_GPIO GPIO_PIN(GPIOD, 15) // PD.15 #define INTMODULE_HEARTBEAT_EXTI_PORT LL_SYSCFG_EXTI_PORTD #define INTMODULE_HEARTBEAT_EXTI_SYS_LINE LL_SYSCFG_EXTI_LINE15 #define INTMODULE_HEARTBEAT_EXTI_LINE LL_EXTI_LINE_15 @@ -2433,12 +2249,10 @@ #define EXTI15_10_IRQ_Priority 5 #endif #elif defined(PCBX9LITE) - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph 0 + // No heartbeat #elif defined(RADIO_X7ACCESS) #define INTMODULE_HEARTBEAT - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define INTMODULE_HEARTBEAT_GPIO GPIOA - #define INTMODULE_HEARTBEAT_GPIO_PIN LL_GPIO_PIN_7 // PA.07 + #define INTMODULE_HEARTBEAT_GPIO GPIO_PIN(GPIOA, 7) // PA.07 #define INTMODULE_HEARTBEAT_EXTI_PORT LL_SYSCFG_EXTI_PORTA #define INTMODULE_HEARTBEAT_EXTI_SYS_LINE LL_SYSCFG_EXTI_LINE7 #define INTMODULE_HEARTBEAT_EXTI_LINE LL_EXTI_LINE_7 @@ -2449,9 +2263,7 @@ #endif #elif defined(RADIO_X9DP2019) #define INTMODULE_HEARTBEAT - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define INTMODULE_HEARTBEAT_GPIO GPIOB - #define INTMODULE_HEARTBEAT_GPIO_PIN LL_GPIO_PIN_1 // PB.01 + #define INTMODULE_HEARTBEAT_GPIO GPIO_PIN(GPIOB, 1) // PB.01 #define INTMODULE_HEARTBEAT_EXTI_PORT LL_SYSCFG_EXTI_PORTB #define INTMODULE_HEARTBEAT_EXTI_SYS_LINE LL_SYSCFG_EXTI_LINE1 #define INTMODULE_HEARTBEAT_EXTI_LINE LL_EXTI_LINE_1 @@ -2462,9 +2274,7 @@ #endif #elif defined(MANUFACTURER_FRSKY) #define INTMODULE_HEARTBEAT - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph RCC_AHB1Periph_GPIOC - #define INTMODULE_HEARTBEAT_GPIO GPIOC - #define INTMODULE_HEARTBEAT_GPIO_PIN LL_GPIO_PIN_7 // PC.07 + #define INTMODULE_HEARTBEAT_GPIO GPIO_PIN(GPIOC, 7) // PC.07 #define INTMODULE_HEARTBEAT_EXTI_PORT LL_SYSCFG_EXTI_PORTC #define INTMODULE_HEARTBEAT_EXTI_SYS_LINE LL_SYSCFG_EXTI_LINE7 #define INTMODULE_HEARTBEAT_EXTI_LINE LL_EXTI_LINE_7 @@ -2473,8 +2283,6 @@ #define USE_EXTI9_5_IRQ #define EXTI9_5_IRQ_Priority 5 #endif -#else - #define INTMODULE_HEARTBEAT_RCC_AHB1Periph 0 #endif // Trainer / Trainee from the module bay @@ -2484,11 +2292,10 @@ defined(RADIO_T14) #define TRAINER_MODULE_CPPM_TIMER TIM3 #define TRAINER_MODULE_CPPM_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) - #define TRAINER_MODULE_CPPM_GPIO EXTMODULE_USART_GPIO - #define TRAINER_MODULE_CPPM_GPIO_PIN EXTMODULE_RX_GPIO_PIN + #define TRAINER_MODULE_CPPM_GPIO EXTMODULE_RX_GPIO #define TRAINER_MODULE_CPPM_TIMER_Channel LL_TIM_CHANNEL_CH2 #define TRAINER_MODULE_CPPM_TIMER_IRQn TIM3_IRQn - #define TRAINER_MODULE_CPPM_GPIO_AF GPIO_AF_TIM3 + #define TRAINER_MODULE_CPPM_GPIO_AF LL_GPIO_AF_2 #if defined(PCBX9LITE) || defined(PCBXLITE) #define TRAINER_MODULE_CPPM_TIMER_IRQHandler TIM3_IRQHandler #endif @@ -2497,125 +2304,79 @@ #define TRAINER_MODULE_CPPM_TIMER TRAINER_TIMER #define TRAINER_MODULE_CPPM_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define TRAINER_MODULE_CPPM_GPIO INTMODULE_HEARTBEAT_GPIO - #define TRAINER_MODULE_CPPM_GPIO_PIN INTMODULE_HEARTBEAT_GPIO_PIN #define TRAINER_MODULE_CPPM_TIMER_Channel LL_TIM_CHANNEL_CH2 #define TRAINER_MODULE_CPPM_TIMER_IRQn TRAINER_TIMER_IRQn - #define TRAINER_MODULE_CPPM_GPIO_AF GPIO_AF_TIM3 + #define TRAINER_MODULE_CPPM_GPIO_AF GPIO_AF2 // Trainer SBUS input on heartbeat pin #define TRAINER_MODULE_SBUS_USART USART6 - #define TRAINER_MODULE_SBUS_GPIO_AF GPIO_AF_USART6 #define TRAINER_MODULE_SBUS_GPIO INTMODULE_HEARTBEAT_GPIO - #define TRAINER_MODULE_SBUS_GPIO_PIN INTMODULE_HEARTBEAT_GPIO_PIN #define TRAINER_MODULE_SBUS_DMA DMA2 #define TRAINER_MODULE_SBUS_DMA_STREAM DMA2_Stream1 #define TRAINER_MODULE_SBUS_DMA_STREAM_LL LL_DMA_STREAM_1 - #define TRAINER_MODULE_SBUS_DMA_CHANNEL DMA_Channel_5 + #define TRAINER_MODULE_SBUS_DMA_CHANNEL LL_DMA_CHANNEL_5 #else // TODO: replace SBUS trainer with S.PORT pin #endif // USB -#define USB_RCC_AHB1Periph_GPIO RCC_AHB1Periph_GPIOA -#define USB_GPIO GPIOA -#define USB_GPIO_PIN_VBUS LL_GPIO_PIN_9 // PA.09 -#define USB_GPIO_PIN_DM LL_GPIO_PIN_11 // PA.11 -#define USB_GPIO_PIN_DP LL_GPIO_PIN_12 // PA.12 +#define USB_GPIO_VBUS GPIO_PIN(GPIOA, 9) // PA.09 +#define USB_GPIO_DM GPIO_PIN(GPIOA, 11) // PA.11 +#define USB_GPIO_DP GPIO_PIN(GPIOA, 12) // PA.12 +#define USB_GPIO_AF GPIO_AF10 // BackLight #if defined(PCBX9E) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOE - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM9 #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define BACKLIGHT_TIMER TIM9 - #define BACKLIGHT_GPIO GPIOE - #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_6 // PE.06 - #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_5 // PE.05 - #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource6 - #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource5 - #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM9 - #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM9 + #define BACKLIGHT_GPIO_1 GPIO_PIN(GPIOE, 6) // PE.06 + #define BACKLIGHT_GPIO_2 GPIO_PIN(GPIOE, 5) // PE.05 + #define BACKLIGHT_GPIO_AF GPIO_AF3 #elif defined(PCBX9DP) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 - #define BACKLIGHT_RCC_APB2Periph 0 #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define BACKLIGHT_TIMER TIM4 - #define BACKLIGHT_GPIO GPIOD - #define BACKLIGHT_GPIO_PIN_1 GPIO_Pin_15 // PD.15 - #define BACKLIGHT_GPIO_PIN_2 GPIO_Pin_13 // PD.13 - #define BACKLIGHT_GPIO_PinSource_1 GPIO_PinSource15 - #define BACKLIGHT_GPIO_PinSource_2 GPIO_PinSource13 - #define BACKLIGHT_GPIO_AF_1 GPIO_AF_TIM4 - #define BACKLIGHT_GPIO_AF_2 GPIO_AF_TIM4 + #define BACKLIGHT_GPIO_1 GPIO_PIN(GPIOD, 15) // PD.15 + #define BACKLIGHT_GPIO_2 GPIO_PIN(GPIOD, 13) // PD.13 + #define BACKLIGHT_GPIO_AF GPIO_AF2 #elif defined(PCBXLITES) || defined(PCBX9LITE) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM1 #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define BACKLIGHT_TIMER TIM1 - #define BACKLIGHT_GPIO GPIOA - #define BACKLIGHT_GPIO_PIN GPIO_Pin_10 // PA.10 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource10 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM1 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 10) // PA.10 + #define BACKLIGHT_GPIO_AF GPIO_AF1 #define BACKLIGHT_CCMR2 TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_2 // Channel 3, PWM #define BACKLIGHT_CCER TIM_CCER_CC3E #define BACKLIGHT_COUNTER_REGISTER BACKLIGHT_TIMER->CCR3 #elif defined(PCBXLITE) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM1 #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define BACKLIGHT_TIMER TIM1 - #define BACKLIGHT_GPIO GPIOA - #define BACKLIGHT_GPIO_PIN GPIO_Pin_8 // PA.08 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource8 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM1 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOA, 8) // PA.08 + #define BACKLIGHT_GPIO_AF GPIO_AF1 #define BACKLIGHT_CCMR1 TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 // Channel 1, PWM #define BACKLIGHT_CCER TIM_CCER_CC1E #define BACKLIGHT_COUNTER_REGISTER BACKLIGHT_TIMER->CCR1 #elif defined(RADIO_T8) || defined(RADIO_TPROV2) || defined(RADIO_FAMILY_T20) || defined(RADIO_T14) - #define BACKLIGHT_RCC_AHB1Periph 0 - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph 0 + // No backlight: OLED display #elif defined(RADIO_COMMANDO8) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 - #define BACKLIGHT_RCC_APB2Periph 0 #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define BACKLIGHT_TIMER TIM4 - #define BACKLIGHT_GPIO GPIOD - #define BACKLIGHT_GPIO_PIN GPIO_Pin_13 // PD.13 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource13 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM4 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOD, 13) // PD.13 + #define BACKLIGHT_GPIO_AF GPIO_AF2 #define BACKLIGHT_CCMR1 TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 // Channel2, PWM #define BACKLIGHT_CCER TIM_CCER_CC2E #define BACKLIGHT_COUNTER_REGISTER BACKLIGHT_TIMER->CCR2 #elif defined(PCBX7) - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define BACKLIGHT_RCC_APB1Periph RCC_APB1Periph_TIM4 - #define BACKLIGHT_RCC_APB2Periph 0 #define BACKLIGHT_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define BACKLIGHT_TIMER TIM4 - #define BACKLIGHT_GPIO GPIOD - #define BACKLIGHT_GPIO_PIN GPIO_Pin_13 // PD.13 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource13 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM4 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOD, 13) // PD.13 + #define BACKLIGHT_GPIO_AF GPIO_AF2 #define BACKLIGHT_CCMR1 TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 // Channel2, PWM #define BACKLIGHT_CCER TIM_CCER_CC2E #define BACKLIGHT_COUNTER_REGISTER BACKLIGHT_TIMER->CCR2 #else - #define BACKLIGHT_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define BACKLIGHT_RCC_APB1Periph 0 - #define BACKLIGHT_RCC_APB2Periph RCC_APB2Periph_TIM10 #define BACKLIGHT_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define BACKLIGHT_TIMER TIM10 - #define BACKLIGHT_GPIO GPIOB - #define BACKLIGHT_GPIO_PIN GPIO_Pin_8 // PB.08 - #define BACKLIGHT_GPIO_PinSource GPIO_PinSource8 - #define BACKLIGHT_GPIO_AF GPIO_AF_TIM10 + #define BACKLIGHT_GPIO GPIO_PIN(GPIOB, 8) // PB.08 + #define BACKLIGHT_GPIO_AF GPIO_AF3 #endif -#define KEYS_BACKLIGHT_RCC_AHB1Periph 0 // LCD driver #if defined(RADIO_TX12) || defined(RADIO_TX12MK2) || defined(RADIO_BOXER) || defined(RADIO_ZORRO) || defined(RADIO_POCKET) || defined(RADIO_FAMILY_JUMPER_T12) || defined(RADIO_T8) || defined(RADIO_COMMANDO8) || defined(RADIO_TPRO) || defined(RADIO_TPROV2) || defined(RADIO_FAMILY_T20) || defined(RADIO_MT12) @@ -2629,18 +2390,12 @@ #define SSD1309_LCD #endif #if defined(PCBX9E) - #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 - #define LCD_SPI_GPIO GPIOC - #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 - #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 - #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 - #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 - #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 - #define LCD_NCS_GPIO GPIOA - #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_15 // PD.15 + #define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA1 + #define LCD_MOSI_GPIO GPIO_PIN(GPIOC, 12) // PC.12 + #define LCD_CLK_GPIO GPIO_PIN(GPIOC, 10) // PC.10 + #define LCD_A0_GPIO GPIO_PIN(GPIOC, 11) // PC.11 + #define LCD_NCS_GPIO GPIO_PIN(GPIOA, 15) // PA.15 + #define LCD_RST_GPIO GPIO_PIN(GPIOD, 15) // PD.15 #define LCD_DMA DMA1 #define LCD_DMA_Stream DMA1_Stream7 #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn @@ -2648,20 +2403,14 @@ #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 #define LCD_SPI SPI3 - #define LCD_GPIO_AF GPIO_AF_SPI3 + #define LCD_GPIO_AF GPIO_AF6 #elif defined(PCBXLITE) || defined(PCBX9LITE) - #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 - #define LCD_SPI_GPIO GPIOC - #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 - #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 - #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 - #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 - #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 - #define LCD_NCS_GPIO GPIOD - #define LCD_NCS_GPIO_PIN GPIO_Pin_3 // PD.03 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_2 // PD.02 + #define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA1 + #define LCD_MOSI_GPIO GPIO_PIN(GPIOC, 12) // PC.12 + #define LCD_CLK_GPIO GPIO_PIN(GPIOC, 10) // PC.10 + #define LCD_A0_GPIO GPIO_PIN(GPIOC, 11) // PC.11 + #define LCD_NCS_GPIO GPIO_PIN(GPIOD, 3) // PD.03 + #define LCD_RST_GPIO GPIO_PIN(GPIOD, 2) // PD.02 #define LCD_DMA DMA1 #define LCD_DMA_Stream DMA1_Stream7 #define LCD_DMA_Stream_IRQn DMA1_Stream7_IRQn @@ -2669,24 +2418,17 @@ #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 #define LCD_SPI SPI3 - #define LCD_GPIO_AF GPIO_AF_SPI3 + #define LCD_GPIO_AF GPIO_AF6 #elif defined(PCBX9DP) || defined(PCBX7) - #define LCD_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define LCD_RCC_APB1Periph RCC_APB1Periph_SPI3 - #define LCD_SPI_GPIO GPIOC - #define LCD_MOSI_GPIO_PIN GPIO_Pin_12 // PC.12 - #define LCD_MOSI_GPIO_PinSource GPIO_PinSource12 - #define LCD_CLK_GPIO_PIN GPIO_Pin_10 // PC.10 - #define LCD_CLK_GPIO_PinSource GPIO_PinSource10 - #define LCD_A0_GPIO_PIN GPIO_Pin_11 // PC.11 //MOSI - #define LCD_NCS_GPIO GPIOA - #define LCD_NCS_GPIO_PIN GPIO_Pin_15 // PA.15 + #define LCD_RCC_AHB1Periph LL_AHB1_GRP1_PERIPH_DMA1 + #define LCD_MOSI_GPIO GPIO_PIN(GPIOC, 12) // PC.12 + #define LCD_CLK_GPIO GPIO_PIN(GPIOC, 10) // PC.10 + #define LCD_A0_GPIO GPIO_PIN(GPIOC, 11) // PC.11 + #define LCD_NCS_GPIO GPIO_PIN(GPIOA, 15) // PA.15 #if defined(RADIO_FAMILY_T20) - #define LCD_RST_GPIO GPIOA - #define LCD_RST_GPIO_PIN GPIO_Pin_14 // PA.14 + #define LCD_RST_GPIO GPIO_PIN(GPIOA, 14) // PA.14 #else - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 + #define LCD_RST_GPIO GPIO_PIN(GPIOD, 12) // PD.12 #endif #define LCD_DMA DMA1 #define LCD_DMA_Stream DMA1_Stream7 @@ -2695,20 +2437,16 @@ #define LCD_DMA_FLAGS (DMA_HIFCR_CTCIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7 | DMA_HIFCR_CFEIF7) #define LCD_DMA_FLAG_INT DMA_HIFCR_CTCIF7 #define LCD_SPI SPI3 - #define LCD_GPIO_AF GPIO_AF_SPI3 + #define LCD_GPIO_AF GPIO_AF6 #else - #define LCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOD - #define LCD_RCC_APB1Periph 0 - #define LCD_SPI_GPIO GPIOD - #define LCD_MOSI_GPIO_PIN GPIO_Pin_10 // PD.10 - #define LCD_CLK_GPIO_PIN GPIO_Pin_11 // PD.11 - #define LCD_A0_GPIO_PIN GPIO_Pin_13 // PD.13 - #define LCD_NCS_GPIO GPIOD - #define LCD_NCS_GPIO_PIN GPIO_Pin_14 // PD.14 - #define LCD_RST_GPIO GPIOD - #define LCD_RST_GPIO_PIN GPIO_Pin_12 // PD.12 + #define LCD_RCC_AHB1Periph 0 + // Soft SPI: these pins are not connected to SPI periph on STM32F205 + #define LCD_MOSI_GPIO GPIO_PIN(GPIOD, 10) // PD.10 + #define LCD_CLK_GPIO GPIO_PIN(GPIOD, 11) // PD.11 + #define LCD_A0_GPIO GPIO_PIN(GPIOD, 13) // PD.13 + #define LCD_NCS_GPIO GPIO_PIN(GPIOD, 14) // PD.14 + #define LCD_RST_GPIO GPIO_PIN(GPIOD, 12) // PD.12 #endif -#define LCD_RCC_APB2Periph 0 #if defined(SSD1309_LCD) #define LCD_SPI_PRESCALER SPI_CR1_BR_1 #else @@ -2806,62 +2544,44 @@ #define SD_SPI_DMA_CHANNEL LL_DMA_CHANNEL_0 // Audio -#define AUDIO_RCC_APB1Periph (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC) -#define AUDIO_OUTPUT_GPIO GPIOA -#define AUDIO_OUTPUT_GPIO_PIN GPIO_Pin_4 // PA.04 -#define AUDIO_DMA_Stream DMA1_Stream5 -#define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn +#define AUDIO_RCC_APB1Periph LL_APB1_GRP1_PERIPH_DAC1 +#define AUDIO_OUTPUT_GPIO GPIO_PIN(GPIOA, 4) +#define AUDIO_DMA DMA1 #define AUDIO_TIM_IRQn TIM6_DAC_IRQn #define AUDIO_TIM_IRQHandler TIM6_DAC_IRQHandler +#define AUDIO_DMA_Stream DMA1_Stream5 +#define AUDIO_DMA_Stream_IRQn DMA1_Stream5_IRQn #define AUDIO_DMA_Stream_IRQHandler DMA1_Stream5_IRQHandler #define AUDIO_TIMER TIM6 -#define AUDIO_DMA DMA1 #if defined(PCBXLITES) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_DMA1) - #define JACK_DETECT_GPIO GPIOC - #define JACK_DETECT_GPIO_PIN GPIO_Pin_13 // PC.13 - #define AUDIO_SPEAKER_ENABLE_GPIO GPIOD - #define AUDIO_SPEAKER_ENABLE_GPIO_PIN GPIO_Pin_14 // PD.14 - #define HEADPHONE_TRAINER_SWITCH_GPIO GPIOD - #define HEADPHONE_TRAINER_SWITCH_GPIO_PIN GPIO_Pin_9 // PD.09 + #define JACK_DETECT_GPIO GPIO_PIN(GPIOC, 13) // PC.13 + #define AUDIO_SPEAKER_ENABLE_GPIO GPIO_PIN(GPIOD, 14) // PD.14 + #define HEADPHONE_TRAINER_SWITCH_GPIO GPIO_PIN(GPIOD, 9) // PD.09 #elif defined(RADIO_FAMILY_T20) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOG | RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) - #define AUDIO_MUTE_GPIO GPIOG - #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_4 // PG.04 + #define AUDIO_MUTE_GPIO GPIO_PIN(GPIOG, 4) // PG.04 #define AUDIO_MUTE_DELAY 500 // ms #define AUDIO_UNMUTE_DELAY 150 // ms #elif defined(RADIO_COMMANDO8) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) - #define AUDIO_MUTE_GPIO GPIOB - #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_1 // PB.01 + #define AUDIO_MUTE_GPIO GPIO_PIN(GPIOB, 1) #define AUDIO_MUTE_DELAY 500 // ms #define INVERTED_MUTE_PIN #elif defined(MANUFACTURER_RADIOMASTER) || defined(MANUFACTURER_JUMPER) || defined(RADIO_LR3PRO) - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) - #define AUDIO_MUTE_GPIO GPIOE - #define AUDIO_MUTE_GPIO_PIN GPIO_Pin_12 // PE.12 + #define AUDIO_MUTE_GPIO GPIO_PIN(GPIOE, 12) #define AUDIO_MUTE_DELAY 500 // ms -#if defined(MANUFACTURER_JUMPER) || defined(RADIO_LR3PRO) - #define AUDIO_UNMUTE_DELAY 250 // ms -#else - #define AUDIO_UNMUTE_DELAY 150 // ms -#endif -#else - #define AUDIO_RCC_AHB1Periph (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1) + #if defined(MANUFACTURER_JUMPER) || defined(RADIO_LR3PRO) + #define AUDIO_UNMUTE_DELAY 250 // ms + #else + #define AUDIO_UNMUTE_DELAY 150 // ms + #endif #endif // Haptic #if defined(PCBXLITE) || defined(PCBX9LITE) || defined(RADIO_ZORRO) || defined(RADIO_POCKET) || defined(RADIO_TX12MK2)|| defined(RADIO_BOXER) || defined(RADIO_MT12) || defined(RADIO_T20V2) || defined(RADIO_T14) #define HAPTIC_PWM - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define HAPTIC_RCC_APB1Periph RCC_APB1Periph_TIM2 - #define HAPTIC_RCC_APB2Periph 0 - #define HAPTIC_GPIO_PinSource GPIO_PinSource3 - #define HAPTIC_GPIO GPIOB - #define HAPTIC_GPIO_PIN GPIO_Pin_3 // PB.03 - #define HAPTIC_GPIO_AF GPIO_AF_TIM2 - #define HAPTIC_TIMER TIM2 + #define HAPTIC_GPIO GPIO_PIN(GPIOB, 3) // PB.03 + #define HAPTIC_GPIO_AF GPIO_AF1 + #define HAPTIC_TIMER TIM2 // Timer 2 Channel1 #define HAPTIC_TIMER_FREQ (PERI1_FREQUENCY * TIMER_MULT_APB1) #define HAPTIC_COUNTER_REGISTER HAPTIC_TIMER->CCR2 #define HAPTIC_CCMR1 TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2M_2 @@ -2869,13 +2589,8 @@ #define BACKLIGHT_BDTR TIM_BDTR_MOE #elif defined(RADIO_X9DP2019) || defined(RADIO_X7ACCESS) #define HAPTIC_PWM - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOA - #define HAPTIC_RCC_APB2Periph RCC_APB2Periph_TIM1 - #define HAPTIC_RCC_APB1Periph 0 - #define HAPTIC_GPIO_PinSource GPIO_PinSource10 - #define HAPTIC_GPIO GPIOA - #define HAPTIC_GPIO_PIN GPIO_Pin_10 // PA.10 - #define HAPTIC_GPIO_AF GPIO_AF_TIM1 + #define HAPTIC_GPIO GPIO_PIN(GPIOA, 10) // PA.10 + #define HAPTIC_GPIO_AF GPIO_AF1 #define HAPTIC_TIMER TIM1 // Timer1 Channel3 #define HAPTIC_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define HAPTIC_COUNTER_REGISTER HAPTIC_TIMER->CCR3 @@ -2883,24 +2598,15 @@ #define HAPTIC_CCER TIM_CCER_CC3E #elif defined(PCBX9E) || defined(PCBX9DP) || defined(PCBX7) #define HAPTIC_PWM - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOB - #define HAPTIC_RCC_APB2Periph RCC_APB2Periph_TIM10 - #define HAPTIC_RCC_APB1Periph 0 - #define HAPTIC_GPIO_PinSource GPIO_PinSource8 - #define HAPTIC_GPIO GPIOB - #define HAPTIC_GPIO_PIN GPIO_Pin_8 // PB.08 - #define HAPTIC_GPIO_AF GPIO_AF_TIM10 - #define HAPTIC_TIMER TIM10 + #define HAPTIC_GPIO GPIO_PIN(GPIOB, 8) // PB.08 + #define HAPTIC_GPIO_AF GPIO_AF3 + #define HAPTIC_TIMER TIM10 // Timer 10 Channel1 #define HAPTIC_TIMER_FREQ (PERI2_FREQUENCY * TIMER_MULT_APB2) #define HAPTIC_COUNTER_REGISTER HAPTIC_TIMER->CCR1 #define HAPTIC_CCMR1 TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 #define HAPTIC_CCER TIM_CCER_CC1E #else - #define HAPTIC_RCC_AHB1Periph RCC_AHB1Periph_GPIOC - #define HAPTIC_RCC_APB2Periph 0 - #define HAPTIC_RCC_APB1Periph 0 - #define HAPTIC_GPIO GPIOC - #define HAPTIC_GPIO_PIN GPIO_Pin_12 + #define HAPTIC_GPIO GPIO_PIN(GPIOC, 12) // PC.12 #endif #if defined(RADIO_BOXER) || defined(RADIO_FAMILY_T20) || defined(RADIO_X9DP2019) @@ -2908,14 +2614,8 @@ #define FLYSKY_HALL_SERIAL_USART UART4 #define FLYSKY_HALL_SERIAL_GPIO GPIOA #define FLYSKY_HALL_DMA_Channel LL_DMA_CHANNEL_4 - #define FLYSKY_HALL_SERIAL_TX_GPIO_PIN LL_GPIO_PIN_0 // PA.00 - #define FLYSKY_HALL_SERIAL_RX_GPIO_PIN LL_GPIO_PIN_1 // PA.01 - #define FLYSKY_HALL_SERIAL_GPIO_AF LL_GPIO_AF_8 - - #define FLYSKY_HALL_RCC_AHB1Periph RCC_AHB1Periph_DMA1 - #define FLYSKY_HALL_RCC_APB1Periph RCC_APB1Periph_UART4 - - #define FLYSKY_HALL_SERIAL_USART_IRQHandler UART4_IRQHandler + #define FLYSKY_HALL_SERIAL_TX_GPIO GPIO_PIN(GPIOA, 0) // PA.00 + #define FLYSKY_HALL_SERIAL_RX_GPIO GPIO_PIN(GPIOA, 1) // PA.01 #define FLYSKY_HALL_SERIAL_USART_IRQn UART4_IRQn #define FLYSKY_HALL_SERIAL_DMA DMA1 #define FLYSKY_HALL_DMA_Stream_RX LL_DMA_STREAM_2 @@ -2924,72 +2624,44 @@ // Top LCD on X9E #if defined(PCBX9E) - #define TOPLCD_RCC_AHB1Periph RCC_AHB1Periph_GPIOG - #define TOPLCD_GPIO GPIOG - #define TOPLCD_GPIO_PIN_DATA GPIO_Pin_5 - #define TOPLCD_GPIO_PIN_WR GPIO_Pin_4 - #define TOPLCD_GPIO_PIN_CS1 GPIO_Pin_3 - #define TOPLCD_GPIO_PIN_CS2 GPIO_Pin_15 - #define TOPLCD_GPIO_PIN_BL GPIO_Pin_2 + #define TOPLCD_GPIO + #define TOPLCD_GPIO_DATA GPIO_PIN(GPIOG, 5) // PG.05 + #define TOPLCD_GPIO_WR GPIO_PIN(GPIOG, 4) // PG.04 + #define TOPLCD_GPIO_CS1 GPIO_PIN(GPIOG, 3) // PG.03 + #define TOPLCD_GPIO_CS2 GPIO_PIN(GPIOG, 15) // PG.15 + #define TOPLCD_GPIO_BL GPIO_PIN(GPIOG, 2) // PG.02 #endif // Bluetooth #if defined(PCBX9E) #define STORAGE_BLUETOOTH #define BT_USART USART6 - #define BT_GPIO_AF LL_GPIO_AF_8 #define BT_USART_IRQn USART6_IRQn - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOD | RCC_AHB1Periph_GPIOE | RCC_AHB1Periph_GPIOG) - #define BT_RCC_APB1Periph 0 - #define BT_RCC_APB2Periph RCC_APB2Periph_USART6 - #define BT_USART_GPIO GPIOG - #define BT_TX_GPIO_PIN LL_GPIO_PIN_14 // PG.14 - #define BT_RX_GPIO_PIN LL_GPIO_PIN_9 // PG.09 - #define BT_EN_GPIO GPIOD - #define BT_EN_GPIO_PIN LL_GPIO_PIN_11 // PD.11 + #define BT_TX_GPIO GPIO_PIN(GPIOG, 14) // PG.14 + #define BT_RX_GPIO GPIO_PIN(GPIOG, 9) // PG.09 + #define BT_EN_GPIO GPIO_PIN(GPIOG, 11) // PD.11 // #define BT_BRTS_GPIO GPIOE - // #define BT_BRTS_GPIO_PIN GPIO_Pin_12 // PE.12 + // #define BT_BRTS_GPIO_PIN LL_GPIO_PIN_12 // PE.12 // #define BT_BCTS_GPIO GPIOG - // #define BT_BCTS_GPIO_PIN GPIO_Pin_6 // PG.06 - #define BT_TX_GPIO_PinSource GPIO_PinSource14 - #define BT_RX_GPIO_PinSource GPIO_PinSource9 - #define BT_USART_IRQHandler USART6_IRQHandler + // #define BT_BCTS_GPIO_PIN LL_GPIO_PIN_6 // PG.06 #elif defined(BLUETOOTH) #define STORAGE_BLUETOOTH - #define BT_RCC_APB1Periph RCC_APB1Periph_USART3 - #define BT_RCC_APB2Periph 0 #if defined(PCBX9DP) - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB) // RCC_AHB1Periph_DMA1 - #define BT_EN_GPIO GPIOB - #define BT_EN_GPIO_PIN LL_GPIO_PIN_2 // PB.02 + #define BT_EN_GPIO GPIO_PIN(GPIOB, 2) // PB.02 #elif defined(PCBXLITE) - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE) // RCC_AHB1Periph_DMA1 - #define BT_EN_GPIO GPIOE - #define BT_EN_GPIO_PIN LL_GPIO_PIN_15 // PE.15 + #define BT_EN_GPIO GPIO_PIN(GPIOE, 15) // PE.15 #elif defined(PCBX9LITES) - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOD) // RCC_AHB1Periph_DMA1 - #define BT_EN_GPIO GPIOD - #define BT_EN_GPIO_PIN LL_GPIO_PIN_14 // PD.14 + #define BT_EN_GPIO GPIO_PIN(GPIOD, 14) // PD.14 #elif defined(MANUFACTURER_RADIOMASTER) #if defined(RADIO_POCKET) - #define BT_EN_GPIO GPIOA - #define BT_EN_GPIO_PIN LL_GPIO_PIN_6 // PA.06 - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOA) // RCC_AHB1Periph_DMA1 - #else - // No enable port on those RM BLE port - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB) + #define BT_EN_GPIO GPIO_PIN(GPIOA, 6) // PA.06 #endif #else - #define BT_RCC_AHB1Periph (RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOE) // RCC_AHB1Periph_DMA1 - #define BT_EN_GPIO GPIOE - #define BT_EN_GPIO_PIN LL_GPIO_PIN_12 // PE.12 + #define BT_EN_GPIO GPIO_PIN(GPIOE, 12) // PE.12 #endif - #define BT_USART_GPIO GPIOB - #define BT_TX_GPIO_PIN LL_GPIO_PIN_10 // PB.10 - #define BT_RX_GPIO_PIN LL_GPIO_PIN_11 // PB.11 - #define BT_GPIO_AF LL_GPIO_AF_7 + #define BT_TX_GPIO GPIO_PIN(GPIOB, 10) // PB.10 + #define BT_RX_GPIO GPIO_PIN(GPIOB, 11) // PB.11 #define BT_USART USART3 - #define BT_USART_IRQHandler USART3_IRQHandler #define BT_USART_IRQn USART3_IRQn // #define BT_DMA_Stream_RX DMA1_Stream1 // #define BT_DMA_Channel_RX DMA_Channel_4 @@ -2998,9 +2670,6 @@ // To avoid change in modelsize, todo: remove me #define STORAGE_BLUETOOTH #endif - #define BT_RCC_AHB1Periph 0 - #define BT_RCC_APB1Periph 0 - #define BT_RCC_APB2Periph 0 #endif // Millisecond timer diff --git a/radio/src/targets/taranis/haptic_driver.cpp b/radio/src/targets/taranis/haptic_driver.cpp index edcda28f9..35bef2679 100644 --- a/radio/src/targets/taranis/haptic_driver.cpp +++ b/radio/src/targets/taranis/haptic_driver.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_timer.h" + #include "board.h" #if defined(HAPTIC_PWM) @@ -38,16 +42,9 @@ void hapticOn(uint32_t pwmPercent) void hapticInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HAPTIC_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HAPTIC_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(HAPTIC_GPIO, HAPTIC_GPIO_PinSource, HAPTIC_GPIO_AF); + gpio_init_af(HAPTIC_GPIO, HAPTIC_GPIO_AF, GPIO_PIN_SPEED_LOW); + stm32_timer_enable_clock(HAPTIC_TIMER); HAPTIC_TIMER->ARR = 100; HAPTIC_TIMER->PSC = HAPTIC_TIMER_FREQ / 10000 - 1; #if defined(HAPTIC_CCMR1) @@ -67,23 +64,17 @@ void hapticInit() // No PWM before X9D+ void hapticInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = HAPTIC_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(HAPTIC_GPIO, &GPIO_InitStructure); + gpio_init(HAPTIC_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); } void hapticOff() { - GPIO_ResetBits(HAPTIC_GPIO, HAPTIC_GPIO_PIN); + gpio_clear(HAPTIC_GPIO); } void hapticOn() { - GPIO_SetBits(HAPTIC_GPIO, HAPTIC_GPIO_PIN); + gpio_set(HAPTIC_GPIO); } #endif diff --git a/radio/src/targets/taranis/lcd_driver_aspi.cpp b/radio/src/targets/taranis/lcd_driver_aspi.cpp index 39b3b3951..7d100c4d2 100644 --- a/radio/src/targets/taranis/lcd_driver_aspi.cpp +++ b/radio/src/targets/taranis/lcd_driver_aspi.cpp @@ -19,6 +19,9 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" #include "lcd.h" #include "hal/abnormal_reboot.h" @@ -34,20 +37,20 @@ bool lcdInitFinished = false; void lcdInitFinish(); -#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN -#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN +#define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) +#define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) -#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN -#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN +#define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) +#define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) -#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN -#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN +#define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) +#define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) -#define LCD_CLK_HIGH() LCD_SPI_GPIO->BSRRL = LCD_CLK_GPIO_PIN -#define LCD_CLK_LOW() LCD_SPI_GPIO->BSRRH = LCD_CLK_GPIO_PIN +#define LCD_CLK_HIGH() gpio_set(LCD_CLK_GPIO) +#define LCD_CLK_LOW() gpio_clear(LCD_CLK_GPIO) -#define LCD_MOSI_HIGH() LCD_SPI_GPIO->BSRRL = LCD_MOSI_GPIO_PIN -#define LCD_MOSI_LOW() LCD_SPI_GPIO->BSRRH = LCD_MOSI_GPIO_PIN +#define LCD_MOSI_HIGH() gpio_set(LCD_MOSI_GPIO) +#define LCD_MOSI_LOW() gpio_clear(LCD_MOSI_GPIO) void lcdWriteCommand(uint8_t command) { @@ -198,29 +201,14 @@ void lcdRefresh() void lcdHardwareInit() { - GPIO_InitTypeDef GPIO_InitStructure; - - // Configure CLK, MOSI and A0 pins in output push-pull mode - GPIO_InitStructure.GPIO_Pin = LCD_MOSI_GPIO_PIN | LCD_CLK_GPIO_PIN | LCD_A0_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); + gpio_init(LCD_MOSI_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_CLK_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_A0_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(LCD_NCS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); LCD_NCS_HIGH(); - // Configure NCS pin in output push-pull mode with PULLUP - GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); - - // Configure RST pin in output push-pull mode with PULLUP - GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; - GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); + gpio_init(LCD_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); } /* @@ -233,14 +221,14 @@ void lcdOff() LCD Sleep mode is also good for draining capacitors and enables us to re-init LCD without any delay */ - lcdWriteCommand(0xAE); //LCD sleep - delay_ms(3); //wait for caps to drain + lcdWriteCommand(0xAE); // LCD sleep + delay_ms(3); // wait for caps to drain } void lcdReset() { LCD_RST_LOW(); - delay_ms(1); // only 3 us needed according to data-sheet, we use 1 ms + delay_ms(1); // only 3 us needed according to data-sheet, we use 1 ms LCD_RST_HIGH(); } diff --git a/radio/src/targets/taranis/lcd_driver_spi.cpp b/radio/src/targets/taranis/lcd_driver_spi.cpp index 7f213d96e..4b16796f2 100644 --- a/radio/src/targets/taranis/lcd_driver_spi.cpp +++ b/radio/src/targets/taranis/lcd_driver_spi.cpp @@ -19,6 +19,10 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" + #include "board.h" #include "debug.h" #include "lcd.h" @@ -39,14 +43,14 @@ #define RESET_WAIT_DELAY_MS 300 // Wait time after LCD reset before first command #define WAIT_FOR_DMA_END() do { } while (lcd_busy) -#define LCD_NCS_HIGH() LCD_NCS_GPIO->BSRRL = LCD_NCS_GPIO_PIN -#define LCD_NCS_LOW() LCD_NCS_GPIO->BSRRH = LCD_NCS_GPIO_PIN +#define LCD_NCS_HIGH() gpio_set(LCD_NCS_GPIO) +#define LCD_NCS_LOW() gpio_clear(LCD_NCS_GPIO) -#define LCD_A0_HIGH() LCD_SPI_GPIO->BSRRL = LCD_A0_GPIO_PIN -#define LCD_A0_LOW() LCD_SPI_GPIO->BSRRH = LCD_A0_GPIO_PIN +#define LCD_A0_HIGH() gpio_set(LCD_A0_GPIO) +#define LCD_A0_LOW() gpio_clear(LCD_A0_GPIO) -#define LCD_RST_HIGH() LCD_RST_GPIO->BSRRL = LCD_RST_GPIO_PIN -#define LCD_RST_LOW() LCD_RST_GPIO->BSRRH = LCD_RST_GPIO_PIN +#define LCD_RST_HIGH() gpio_set(LCD_RST_GPIO) +#define LCD_RST_LOW() gpio_clear(LCD_RST_GPIO) bool lcdInitFinished = false; void lcdInitFinish(); @@ -68,7 +72,9 @@ void lcdWriteCommand(uint8_t byte) void lcdHardwareInit() { - GPIO_InitTypeDef GPIO_InitStructure; + stm32_spi_enable_clock(LCD_SPI); + gpio_init_af(LCD_MOSI_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_HIGH); + gpio_init_af(LCD_CLK_GPIO, LCD_GPIO_AF, GPIO_PIN_SPEED_HIGH); // APB1 clock / 2 = 133nS per clock LCD_SPI->CR1 = 0; // Clear any mode error @@ -77,28 +83,11 @@ void lcdHardwareInit() LCD_SPI->CR1 |= SPI_CR1_MSTR; // Make sure in case SSM/SSI needed to be set first LCD_SPI->CR1 |= SPI_CR1_SPE; + gpio_init(LCD_NCS_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); LCD_NCS_HIGH(); - GPIO_InitStructure.GPIO_Pin = LCD_NCS_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; - GPIO_Init(LCD_NCS_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_RST_GPIO_PIN; - GPIO_Init(LCD_RST_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_A0_GPIO_PIN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_InitStructure.GPIO_Pin = LCD_CLK_GPIO_PIN | LCD_MOSI_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; - GPIO_Init(LCD_SPI_GPIO, &GPIO_InitStructure); - - GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_MOSI_GPIO_PinSource, LCD_GPIO_AF); - GPIO_PinAFConfig(LCD_SPI_GPIO, LCD_CLK_GPIO_PinSource, LCD_GPIO_AF); + gpio_init(LCD_RST_GPIO, GPIO_OUT, GPIO_PIN_SPEED_MEDIUM); + gpio_init(LCD_A0_GPIO, GPIO_OUT, GPIO_PIN_SPEED_HIGH); LCD_DMA_Stream->CR &= ~DMA_SxCR_EN; // Disable DMA LCD_DMA->HIFCR = LCD_DMA_FLAGS; // Write ones to clear bits diff --git a/radio/src/targets/taranis/led_driver.cpp b/radio/src/targets/taranis/led_driver.cpp index 4090c7d7a..d39da4c93 100644 --- a/radio/src/targets/taranis/led_driver.cpp +++ b/radio/src/targets/taranis/led_driver.cpp @@ -19,73 +19,65 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" +#if defined(FUNCTION_SWITCHES) +static const uint32_t fsLeds[] = {FSLED_GPIO_PIN_1, FSLED_GPIO_PIN_2, + FSLED_GPIO_PIN_3, FSLED_GPIO_PIN_4, + FSLED_GPIO_PIN_5, FSLED_GPIO_PIN_6}; +#endif + void ledInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - #if defined(LED_GREEN_GPIO) - GPIO_InitStructure.GPIO_Pin = LED_GREEN_GPIO_PIN; - GPIO_Init(LED_GREEN_GPIO, &GPIO_InitStructure); + gpio_init(LED_GREEN_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif #if defined(LED_RED_GPIO) - GPIO_InitStructure.GPIO_Pin = LED_RED_GPIO_PIN; - GPIO_Init(LED_RED_GPIO, &GPIO_InitStructure); + gpio_init(LED_RED_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif #if defined(LED_BLUE_GPIO) - GPIO_InitStructure.GPIO_Pin = LED_BLUE_GPIO_PIN; - GPIO_Init(LED_BLUE_GPIO, &GPIO_InitStructure); + gpio_init(LED_BLUE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW); #endif #if defined(FUNCTION_SWITCHES) - RCC_AHB1PeriphClockCmd(FS_RCC_AHB1Periph, ENABLE); - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_InitStructure.GPIO_Pin = FSLED_GPIO_PIN_1 | FSLED_GPIO_PIN_2 | FSLED_GPIO_PIN_3 | FSLED_GPIO_PIN_4 | FSLED_GPIO_PIN_5 | FSLED_GPIO_PIN_6; - GPIO_Init(FSLED_GPIO, &GPIO_InitStructure); + for (int i = 0; i < DIM(fsLeds); i++) { + gpio_init(fsLeds[i], GPIO_OUT, GPIO_PIN_SPEED_LOW); + } #endif } #if defined(FUNCTION_SWITCHES) -constexpr uint32_t fsLeds[] = {FSLED_GPIO_PIN_1, FSLED_GPIO_PIN_2, - FSLED_GPIO_PIN_3, FSLED_GPIO_PIN_4, - FSLED_GPIO_PIN_5, FSLED_GPIO_PIN_6}; - void fsLedOff(uint8_t index) { - GPIO_FSLED_GPIO_OFF(FSLED_GPIO, fsLeds[index]); + gpio_clear(fsLeds[index]); } void fsLedOn(uint8_t index) { - GPIO_FSLED_GPIO_ON(FSLED_GPIO, fsLeds[index]); + gpio_set(fsLeds[index]); } bool getFSLedState(uint8_t index) { - return (FSLED_GPIO->ODR & fsLeds[index]); + return gpio_read(fsLeds[index]) ? true : false; } #endif void ledOff() { #if defined(LED_RED_GPIO) - GPIO_LED_GPIO_OFF(LED_RED_GPIO, LED_RED_GPIO_PIN); + GPIO_LED_GPIO_OFF(LED_RED_GPIO); #endif #if defined(LED_BLUE_GPIO) - GPIO_LED_GPIO_OFF(LED_BLUE_GPIO, LED_BLUE_GPIO_PIN); + GPIO_LED_GPIO_OFF(LED_BLUE_GPIO); #endif #if defined(LED_GREEN_GPIO) - GPIO_LED_GPIO_OFF(LED_GREEN_GPIO, LED_GREEN_GPIO_PIN); + GPIO_LED_GPIO_OFF(LED_GREEN_GPIO); #endif } @@ -93,7 +85,7 @@ void ledRed() { ledOff(); #if defined(LED_RED_GPIO) - GPIO_LED_GPIO_ON(LED_RED_GPIO, LED_RED_GPIO_PIN); + GPIO_LED_GPIO_ON(LED_RED_GPIO); #endif } @@ -101,7 +93,7 @@ void ledGreen() { ledOff(); #if defined(LED_GREEN_GPIO) - GPIO_LED_GPIO_ON(LED_GREEN_GPIO, LED_GREEN_GPIO_PIN); + GPIO_LED_GPIO_ON(LED_GREEN_GPIO); #endif } @@ -109,6 +101,6 @@ void ledBlue() { ledOff(); #if defined(LED_BLUE_GPIO) - GPIO_LED_GPIO_ON(LED_BLUE_GPIO, LED_BLUE_GPIO_PIN); + GPIO_LED_GPIO_ON(LED_BLUE_GPIO); #endif } diff --git a/radio/src/targets/taranis/top_lcd_driver.cpp b/radio/src/targets/taranis/top_lcd_driver.cpp index 2e08dd88d..ca949de5e 100644 --- a/radio/src/targets/taranis/top_lcd_driver.cpp +++ b/radio/src/targets/taranis/top_lcd_driver.cpp @@ -19,22 +19,25 @@ * GNU General Public License for more details. */ -#include +#include "hal/gpio.h" +#include "stm32_gpio.h" #include "opentx.h" #include "board.h" #include "lcd.h" -#define CS1_HIGH() TOPLCD_GPIO->BSRRL = TOPLCD_GPIO_PIN_CS1 -#define CS1_LOW() TOPLCD_GPIO->BSRRH = TOPLCD_GPIO_PIN_CS1 -#define CS2_HIGH() TOPLCD_GPIO->BSRRL = TOPLCD_GPIO_PIN_CS2 -#define CS2_LOW() TOPLCD_GPIO->BSRRH = TOPLCD_GPIO_PIN_CS2 -#define WR_HIGH() TOPLCD_GPIO->BSRRL = TOPLCD_GPIO_PIN_WR -#define WR_LOW() TOPLCD_GPIO->BSRRH = TOPLCD_GPIO_PIN_WR -#define DATA_HIGH() TOPLCD_GPIO->BSRRL = TOPLCD_GPIO_PIN_DATA -#define DATA_LOW() TOPLCD_GPIO->BSRRH = TOPLCD_GPIO_PIN_DATA -#define BL_ON() TOPLCD_GPIO->BSRRL = TOPLCD_GPIO_PIN_BL -#define BL_OFF() TOPLCD_GPIO->BSRRH = TOPLCD_GPIO_PIN_BL +#include + +#define CS1_HIGH() gpio_set(TOPLCD_GPIO_CS1) +#define CS1_LOW() gpio_clear(TOPLCD_GPIO_CS1) +#define CS2_HIGH() gpio_set(TOPLCD_GPIO_CS2) +#define CS2_LOW() gpio_clear(TOPLCD_GPIO_CS2) +#define WR_HIGH() gpio_set(TOPLCD_GPIO_WR) +#define WR_LOW() gpio_clear(TOPLCD_GPIO_WR) +#define DATA_HIGH() gpio_set(TOPLCD_GPIO_DATA) +#define DATA_LOW() gpio_clear(TOPLCD_GPIO_DATA) +#define BL_ON() gpio_set(TOPLCD_GPIO_BL) +#define BL_OFF() gpio_clear(TOPLCD_GPIO_BL) const uint8_t TimeLCDsegs[] = { 0xAF, 0x06, 0x6D, 0x4F, 0xC6, 0xCB, 0xEB, 0x0E, 0xEF, 0xCF }; const uint8_t RssiLCDsegs[] = { 0xFA, 0x60, 0xBC, 0xF4, 0x66, 0xD6, 0xDE, 0x70, 0xFE, 0xF6 }; @@ -224,14 +227,11 @@ extern "C" void TIM8_BRK_TIM12_IRQHandler() void toplcdInit() { - RCC_AHB1PeriphClockCmd(TOPLCD_RCC_AHB1Periph, ENABLE); - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = TOPLCD_GPIO_PIN_DATA | TOPLCD_GPIO_PIN_WR |TOPLCD_GPIO_PIN_BL|TOPLCD_GPIO_PIN_CS1|TOPLCD_GPIO_PIN_CS2; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(TOPLCD_GPIO, &GPIO_InitStructure); + gpio_init(TOPLCD_GPIO_DATA, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TOPLCD_GPIO_WR, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TOPLCD_GPIO_CS1, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TOPLCD_GPIO_CS2, GPIO_OUT, GPIO_PIN_SPEED_LOW); + gpio_init(TOPLCD_GPIO_BL, GPIO_OUT, GPIO_PIN_SPEED_LOW); BL_ON(); diff --git a/radio/src/targets/taranis/usb_charger_driver.cpp b/radio/src/targets/taranis/usb_charger_driver.cpp index 1fdae5d34..fd919d83b 100644 --- a/radio/src/targets/taranis/usb_charger_driver.cpp +++ b/radio/src/targets/taranis/usb_charger_driver.cpp @@ -19,25 +19,18 @@ * GNU General Public License for more details. */ +#include "hal/gpio.h" +#include "stm32_gpio.h" + #include "board.h" #include "hal/usb_driver.h" void usbChargerInit() { - GPIO_InitTypeDef GPIO_InitStructure; - GPIO_InitStructure.GPIO_Pin = USB_CHARGER_GPIO_PIN; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; - GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; - GPIO_Init(USB_CHARGER_GPIO, &GPIO_InitStructure); + gpio_init(USB_CHARGER_GPIO, GPIO_IN_PU, GPIO_PIN_SPEED_LOW); } bool usbChargerLed() { -#if defined(SIMU) - return true; -#else - return (GPIO_ReadInputDataBit(USB_CHARGER_GPIO, USB_CHARGER_GPIO_PIN) == Bit_RESET && usbPlugged()); -#endif + return (!gpio_read(USB_CHARGER_GPIO) && usbPlugged()); } diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h deleted file mode 100644 index 0381f4e00..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h +++ /dev/null @@ -1,6967 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx.h - * @author MCD Application Team - * @version V1.1.3 - * @date 05-March-2012 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F2xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx - * @{ - */ - -#ifndef __STM32F2xx_H -#define __STM32F2xx_H - -#define assert_param(xx) - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined (STM32F2XX) - #define STM32F2XX -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined (STM32F2XX) - #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" -#endif - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER*/ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F2XX Standard Peripherals Library version number V1.1.3 - */ -#define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ -#define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ -#define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F2XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M3 Processor and Core Peripherals - */ -#define __CM3_REV 0x0200 /*!< Core Revision r2p0 */ -#define __MPU_PRESENT 1 /*!< STM32F2XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F2XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * @brief STM32F2XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80 /*!< Hash and Rng global interrupt */ -} IRQn_Type; - -/** - * @} - */ - -#include "../../../../Include/core_cm3.h" -#include "system_stm32f2xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; /* added for STM32F2xx */ - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; /* added for STM32F2xx */ - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register, Address offset: 0x14 */ -} FLASH_TypeDef; - -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< Reserved, 0x28 */ - uint32_t RESERVED2; /*!< Reserved, 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - uint32_t RESERVED3; /*!< Reserved, 0x38 */ - uint32_t RESERVED4; /*!< Reserved, 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - uint32_t RESERVED5; /*!< Reserved, 0x44 */ - uint32_t RESERVED6; /*!< Reserved, 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[51]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1C0 */ -} HASH_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */ -#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ - -#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ - -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#if !defined WIN32 && defined __GNUC__ -#define CRC ((CRC_TypeDef *) CRC_BASE) -#endif -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!*/ - -#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F2XX_H -#define __SYSTEM_STM32F2XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F2xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F2xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F2XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 7245c4f12..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,35 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010 ARM Limited. All rights reserved. -* -* $Date: 11. November 2010 -* $Revision: V1.0.2 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Version 1.0.2 2010/11/11 -* Documentation updated. -* -* Version 1.0.1 2010/10/05 -* Production release and review comments incorporated. -* -* Version 1.0.0 2010/09/20 -* Production release and review comments incorporated. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern uint16_t armBitRevTable[256]; -extern q15_t armRecipTableQ15[64]; -extern q31_t armRecipTableQ31[64]; -extern const q31_t realCoefAQ31[1024]; -extern const q31_t realCoefBQ31[1024]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index ffa03b6fd..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7051 +0,0 @@ -/* ---------------------------------------------------------------------- - * Copyright (C) 2010 ARM Limited. All rights reserved. - * - * $Date: 15. July 2011 - * $Revision: V1.0.10 - * - * Project: CMSIS DSP Library - * Title: arm_math.h - * - * Description: Public header file for CMSIS DSP Library - * - * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 - * - * Version 1.0.10 2011/7/15 - * Big Endian support added and Merged M0 and M3/M4 Source code. - * - * Version 1.0.3 2010/11/29 - * Re-organized the CMSIS folders and updated documentation. - * - * Version 1.0.2 2010/11/11 - * Documentation updated. - * - * Version 1.0.1 2010/10/05 - * Production release and review comments incorporated. - * - * Version 1.0.0 2010/09/20 - * Production release and review comments incorporated. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of modules each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Processor Support - * - * The library is completely written in C and is fully CMSIS compliant. - * High performance is achieved through maximum use of Cortex-M4 intrinsics. - * - * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor, - * with the DSP intrinsics being emulated through software. - * - * - * Toolchain Support - * - * The library has been developed and tested with MDK-ARM version 4.21. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Using the Library - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 depending on the target processor in the application. - * - * Examples - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Building the Library - * - * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder. - * - arm_cortexM0b_math.uvproj - * - arm_cortexM0l_math.uvproj - * - arm_cortexM3b_math.uvproj - * - arm_cortexM3l_math.uvproj - * - arm_cortexM4b_math.uvproj - * - arm_cortexM4l_math.uvproj - * - arm_cortexM4bf_math.uvproj - * - arm_cortexM4lf_math.uvproj - * - * Each library project have differant pre-processor macros. - * - * ARM_MATH_CMx: - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target. - * - * ARM_MATH_BIG_ENDIAN: - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * ARM_MATH_MATRIX_CHECK: - * Define macro for checking on the input and output sizes of matrices - * - * ARM_MATH_ROUNDING: - * Define macro for rounding on support functions - * - * __FPU_PRESENT: - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - * - * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above. - * - * Copyright Notice - * - * Copyright (C) 2010 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the #define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" - #include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#define PI 3.14159265358979f - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x800000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#define __SIMD32(addr) (*(int32_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ(q31_t data); - - - static __INLINE uint32_t __CLZ(q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return(count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0 */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (char) x; - s = (char) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + - clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (short) x; - s = (short) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) - - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t)(((short) x * (short) (y >> 16)) + - ((short) (x >> 16) * (short) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((short) (x >> 16) * (short) (y)) + - ((short) x * (short) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) (y >> 16)) + - ((short) x * (short) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((short) (x >> 16) * (short) y)) + - ((short) x * (short) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - - -#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t *pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t *pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t *pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - #ifdef ARM_MATH_CM0 - q15_t A1; - q15_t A2; - #else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ - #endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; - float32_t x1; - float32_t xSpacing; - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - - /** - * @brief Processing function for the Q15 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Initialization function for the Q15 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 CFFT/CIFFT. - * @param[in] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Initialization function for the Q31 CFFT/CIFFT. - * @param[in,out] *S points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point CFFT/CIFFT. - * @param[in] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place. - * @return none. - */ - - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Initialization function for the floating-point CFFT/CIFFT. - * @param[in,out] *S points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLen length of the FFT. - * @param[in] ifftFlag flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value. - */ - - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - - - /*---------------------------------------------------------------------- - * Internal functions prototypes FFT function - ----------------------------------------------------------------------*/ - - /** - * @brief Core function for the floating-point CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to the twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier); - - /** - * @brief Core function for the floating-point CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @param[in] onebyfftLen value of 1/fftLen. - * @return none. - */ - - void arm_radix4_butterfly_inverse_f32( - float32_t * pSrc, - uint16_t fftLen, - float32_t * pCoef, - uint16_t twidCoefModifier, - float32_t onebyfftLen); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of floating-point data type. - * @param[in] fftSize length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table. - * @param[in] *pBitRevTab points to the bit reversal table. - * @return none. - */ - - void arm_bitreversal_f32( - float32_t *pSrc, - uint16_t fftSize, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q31 CFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q31( - q31_t *pSrc, - uint32_t fftLen, - q31_t *pCoef, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q31 CIFFT butterfly process. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q31( - q31_t * pSrc, - uint32_t fftLen, - q31_t * pCoef, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q31 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q31( - q31_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Core function for the Q15 CFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief Core function for the Q15 CIFFT butterfly process. - * @param[in, out] *pSrc16 points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] *pCoef16 points to twiddle coefficient buffer. - * @param[in] twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. - * @return none. - */ - - void arm_radix4_butterfly_inverse_q15( - q15_t *pSrc16, - uint32_t fftLen, - q15_t *pCoef16, - uint32_t twidCoefModifier); - - /** - * @brief In-place bit reversal function. - * @param[in, out] *pSrc points to the in-place buffer of Q15 data type. - * @param[in] fftLen length of the FFT. - * @param[in] bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table - * @param[in] *pBitRevTab points to bit reversal table. - * @return none. - */ - - void arm_bitreversal_q15( - q15_t * pSrc, - uint32_t fftLen, - uint16_t bitRevFactor, - uint16_t *pBitRevTab); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - /** - * @brief Processing function for the Q15 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Initialization function for the Q15 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of the Q15 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the Q31 RFFT/RIFFT. - * @param[in] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Initialization function for the Q31 RFFT/RIFFT. - * @param[in, out] *S points to an instance of the Q31 RFFT/RIFFT structure. - * @param[in, out] *S_CFFT points to an instance of the Q31 CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Initialization function for the floating-point RFFT/RIFFT. - * @param[in,out] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in,out] *S_CFFT points to an instance of the floating-point CFFT/CIFFT structure. - * @param[in] fftLenReal length of the FFT. - * @param[in] ifftFlagR flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. - * @param[in] bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value. - */ - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - /** - * @brief Processing function for the floating-point RFFT/RIFFT. - * @param[in] *S points to an instance of the floating-point RFFT/RIFFT structure. - * @param[in] *pSrc points to the input buffer. - * @param[out] *pDst points to the output buffer. - * @return none. - */ - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t *pkCoeffs, - float32_t *pvCoeffs, - float32_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t *pkCoeffs, - q31_t *pvCoeffs, - q31_t *pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t *pkCoeffs, - q15_t *pvCoeffs, - q15_t *pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t *pCoeffs, - q31_t *pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t *pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t *pSinVal, - float32_t *pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t *pSinVal, - q31_t *pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - - /* Implementation of PID controller */ - - #ifdef ARM_MATH_CM0 - - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0 )* in ; - - #else - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - #endif - - #ifdef ARM_MATH_CM0 - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0] ; - acc += (q31_t) S->A2 * S->state[1] ; - - #else - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc); - - #endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (x - S->x1) / xSpacing; - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if(i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues-1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i +1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0)/(x1-x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, - q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - - if(index >= (nValues - 1)) - { - return(pYData[nValues - 1]); - } - else if(index < 0) - { - return(pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, float32_t *pOut) - { - if(in > 0) - { - -// #if __FPU_USED - #if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); - #else - *pOut = sqrtf(in); - #endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, q31_t *pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, q15_t *pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0 || yIndex > ( S->numCols-1)) - { - return(0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex-1) * S->numCols ; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex-1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows-1) || cI < 0 || cI > ( S->numCols-1)) - { - return(0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index 9d7a19f9a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,665 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - - -/** \mainpage CMSIS Cortex-M0 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP - and not via processor. Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } - else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ - else { - return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index 5d39ef86c..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1240 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - - -/** \mainpage CMSIS Cortex-M3 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#else - #define __INLINE - #define __DSB() - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks */ -#endif - -#include /*!< standard types definitions */ -#include "core_cmInstr.h" /*!< Core Instruction Access */ -#include "core_cmFunc.h" /*!< Core Function Access */ - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index bf022ba67..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1378 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - - -/** \mainpage CMSIS Cortex-M4 - - This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. - It consists of: - - - Cortex-M Core Register Definitions - - Cortex-M functions - - Cortex-M instructions - - Cortex-M SIMD instructions - - The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease - access to the Cortex-M Core - */ - -/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions - CMSIS violates following MISRA-C2004 Rules: - - - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \defgroup CMSIS_core_definitions CMSIS Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core - - Cortex-M core Revision Number - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - /* add preprocessor checks to define __FPU_USED */ - #define __FPU_USED 0 -#endif - -#include /*!< standard types definitions */ -#include /*!< Core Instruction Access */ -#include /*!< Core Function Access */ -#include /*!< Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - -/*@} end of group CMSIS_core_definitions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** \defgroup CMSIS_core_register CMSIS Core Register - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE CMSIS Core - Type definitions for the Cortex-M Core Registers - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC CMSIS NVIC - Type definitions for the Cortex-M NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB CMSIS SCB - Type definitions for the Cortex-M System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB - Type definitions for the Cortex-M System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick CMSIS SysTick - Type definitions for the Cortex-M System Timer Registers - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM CMSIS ITM - Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */ -#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU CMSIS MPU - Type definitions for the Cortex-M Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU CMSIS FPU - Type definitions for the Cortex-M Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug CMSIS Core Debug - Type definitions for the Cortex-M Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions - @{ - */ - -/** \brief Set Priority Grouping - - This function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - This function gets the priority grouping from NVIC Interrupt Controller. - Priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - - \return Priority grouping field - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - This function enables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to enable - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - This function disables a device specific interrupt in the NVIC interrupt controller. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the external interrupt to disable - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - This function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Number of the interrupt for get pending - \return 0 Interrupt status is not pending - \return 1 Interrupt status is pending - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - This function sets the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for set pending - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - This function clears the pending bit for the specified interrupt. - The interrupt number cannot be a negative value. - - \param [in] IRQn Number of the interrupt for clear pending - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - This function reads the active register in NVIC and returns the active bit. - \param [in] IRQn Number of the interrupt for get active - \return 0 Interrupt status is not active - \return 1 Interrupt status is active - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - This function sets the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - Note: The priority cannot be set for every core interrupt. - - \param [in] IRQn Number of the interrupt for set priority - \param [in] priority Priority to set - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - This function reads the priority for the specified interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - The returned priority value is automatically aligned to the implemented - priority bits of the microcontroller. - - \param [in] IRQn Number of the interrupt for get priority - \return Interrupt Priority - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - This function encodes the priority for an interrupt with the given priority group, - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The returned priority value can be used for NVIC_SetPriority(...) function - - \param [in] PriorityGroup Used priority group - \param [in] PreemptPriority Preemptive priority value (starting from 0) - \param [in] SubPriority Sub priority value (starting from 0) - \return Encoded priority for the interrupt - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - This function decodes an interrupt priority value with the given priority group to - preemptive priority value and sub priority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - - The priority value can be retrieved with NVIC_GetPriority(...) function - - \param [in] Priority Priority value - \param [in] PriorityGroup Used priority group - \param [out] pPreemptPriority Preemptive priority value (starting from 0) - \param [out] pSubPriority Sub priority value (starting from 0) - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - This function initiate a system reset request to reset the MCU. - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - This function initialises the system tick timer and its interrupt and start the system tick timer. - Counter is in free running mode to generate periodical interrupts. - - \param [in] ticks Number of ticks between two interrupts - \return 0 Function succeeded - \return 1 Function failed - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** \brief ITM Send Character - - This function transmits a character via the ITM channel 0. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \param [in] ch Character to transmit - \return Character to transmit - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - This function inputs a character via external variable ITM_RxBuffer. - It just returns when no debugger is connected that has booked the output. - It is blocking when a debugger is connected, but the previous character send is not transmitted. - - \return Received character - \return -1 No character received - */ -static __INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - This function checks external variable ITM_RxBuffer whether a character is available or not. - It returns '1' if a character is available and '0' if no character is available. - - \return 0 No character available - \return 1 Character available - */ -static __INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ - -#ifdef __cplusplus -} -#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index e7b676522..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,701 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2010-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/ -/* intrinsic __SADD8 see intrinsics.h */ -/* intrinsic __QADD8 see intrinsics.h */ -/* intrinsic __SHADD8 see intrinsics.h */ -/* intrinsic __UADD8 see intrinsics.h */ -/* intrinsic __UQADD8 see intrinsics.h */ -/* intrinsic __UHADD8 see intrinsics.h */ -/* intrinsic __SSUB8 see intrinsics.h */ -/* intrinsic __QSUB8 see intrinsics.h */ -/* intrinsic __SHSUB8 see intrinsics.h */ -/* intrinsic __USUB8 see intrinsics.h */ -/* intrinsic __UQSUB8 see intrinsics.h */ -/* intrinsic __UHSUB8 see intrinsics.h */ -/* intrinsic __SADD16 see intrinsics.h */ -/* intrinsic __QADD16 see intrinsics.h */ -/* intrinsic __SHADD16 see intrinsics.h */ -/* intrinsic __UADD16 see intrinsics.h */ -/* intrinsic __UQADD16 see intrinsics.h */ -/* intrinsic __UHADD16 see intrinsics.h */ -/* intrinsic __SSUB16 see intrinsics.h */ -/* intrinsic __QSUB16 see intrinsics.h */ -/* intrinsic __SHSUB16 see intrinsics.h */ -/* intrinsic __USUB16 see intrinsics.h */ -/* intrinsic __UQSUB16 see intrinsics.h */ -/* intrinsic __UHSUB16 see intrinsics.h */ -/* intrinsic __SASX see intrinsics.h */ -/* intrinsic __QASX see intrinsics.h */ -/* intrinsic __SHASX see intrinsics.h */ -/* intrinsic __UASX see intrinsics.h */ -/* intrinsic __UQASX see intrinsics.h */ -/* intrinsic __UHASX see intrinsics.h */ -/* intrinsic __SSAX see intrinsics.h */ -/* intrinsic __QSAX see intrinsics.h */ -/* intrinsic __SHSAX see intrinsics.h */ -/* intrinsic __USAX see intrinsics.h */ -/* intrinsic __UQSAX see intrinsics.h */ -/* intrinsic __UHSAX see intrinsics.h */ -/* intrinsic __USAD8 see intrinsics.h */ -/* intrinsic __USADA8 see intrinsics.h */ -/* intrinsic __SSAT16 see intrinsics.h */ -/* intrinsic __USAT16 see intrinsics.h */ -/* intrinsic __UXTB16 see intrinsics.h */ -/* intrinsic __SXTB16 see intrinsics.h */ -/* intrinsic __UXTAB16 see intrinsics.h */ -/* intrinsic __SXTAB16 see intrinsics.h */ -/* intrinsic __SMUAD see intrinsics.h */ -/* intrinsic __SMUADX see intrinsics.h */ -/* intrinsic __SMLAD see intrinsics.h */ -/* intrinsic __SMLADX see intrinsics.h */ -/* intrinsic __SMLALD see intrinsics.h */ -/* intrinsic __SMLALDX see intrinsics.h */ -/* intrinsic __SMUSD see intrinsics.h */ -/* intrinsic __SMUSDX see intrinsics.h */ -/* intrinsic __SMLSD see intrinsics.h */ -/* intrinsic __SMLSDX see intrinsics.h */ -/* intrinsic __SMLSLD see intrinsics.h */ -/* intrinsic __SMLSLDX see intrinsics.h */ -/* intrinsic __SEL see intrinsics.h */ -/* intrinsic __QADD see intrinsics.h */ -/* intrinsic __QSUB see intrinsics.h */ -/* intrinsic __PKHBT see intrinsics.h */ -/* intrinsic __PKHTB see intrinsics.h */ - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 88819f9dd..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,609 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V2.10 - * @date 26. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - - -/** \brief Get ISPR Register - - This function returns the content of the ISPR Register. - - \return ISPR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -#endif /* __CORE_CMFUNC_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index 78d2ef80b..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,585 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V2.10 - * @date 19. July 2011 - * - * @note - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -static __INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __rbit - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - -#endif /* (__CORTEX_M >= 0x03) */ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -#include - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) -{ - __ASM volatile ("isb"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) -{ - __ASM volatile ("dsb"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) -{ - __ASM volatile ("dmb"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) -{ - uint32_t result; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -/** \brief LDR Exclusive (8 bit) - - This function performs a exclusive LDR command for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint8_t result; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (16 bit) - - This function performs a exclusive LDR command for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint16_t result; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief LDR Exclusive (32 bit) - - This function performs a exclusive LDR command for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function performs a exclusive STR command for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function performs a exclusive STR command for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function performs a exclusive STR command for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) -{ - __ASM volatile ("clrex"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) -{ - uint8_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h deleted file mode 100644 index bd5e4f52e..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f2xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h deleted file mode 100644 index 4dae8c173..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h +++ /dev/null @@ -1,649 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_adc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_ADC_H -#define __STM32F2xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h deleted file mode 100644 index ba287d77a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_can.h +++ /dev/null @@ -1,644 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_can.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CAN_H -#define __STM32F2xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h deleted file mode 100644 index 3361bbccb..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_crc.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_crc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CRC_H -#define __STM32F2xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h deleted file mode 100644 index e0b45016f..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_cryp.h +++ /dev/null @@ -1,344 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the Cryptographic - * processor(CRYP) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_CRYP_H -#define __STM32F2xx_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CRYP Init structure definition - */ -typedef struct -{ - uint16_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a - value of @ref CRYP_Algorithm_Direction */ - uint16_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key. This parameter can be - a value of @ref CRYP_Algorithm_Mode */ - uint16_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit-string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint16_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit - key length. This parameter can be a value of - @ref CRYP_Key_Size_for_AES_only */ -}CRYP_InitTypeDef; - -/** - * @brief CRYP Key(s) structure definition - */ -typedef struct -{ - uint32_t CRYP_Key0Left; /*!< Key 0 Left */ - uint32_t CRYP_Key0Right; /*!< Key 0 Right */ - uint32_t CRYP_Key1Left; /*!< Key 1 left */ - uint32_t CRYP_Key1Right; /*!< Key 1 Right */ - uint32_t CRYP_Key2Left; /*!< Key 2 left */ - uint32_t CRYP_Key2Right; /*!< Key 2 Right */ - uint32_t CRYP_Key3Left; /*!< Key 3 left */ - uint32_t CRYP_Key3Right; /*!< Key 3 Right */ -}CRYP_KeyInitTypeDef; -/** - * @brief CRYP Initialization Vectors (IV) structure definition - */ -typedef struct -{ - uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ - uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ - uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ - uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ -}CRYP_IVInitTypeDef; - -/** - * @brief CRYP context swapping structure definition - */ -typedef struct -{ - /*!< Configuration */ - uint32_t CR_bits9to2; - /*!< KEY */ - uint32_t CRYP_IV0LR; - uint32_t CRYP_IV0RR; - uint32_t CRYP_IV1LR; - uint32_t CRYP_IV1RR; - /*!< IV */ - uint32_t CRYP_K0LR; - uint32_t CRYP_K0RR; - uint32_t CRYP_K1LR; - uint32_t CRYP_K1RR; - uint32_t CRYP_K2LR; - uint32_t CRYP_K2RR; - uint32_t CRYP_K3LR; - uint32_t CRYP_K3RR; -}CRYP_Context; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants - * @{ - */ - -/** @defgroup CRYP_Algorithm_Direction - * @{ - */ -#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) -#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) -#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ - ((ALGODIR) == CRYP_AlgoDir_Decrypt)) - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode - * @{ - */ - -/*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint16_t)0x0000) -#define CRYP_AlgoMode_TDES_CBC ((uint16_t)0x0008) - -/*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint16_t)0x0010) -#define CRYP_AlgoMode_DES_CBC ((uint16_t)0x0018) - -/*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint16_t)0x0020) -#define CRYP_AlgoMode_AES_CBC ((uint16_t)0x0028) -#define CRYP_AlgoMode_AES_CTR ((uint16_t)0x0030) -#define CRYP_AlgoMode_AES_Key ((uint16_t)0x0038) - -#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key)) -/** - * @} - */ - -/** @defgroup CRYP_Data_Type - * @{ - */ -#define CRYP_DataType_32b ((uint16_t)0x0000) -#define CRYP_DataType_16b ((uint16_t)0x0040) -#define CRYP_DataType_8b ((uint16_t)0x0080) -#define CRYP_DataType_1b ((uint16_t)0x00C0) -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ - ((DATATYPE) == CRYP_DataType_16b)|| \ - ((DATATYPE) == CRYP_DataType_8b)|| \ - ((DATATYPE) == CRYP_DataType_1b)) -/** - * @} - */ - -/** @defgroup CRYP_Key_Size_for_AES_only - * @{ - */ -#define CRYP_KeySize_128b ((uint16_t)0x0000) -#define CRYP_KeySize_192b ((uint16_t)0x0100) -#define CRYP_KeySize_256b ((uint16_t)0x0200) -#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ - ((KEYSIZE) == CRYP_KeySize_192b)|| \ - ((KEYSIZE) == CRYP_KeySize_256b)) -/** - * @} - */ - -/** @defgroup CRYP_flags_definition - * @{ - */ -#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently - processing a block of data - or a key preparation (for - AES decryption). */ -#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ -#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ -#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ -#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw - interrupt status */ -#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ -#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw - interrupt status */ - -#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ - ((FLAG) == CRYP_FLAG_IFNF) || \ - ((FLAG) == CRYP_FLAG_OFNE) || \ - ((FLAG) == CRYP_FLAG_OFFU) || \ - ((FLAG) == CRYP_FLAG_BUSY) || \ - ((FLAG) == CRYP_FLAG_OUTRIS)|| \ - ((FLAG) == CRYP_FLAG_INRIS)) -/** - * @} - */ - -/** @defgroup CRYP_interrupts_definition - * @{ - */ -#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ -#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ -#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) - -/** - * @} - */ - -/** @defgroup CRYP_Encryption_Decryption_modes_definition - * @{ - */ -#define MODE_ENCRYPT ((uint8_t)0x01) -#define MODE_DECRYPT ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup CRYP_DMA_transfer_requests - * @{ - */ -#define CRYP_DMAReq_DataIN ((uint8_t)0x01) -#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) -#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CRYP configuration to the default reset state ****/ -void CRYP_DeInit(void); - -/* CRYP Initialization and Configuration functions ****************************/ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_Cmd(FunctionalState NewState); - -/* CRYP Data processing functions *********************************************/ -void CRYP_DataIn(uint32_t Data); -uint32_t CRYP_DataOut(void); -void CRYP_FIFOFlush(void); - -/* CRYP Context swapping functions ********************************************/ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); - -/* CRYP's DMA interface function **********************************************/ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); - -/* High Level AES functions **************************************************/ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CBC(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CTR(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level TDES functions **************************************************/ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, - uint8_t Key[24], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_TDES_CBC(uint8_t Mode, - uint8_t Key[24], - uint8_t InitVectors[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level DES functions **************************************************/ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, - uint8_t Key[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_DES_CBC(uint8_t Mode, - uint8_t Key[8], - uint8_t InitVectors[8], - uint8_t *Input,uint32_t Ilength, - uint8_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_CRYP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h deleted file mode 100644 index 2a0afc323..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dac.h +++ /dev/null @@ -1,304 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dac.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DAC_H -#define __STM32F2xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h deleted file mode 100644 index 415a5b91e..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dbgmcu.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DBGMCU_H -#define __STM32F2xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h deleted file mode 100644 index d6baafd1c..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dcmi.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dcmi.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DCMI firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DCMI_H -#define __STM32F2xx_DCMI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DCMI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. - This parameter can be a value of @ref DCMI_Capture_Mode */ - - uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ -} DCMI_InitTypeDef; - -/** - * @brief DCMI CROP Init structure definition - */ -typedef struct -{ - uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture - will start. This parameter can be a value between 0x00 and 0x1FFF */ - - uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting - point on the same line. - This parameter can be a value between 0x00 and 0x3FFF */ -} DCMI_CROPInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants - * @{ - */ - -/** @defgroup DCMI_Capture_Mode - * @{ - */ -#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ - ((MODE) == DCMI_CaptureMode_SnapShot)) -/** - * @} - */ - - -/** @defgroup DCMI_Synchronization_Mode - * @{ - */ -#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ - ((MODE) == DCMI_SynchroMode_Embedded)) -/** - * @} - */ - - -/** @defgroup DCMI_PIXCK_Polarity - * @{ - */ -#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ - ((POLARITY) == DCMI_PCKPolarity_Rising)) -/** - * @} - */ - - -/** @defgroup DCMI_VSYNC_Polarity - * @{ - */ -#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ -#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ - ((POLARITY) == DCMI_VSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_HSYNC_Polarity - * @{ - */ -#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ - ((POLARITY) == DCMI_HSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_Capture_Rate - * @{ - */ -#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ -#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ -#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ - ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ - ((RATE) == DCMI_CaptureRate_1of4_Frame)) -/** - * @} - */ - - -/** @defgroup DCMI_Extended_Data_Mode - * @{ - */ -#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ - ((DATA) == DCMI_ExtendedDataMode_10b) ||\ - ((DATA) == DCMI_ExtendedDataMode_12b) ||\ - ((DATA) == DCMI_ExtendedDataMode_14b)) -/** - * @} - */ - - -/** @defgroup DCMI_interrupt_sources - * @{ - */ -#define DCMI_IT_FRAME ((uint16_t)0x0001) -#define DCMI_IT_OVF ((uint16_t)0x0002) -#define DCMI_IT_ERR ((uint16_t)0x0004) -#define DCMI_IT_VSYNC ((uint16_t)0x0008) -#define DCMI_IT_LINE ((uint16_t)0x0010) -#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) -#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ - ((IT) == DCMI_IT_OVF) || \ - ((IT) == DCMI_IT_ERR) || \ - ((IT) == DCMI_IT_VSYNC) || \ - ((IT) == DCMI_IT_LINE)) -/** - * @} - */ - - -/** @defgroup DCMI_Flags - * @{ - */ -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) -#define DCMI_FLAG_FNE ((uint16_t)0x2004) -/** - * @brief DCMI RISR register - */ -#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) -#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) -#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) -#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) -#define DCMI_FLAG_LINERI ((uint16_t)0x0010) -/** - * @brief DCMI MISR register - */ -#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) -#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ - ((FLAG) == DCMI_FLAG_VSYNC) || \ - ((FLAG) == DCMI_FLAG_FNE) || \ - ((FLAG) == DCMI_FLAG_FRAMERI) || \ - ((FLAG) == DCMI_FLAG_OVFRI) || \ - ((FLAG) == DCMI_FLAG_ERRRI) || \ - ((FLAG) == DCMI_FLAG_VSYNCRI) || \ - ((FLAG) == DCMI_FLAG_LINERI) || \ - ((FLAG) == DCMI_FLAG_FRAMEMI) || \ - ((FLAG) == DCMI_FLAG_OVFMI) || \ - ((FLAG) == DCMI_FLAG_ERRMI) || \ - ((FLAG) == DCMI_FLAG_VSYNCMI) || \ - ((FLAG) == DCMI_FLAG_LINEMI)) - -#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DCMI configuration to the default reset state ****/ -void DCMI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); -void DCMI_CROPCmd(FunctionalState NewState); -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); -void DCMI_JPEGCmd(FunctionalState NewState); - -/* Image capture functions ****************************************************/ -void DCMI_Cmd(FunctionalState NewState); -void DCMI_CaptureCmd(FunctionalState NewState); -uint32_t DCMI_ReadData(void); - -/* Interrupts and flags management functions **********************************/ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); -void DCMI_ClearFlag(uint16_t DCMI_FLAG); -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); -void DCMI_ClearITPendingBit(uint16_t DCMI_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DCMI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h deleted file mode 100644 index fb27ff06c..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h +++ /dev/null @@ -1,609 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dma.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_DMA_H -#define __STM32F2xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h deleted file mode 100644 index f9f0a9179..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_exti.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_EXTI_H -#define __STM32F2xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h deleted file mode 100644 index 32b165133..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h +++ /dev/null @@ -1,340 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_flash.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_FLASH_H -#define __STM32F2xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F))) -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[8:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 3 (Bits[24:16]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h deleted file mode 100644 index 102b1cfd0..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_fsmc.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_fsmc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_FSMC_H -#define __STM32F2xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command deassertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h deleted file mode 100644 index a284e856a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h +++ /dev/null @@ -1,411 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_GPIO_H -#define __STM32F2xx_GPIO_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Speed_2MHz = 0x00, /*!< Low speed */ - GPIO_Speed_25MHz = 0x01, /*!< Medium speed */ - GPIO_Speed_50MHz = 0x02, /*!< Fast speed */ - GPIO_Speed_100MHz = 0x03 /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */ -}GPIOSpeed_TypeDef; -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \ - ((SPEED) == GPIO_Speed_50MHz)|| ((SPEED) == GPIO_Speed_100MHz)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00)) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_FSMC) || \ - ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO) || \ - ((AF) == GPIO_AF_DCMI) || ((AF) == GPIO_AF_EVENTOUT)) -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h deleted file mode 100644 index 2e5039e30..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_hash.h +++ /dev/null @@ -1,250 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the HASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_HASH_H -#define __STM32F2xx_HASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HASH Init structure definition - */ -typedef struct -{ - uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value - of @ref HASH_Algo_Selection */ - uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value - of @ref HASH_processor_Algorithm_Mode */ - uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit-string. This parameter can be a value of - @ref HASH_Data_Type */ - uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter - can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ -}HASH_InitTypeDef; - -/** - * @brief HASH message digest result structure definition - */ -typedef struct -{ - uint32_t Data[5]; /*!< Message digest result : 5x 32bit words for SHA1 or - 4x 32bit words for MD5 */ -} HASH_MsgDigest; - -/** - * @brief HASH context swapping structure definition - */ -typedef struct -{ - uint32_t HASH_IMR; - uint32_t HASH_STR; - uint32_t HASH_CR; - uint32_t HASH_CSR[51]; -}HASH_Context; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection - * @{ - */ -#define HASH_AlgoSelection_SHA1 ((uint16_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_MD5 ((uint16_t)0x0080) /*!< HASH function is MD5 */ - -#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) -/** - * @} - */ - -/** @defgroup HASH_processor_Algorithm_Mode - * @{ - */ -#define HASH_AlgoMode_HASH ((uint16_t)0x0000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC ((uint16_t)0x0040) /*!< Algorithm is HMAC */ - -#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ - ((ALGOMODE) == HASH_AlgoMode_HMAC)) -/** - * @} - */ - -/** @defgroup HASH_Data_Type - * @{ - */ -#define HASH_DataType_32b ((uint16_t)0x0000) -#define HASH_DataType_16b ((uint16_t)0x0010) -#define HASH_DataType_8b ((uint16_t)0x0020) -#define HASH_DataType_1b ((uint16_t)0x0030) - -#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ - ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b)|| \ - ((DATATYPE) == HASH_DataType_1b)) -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode - * @{ - */ -#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */ - -#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) -/** - * @} - */ - -/** @defgroup Number_of_valid_bits_in_last_word_of_the_message - * @{ - */ -#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition - * @{ - */ -#define HASH_IT_DINI ((uint8_t)0x01) /*!< A new block can be entered into the input buffer (DIN)*/ -#define HASH_IT_DCI ((uint8_t)0x02) /*!< Digest calculation complete */ - -#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) - -/** - * @} - */ - -/** @defgroup HASH_flags_definition - * @{ - */ -#define HASH_FLAG_DINIS ((uint16_t)0x0001) /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/ -#define HASH_FLAG_DCIS ((uint16_t)0x0002) /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS ((uint16_t)0x0004) /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY ((uint16_t)0x0008) /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE ((uint16_t)0x1000) /*!< DIN not empty : The input buffer contains at least one word of data */ - -#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS) || \ - ((FLAG) == HASH_FLAG_DMAS) || \ - ((FLAG) == HASH_FLAG_BUSY) || \ - ((FLAG) == HASH_FLAG_DINNE)) - -#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the HASH configuration to the default reset state ****/ -void HASH_DeInit(void); - -/* HASH Configuration function ************************************************/ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); -void HASH_Reset(void); - -/* HASH Message Digest generation functions ***********************************/ -void HASH_DataIn(uint32_t Data); -uint8_t HASH_GetInFIFOWordsNbr(void); -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); -void HASH_StartDigest(void); -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); - -/* HASH Context swapping functions ********************************************/ -void HASH_SaveContext(HASH_Context* HASH_ContextSave); -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); - -/* HASH's DMA interface function **********************************************/ -void HASH_DMACmd(FunctionalState NewState); - -/* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG); -void HASH_ClearFlag(uint16_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint8_t HASH_IT); -void HASH_ClearITPendingBit(uint8_t HASH_IT); - -/* High Level SHA1 functions **************************************************/ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); -ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[20]); - -/* High Level MD5 functions ***************************************************/ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); -ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_HASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h deleted file mode 100644 index afff514c7..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h +++ /dev/null @@ -1,698 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_i2c.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_I2C_H -#define __STM32F2xx_I2C_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ - -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0033). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h deleted file mode 100644 index 731ca2f64..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_iwdg.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_iwdg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_IWDG_H -#define __STM32F2xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h deleted file mode 100644 index 33b6d686b..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h +++ /dev/null @@ -1,166 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_pwr.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_PWR_H -#define __STM32F2xx_PWR_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ - -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ - -#define PWR_Regulator_ON ((uint32_t)0x00000000) -#define PWR_Regulator_LowPower PWR_CR_LPDS -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ - ((REGULATOR) == PWR_Regulator_LowPower)) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ - -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) - -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ - -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR)) - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -void PWR_WakeUpPinCmd(FunctionalState NewState); - -/* Backup Regulator configuration functions ***********************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); - -/* FLASH Power Down configuration functions ***********************************/ -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h deleted file mode 100644 index ece02058c..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h +++ /dev/null @@ -1,515 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RCC_H -#define __STM32F2xx_RCC_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_CSS ((uint8_t)0x80) -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); - -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -void RCC_PLLCmd(FunctionalState NewState); -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -void RCC_PLLI2SCmd(FunctionalState NewState); - -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h deleted file mode 100644 index 72f33cb24..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rng.h +++ /dev/null @@ -1,120 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rng.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RNG_H -#define __STM32F2xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h deleted file mode 100644 index 31d4cd811..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h +++ /dev/null @@ -1,650 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rtc.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_RTC_H -#define __STM32F2xx_RTC_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x1FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x1FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_PC13 ((uint32_t)0x00000000) -#define RTC_TamperPin_PI8 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \ - ((PIN) == RTC_TamperPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFC0DF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Coarse Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h deleted file mode 100644 index dbe2e3d3a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_sdio.h +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_sdio.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SDIO_H -#define __STM32F2xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h deleted file mode 100644 index 2d9571f03..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h +++ /dev/null @@ -1,526 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SPI_H -#define __STM32F2xx_SPI_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /*__STM32F2xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h deleted file mode 100644 index de6f3a00f..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_syscfg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_SYSCFG_H -#define __STM32F2xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI)) -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) - -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h deleted file mode 100644 index 2c48f2ad1..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h +++ /dev/null @@ -1,1150 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_tim.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_TIM_H -#define __STM32F2xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F2xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h deleted file mode 100644 index 663f380be..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h +++ /dev/null @@ -1,429 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_usart.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_USART_H -#define __STM32F2xx_USART_H - -#if defined(__cplusplus) && !defined(SIMU) - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "../../CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#if defined(__cplusplus) && !defined(SIMU) -} -#endif - -#endif /* __STM32F2xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h deleted file mode 100644 index 4cf5f03f2..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_wwdg.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_wwdg.h - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F2xx_WWDG_H -#define __STM32F2xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation function ***************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F2xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c deleted file mode 100644 index 7d011629b..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M3 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c deleted file mode 100644 index 37ead2645..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_adc.c +++ /dev/null @@ -1,1748 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_adc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * - Initialization and Configuration (in addition to ADC multi mode - * selection) - * - Analog Watchdog configuration - * - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT - * management - * - Regular Channels Configuration - * - Regular Channels DMA Configuration - * - Injected channels Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the ADC interface clock using - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - * - * 2. ADC pins configuration - * - Enable the clock for the ADC GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Configure these ADC pins in analog mode using GPIO_Init(); - * - * 3. Configure the ADC Prescaler, conversion resolution and data - * alignment using the ADC_Init() function. - * 4. Activate the ADC peripheral using ADC_Cmd() function. - * - * Regular channels group configuration - * ==================================== - * - To configure the ADC regular channels group features, use - * ADC_Init() and ADC_RegularChannelConfig() functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To configurate and activate the Discontinuous mode, use the - * ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - * - To read the ADC converted values, use the ADC_GetConversionValue() - * function. - * - * Multi mode ADCs Regular channels configuration - * =============================================== - * - Refer to "Regular channels group configuration" description to - * configure the ADC1, ADC2 and ADC3 regular channels. - * - Select the Multi mode ADC regular channels features (dual or - * triple mode) using ADC_CommonInit() function and configure - * the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - * functions. - * - Read the ADCs converted values using the - * ADC_GetMultiModeConversionValue() function. - * - * DMA for Regular channels group features configuration - * ====================================================== - * - To enable the DMA mode for regular channels group, use the - * ADC_DMACmd() function. - * - To enable the generation of DMA requests continuously at the end - * of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - * function. - * - * Injected channels group configuration - * ===================================== - * - To configure the ADC Injected channels group features, use - * ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - * functions. - * - To activate the continuous mode, use the ADC_continuousModeCmd() - * function. - * - To activate the Injected Discontinuous mode, use the - * ADC_InjectedDiscModeCmd() function. - * - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - * function. - * - To read the ADC converted values, use the ADC_GetInjectedConversionValue() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_adc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to: - - Initialize and configure the ADC Prescaler - - ADC Conversion Resolution (12bit..6bit) - - Scan Conversion Mode (multichannels or one channel) for regular group - - ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - - External trigger Edge and source of regular group, - - Converted data alignment (left or right) - - The number of ADC conversions that will be done using the sequencer for - regular channel group - - Multi ADC mode selection - - Direct memory access mode selection for multi ADC mode - - Delay between 2 sampling phases (used in dual or triple interleaved modes) - - Enable or disable the ADC peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - Analog Watchdog configuration functions - =============================================================================== - - This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - A typical configuration Analog Watchdog is done following these steps : - 1. the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - 2. The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - 3. The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - Temperature Sensor, Vrefint and VBAT management functions - =============================================================================== - - This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and the - Vbat sources. - - A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - 1. Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - 2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - 3. Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - A typical configuration to get the VBAT channel voltage is done following - these steps : - 1. Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - 2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - 3. Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - Regular Channels Configuration functions - =============================================================================== - - This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - 1. Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - - Configure the rank in the regular group sequencer for each channel - - Configure the sampling time for each channel - - select the conversion Trigger for regular channels - - select the desired EOC event behavior configuration - - Activate the continuous Mode (*) - - Activate the Discontinuous Mode - Please Note that the following features for regular channels are configurated - using the ADC_Init() function : - - scan mode activation - - continuous mode activation (**) - - External trigger source - - External trigger edge - - number of conversion in the regular channels group sequencer. - - @note (*) and (**) are performing the same configuration - - 2. Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - Regular Channels DMA Configuration functions - =============================================================================== - - This section provides functions allowing to configure the DMA for ADC regular - channels. - Since converted regular channel values are stored into a unique data register, - it is useful to use DMA for conversion of more than one regular channel. This - avoids the loss of the data already stored in the ADC Data register. - - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - - Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - - Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - - No new DMA request is issued to the DMA controller (feature DISABLED) - - Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - Injected channels Configuration functions - =============================================================================== - - This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - 1. Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - - Configure the rank in the injected group sequencer for each channel - - Configure the sampling time for each channel - - Activate the Auto injected Mode - - Activate the Discontinuous Mode - - scan mode activation - - External/software trigger source - - External trigger edge - - injected channels sequencer. - - 2. Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the ADC Interrupts and - to get the status and clear flags and Interrupts pending bits. - - Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into - 3 groups: - - I. Flags and Interrupts for ADC regular channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - 2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending - on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of: - ==> a regular CHANNEL conversion - ==> sequence of regular GROUP conversions . - - 3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL - conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event. - 2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of - conversion event. - - - II. Flags and Interrupts for ADC Injected channels - ================================================= - Flags : - ---------- - 1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at - the end of injected GROUP conversion - - 2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - - Interrupts : - ------------ - 1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of - conversion event. - - III. General Flags and Interrupts for the ADC - ================================================= - Flags : - ---------- - 1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - - Interrupts : - ------------ - 1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - The user should identify which mode will be used in his application to manage - the ADC controller events: Polling mode or Interrupt mode. - - In the Polling Mode it is advised to use the following functions: - - ADC_GetFlagStatus() : to check if flags events occur. - - ADC_ClearFlag() : to clear the flags events. - - In the Interrupt Mode it is advised to use the following functions: - - ADC_ITConfig() : to enable or disable the interrupt source. - - ADC_GetITStatus() : to check if Interrupt occurs. - - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c deleted file mode 100644 index 433a9476a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_can.c +++ /dev/null @@ -1,1704 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_can.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * - Initialization and Configuration - * - CAN Frames Transmission - * - CAN Frames Reception - * - Operation modes switch - * - Error management - * - Interrupts and flags - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - - * 1. Enable the CAN controller interface clock using - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - * and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - * @note In case you are using CAN2 only, you have to enable the CAN1 clock. - * - * 2. CAN pins configuration - * - Enable the clock for the CAN GPIOs using the following function: - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - Connect the involved CAN pins to AF9 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - * - Configure these CAN pins in alternate function mode by calling - * the function GPIO_Init(); - * - * 3. Initialise and configure the CAN using CAN_Init() and - * CAN_FilterInit() functions. - * - * 4. Transmit the desired CAN frame using CAN_Transmit() function. - * - * 5. Check the transmission of a CAN frame using CAN_TransmitStatus() - * function. - * - * 6. Cancel the transmission of a CAN frame using CAN_CancelTransmit() - * function. - * - * 7. Receive a CAN frame using CAN_Recieve() function. - * - * 8. Release the receive FIFOs using CAN_FIFORelease() function. - * - * 9. Return the number of pending received frames using - * CAN_MessagePending() function. - * - * 10. To control CAN events you can use one of the following two methods: - * - Check on CAN flags using the CAN_GetFlagStatus() function. - * - Use CAN interrupts through the function CAN_ITConfig() at - * initialization phase and CAN_GetITStatus() function into - * interrupt routines to check if the event has occurred or not. - * After checking on a flag you should clear it using CAN_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using CAN_ClearITPendingBit() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_can.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number - of time quanta to perform resynchronization, the number of time quanta in - Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - - Configures the CAN reception filter. - - Select the start bank filter for slave CAN. - - Enables or disables the Debug Freeze mode for CAN - - Enables or disables the CAN Time Trigger Operation communication mode - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} - -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - CAN Frames Transmission functions - =============================================================================== - This section provides functions allowing to - - Initiate and transmit a CAN frame message (if there is an empty mailbox). - - Check the transmission status of a CAN Frame - - Cancel a transmit request - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - CAN Frames Reception functions - =============================================================================== - This section provides functions allowing to - - Receive a correct CAN frame - - Release a specified receive FIFO (2 FIFOs are available) - - Return the number of the pending received CAN frames - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - CAN Operation modes functions - =============================================================================== - This section provides functions allowing to select the CAN Operation modes - - sleep mode - - normal mode - - initialization mode - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - CAN Bus Error management functions - =============================================================================== - This section provides functions allowing to - - Return the CANx's last error code (LEC) - - Return the CANx Receive Error Counter (REC) - - Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - - @note If TEC is greater than 255, The CAN is in bus-off state. - @note if REC or TEC are greater than 96, an Error warning flag occurs. - @note if REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1 or 2 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CAN Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The CAN provides 14 Interrupts sources and 15 Flags: - - =============== - Flags : - =============== - The 15 flags can be divided on 4 groups: - - A. Transmit Flags - ----------------------- - CAN_FLAG_RQCP0, - CAN_FLAG_RQCP1, - CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when when the last request (transmit or abort) has - been performed. - - B. Receive Flags - ----------------------- - - CAN_FLAG_FMP0, - CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - CAN_FLAG_FF0, - CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - CAN_FLAG_FOV0 - CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - C. Operating Mode Flags - ----------------------- - CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. - - CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. - - D. Error Flags - ----------------------- - CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - - CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. - - CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - =============== - Interrupts : - =============== - The 14 interrupts can be divided on 4 groups: - - A. Transmit interrupt - ----------------------- - CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - B. Receive Interrupts - ----------------------- - CAN_IT_FMP0, - CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending when - messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. - - CAN_IT_FF0, - CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending when - three messages are stored in the selected FIFO. - - CAN_IT_FOV0, - CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending when - a new message has been received and passed the filter - while the FIFO was full. - - C. Operating Mode Interrupts - ------------------------------- - CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware was - in Sleep mode. - - CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - D. Error Interrupts - ----------------------- - CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). - - CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). - - CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. - - CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. - - - Managing the CAN controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CAN controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CAN_GetFlagStatus() : to check if flags events occur. - - CAN_ClearFlag() : to clear the flags events. - - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CAN_ITConfig() : to enable or disable the interrupt source. - - CAN_GetITStatus() : to check if Interrupt occurs. - - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag). - @note This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c deleted file mode 100644 index 427377058..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_crc.c +++ /dev/null @@ -1,133 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_crc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_crc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c deleted file mode 100644 index d97a8c16c..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp.c +++ /dev/null @@ -1,856 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Cryptographic processor (CRYP) peripheral: - * - Initialization and Configuration functions - * - Data treatment functions - * - Context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if - * needed CRYP_IVInit(). - * - * 3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - * - * 4. Enable the CRYP controller using the CRYP_Cmd() function. - * - * 5. If using DMA for Data input and output transfer, - * Activate the needed DMA Requests using CRYP_DMACmd() function - - * 6. If DMA is not used for data transfer, use CRYP_DataIn() and - * CRYP_DataOut() functions to enter data to IN FIFO and get result - * from OUT FIFO. - * - * 7. To control CRYP events you can use one of the following - * two methods: - * - Check on CRYP flags using the CRYP_GetFlagStatus() function. - * - Use CRYP interrupts through the function CRYP_ITConfig() at - * initialization phase and CRYP_GetITStatus() function into - * interrupt routines in processing phase. - * - * 8. Save and restore Cryptographic processor context using - * CRYP_SaveContext() and CRYP_RestoreContext() functions. - * - * - * =================================================================== - * Procedure to perform an encryption or a decryption - * =================================================================== - * - * Initialization - * =============== - * 1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and - * CRYP_IVInit functions: - * - Configure the key size (128-, 192- or 256-bit, in the AES only) - * - Enter the symmetric key - * - Configure the data type - * - In case of decryption in AES-ECB or AES-CBC, you must prepare - * the key: configure the key preparation mode. Then Enable the CRYP - * peripheral using CRYP_Cmd() function: the BUSY flag is set. - * Wait until BUSY flag is reset : the key is prepared for decryption - * - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - * AES in ECB/CBC/CTR) - * - Configure the direction (encryption/decryption). - * - Write the initialization vectors (in CBC or CTR modes only) - * - * 2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - * - * - * Basic Processing mode (polling mode) - * ==================================== - * 1. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 2. Write the first blocks in the input FIFO (2 to 8 words) using - * CRYP_DataIn() function. - * - * 3. Repeat the following sequence until the complete message has been - * processed: - * - * a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - * function), then read the OUT-FIFO using CRYP_DataOut() function - * (1 block or until the FIFO is empty) - * - * b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - * function then write the IN FIFO using CRYP_DataIn() function - * (1 block or until the FIFO is full) - * - * 4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - * both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - * reset). You can disable the peripheral using CRYP_Cmd() function. - * - * Interrupts Processing mode - * =========================== - * In this mode, Processing is done when the data are transferred by the - * CPU during interrupts. - * - * 1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using - * CRYP_ITConfig() function. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * - * 3. In the CRYP_IT_INI interrupt handler : load the input message into the - * IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - * time, or load data until the IN FIFO is full. When the last word of - * the message has been entered into the IN FIFO, disable the CRYP_IT_INI - * interrupt (using CRYP_ITConfig() function). - * - * 4. In the CRYP_IT_OUTI interrupt handler : read the output message from - * the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - * 4 words) at a time or read data until the FIFO is empty. - * When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - * empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - * You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - * function) and you can disable the peripheral using CRYP_Cmd() function. - * - * DMA Processing mode - * ==================== - * In this mode, Processing is done when the DMA is used to transfer the - * data from/to the memory. - * - * 1. Configure the DMA controller to transfer the input data from the - * memory using DMA_Init() function. - * The transfer length is the length of the message. - * As message padding is not managed by the peripheral, the message - * length must be an entire number of blocks. The data are transferred - * in burst mode. The burst length is 4 words in the AES and 2 or 4 - * words in the DES/TDES. The DMA should be configured to set an - * interrupt on transfer completion of the output data to indicate that - * the processing is finished. - * Refer to DMA peripheral driver for more details. - * - * 2. Enable the cryptographic processor using CRYP_Cmd() function. - * Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - * using CRYP_DMACmd() function. - * - * 3. All the transfers and processing are managed by the DMA and the - * cryptographic processor. The DMA transfer complete interrupt indicates - * that the processing is complete. Both FIFOs are normally empty and - * CRYP_FLAG_BUSY flag is reset. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define FLAG_MASK ((uint8_t)0x20) -#define MAX_TIMEOUT ((uint16_t)0xFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the cryptographic Processor using CRYP_Init() function - - Encrypt or Decrypt - - mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key - - DataType : 32-bit data, 16-bit data, bit data or bit-string - - Key Size (only in AES modes) - - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - - Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - - Enable or disable the CRYP Processor using CRYP_Cmd() function - - -@endverbatim - * @{ - */ -/** - * @brief Deinitializes the CRYP peripheral registers to their default reset values - * @param None - * @retval None - */ -void CRYP_DeInit(void) -{ - /* Enable CRYP reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); - - /* Release CRYP from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); -} - -/** - * @brief Initializes the CRYP peripheral according to the specified parameters - * in the CRYP_InitStruct. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains - * the configuration information for the CRYP peripheral. - * @retval None - */ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); - assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); - assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); - - /* Select Algorithm mode*/ - CRYP->CR &= ~CRYP_CR_ALGOMODE; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; - - /* Select dataType */ - CRYP->CR &= ~CRYP_CR_DATATYPE; - CRYP->CR |= CRYP_InitStruct->CRYP_DataType; - - /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) || - (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key)) - { - assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); - CRYP->CR &= ~CRYP_CR_KEYSIZE; - CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be - configured once the key has - been prepared */ - } - - /* Select data Direction */ - CRYP->CR &= ~CRYP_CR_ALGODIR; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; -} - -/** - * @brief Fills each CRYP_InitStruct member with its default value. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Initialize the CRYP_AlgoDir member */ - CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - - /* initialize the CRYP_AlgoMode member */ - CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - - /* initialize the CRYP_DataType member */ - CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; - - /* Initialize the CRYP_KeySize member */ - CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; -} - -/** - * @brief Initializes the CRYP Keys according to the specified parameters in - * the CRYP_KeyInitStruct. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - /* Key Initialisation */ - CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; -} - -/** - * @brief Fills each CRYP_KeyInitStruct member with its default value. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure - * which will be initialized. - * @retval None - */ -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - CRYP_KeyInitStruct->CRYP_Key0Left = 0; - CRYP_KeyInitStruct->CRYP_Key0Right = 0; - CRYP_KeyInitStruct->CRYP_Key1Left = 0; - CRYP_KeyInitStruct->CRYP_Key1Right = 0; - CRYP_KeyInitStruct->CRYP_Key2Left = 0; - CRYP_KeyInitStruct->CRYP_Key2Right = 0; - CRYP_KeyInitStruct->CRYP_Key3Left = 0; - CRYP_KeyInitStruct->CRYP_Key3Right = 0; -} -/** - * @brief Initializes the CRYP Initialization Vectors(IV) according to the - * specified parameters in the CRYP_IVInitStruct. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains - * the configuration information for the CRYP Initialization Vectors(IV). - * @retval None - */ -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; - CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; - CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; - CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; -} - -/** - * @brief Fills each CRYP_IVInitStruct member with its default value. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization - * Vectors(IV) structure which will be initialized. - * @retval None - */ -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP_IVInitStruct->CRYP_IV0Left = 0; - CRYP_IVInitStruct->CRYP_IV0Right = 0; - CRYP_IVInitStruct->CRYP_IV1Left = 0; - CRYP_IVInitStruct->CRYP_IV1Right = 0; -} - -/** - * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the - * FIFOs are reset) - * @note The FIFOs must be flushed only when BUSY flag is reset. - * @param None - * @retval None - */ -void CRYP_FIFOFlush(void) -{ - /* Reset the read and write pointers of the FIFOs */ - CRYP->CR |= CRYP_CR_FFLUSH; -} - -/** - * @brief Enables or disables the CRYP peripheral. - * @param NewState: new state of the CRYP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; - } - else - { - /* Disable the Cryptographic processor */ - CRYP->CR &= ~CRYP_CR_CRYPEN; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group2 CRYP Data processing functions - * @brief CRYP Data processing functions - * -@verbatim - =============================================================================== - CRYP Data processing functions - =============================================================================== - This section provides functions allowing the encryption and decryption - operations: - - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - - Get the data result from the OUT FIFO : using CRYP_DataOut() function. - -@endverbatim - * @{ - */ - -/** - * @brief Writes data in the Data Input register (DIN). - * @note After the DIN register has been read once or several times, - * the FIFO must be flushed (using CRYP_FIFOFlush() function). - * @param Data: data to write in Data Input register - * @retval None - */ -void CRYP_DataIn(uint32_t Data) -{ - CRYP->DR = Data; -} - -/** - * @brief Returns the last data entered into the output FIFO. - * @param None - * @retval Last data entered into the output FIFO. - */ -uint32_t CRYP_DataOut(void) -{ - return CRYP->DOUT; -} -/** - * @} - */ - -/** @defgroup CRYP_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store CRYP Context - - It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. - - 1. To save the current context, use CRYP_SaveContext() function - 2. To restore the saved context, use CRYP_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Saves the CRYP peripheral Context. - * @note This function stops DMA transfer before to save the context. After - * restoring the context, you have to enable the DMA again (if the DMA - * was previously used). - * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains - * the repository for current context. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - __IO uint32_t timeout = 0; - uint32_t ckeckmask = 0, bitstatus; - ErrorStatus status = ERROR; - - /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; - - /* Wait until both the IN and OUT FIFOs are empty - (IFEM=1 and OFNE=0 in the CRYP_SR register) and the - BUSY bit is cleared. */ - - if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; - } - else /* AES or DES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; - } - - do - { - bitstatus = CRYP->SR & ckeckmask; - timeout++; - } - while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); - - if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) - { - status = ERROR; - } - else - { - /* Stop DMA transfers on the OUT FIFO by - - writing the DOEN bit to 0 in the CRYP_DMACR register - - and clear the CRYPEN bit. */ - - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; - CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - - /* Save the current configuration (bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_bits9to2 = CRYP->CR & (CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); - - /* and, if not in ECB mode, the initialization vectors. */ - CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; - CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; - CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; - CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; - - /* save The key value */ - CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; - - /* When needed, save the DMA status (pointers for IN and OUT messages, - number of remaining bytes, etc.) */ - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Restores the CRYP peripheral Context. - * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function, - * after restoring the context, you have to enable the DMA again (if the - * DMA was previously used). - * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains - * the repository for saved context. - * @note The data that were saved during context saving must be rewrited into - * the IN FIFO. - * @retval None - */ -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) -{ - - /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_bits9to2; - - /* restore The key value */ - CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; - CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; - CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; - CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; - CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; - CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; - CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; - CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; - - /* and the initialization vectors. */ - CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; - CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; - CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; - CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; - - /* Enable the cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; -} -/** - * @} - */ - -/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function - * @brief CRYP's DMA interface Configuration function - * -@verbatim - =============================================================================== - CRYP's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. - - When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - - From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRYP DMA interface. - * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer - * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer - * @param NewState: new state of the selected CRYP DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP DMA request */ - CRYP->DMACR |= CRYP_DMAReq; - } - else - { - /* Disable the selected CRYP DMA request */ - CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - The CRYP provides 2 Interrupts sources and 7 Flags: - - Flags : - ------- - - 1. CRYP_FLAG_IFEM : Set when Input FIFO is empty. - This Flag is cleared only by hardware. - - 2. CRYP_FLAG_IFNF : Set when Input FIFO is not full. - This Flag is cleared only by hardware. - - - 3. CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the input FIFO service interrupt. - This Flag is cleared only by hardware. - - 4. CRYP_FLAG_OFNE : Set when Output FIFO not empty. - This Flag is cleared only by hardware. - - 5. CRYP_FLAG_OFFU : Set when Output FIFO is full. - This Flag is cleared only by hardware. - - 6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending - it gives the raw interrupt state prior to masking - of the output FIFO service interrupt. - This Flag is cleared only by hardware. - - 7. CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a - block of data or a key preparation (for AES - decryption). - This Flag is cleared only by hardware. - To clear it, the CRYP core must be disabled and the - last processing has completed. - - Interrupts : - ------------ - - 1. CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. - This interrupt is associated to CRYP_FLAG_INRIS flag. - - @note This interrupt is cleared by performing write operations - to the input FIFO until it holds 4 or more words. The - input FIFO service interrupt INMIS is enabled with the - CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. - - - - 2. CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. - This interrupt is associated to CRYP_FLAG_OUTRIS flag. - - @note This interrupt is cleared by reading data from the output - FIFO until there is no valid (32-bit) word left (that is, - the interrupt follows the state of the OFNE (output FIFO - not empty) flag). - - - Managing the CRYP controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - CRYP_GetFlagStatus() : to check if flags events occur. - - @note The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. - - - 2. In the Interrupt Mode it is advised to use the following functions: - - CRYP_ITConfig() : to enable or disable the interrupt source. - - CRYP_GetITStatus() : to check if Interrupt occurs. - - @note The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified CRYP interrupts. - * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @param NewState: new state of the specified CRYP interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP interrupt */ - CRYP->IMSCR |= CRYP_IT; - } - else - { - /* Disable the selected CRYP interrupt */ - CRYP->IMSCR &= (uint8_t)~CRYP_IT; - } -} - -/** - * @brief Checks whether the specified CRYP interrupt has occurred or not. - * @note This function checks the status of the masked interrupt (i.e the - * interrupt should be previously enabled). - * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. - * This parameter can be one of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @retval The new state of CRYP_IT (SET or RESET). - */ -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CRYP_GET_IT(CRYP_IT)); - - /* Check the status of the specified CRYP interrupt */ - if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) - { - /* CRYP_IT is set */ - bitstatus = SET; - } - else - { - /* CRYP_IT is reset */ - bitstatus = RESET; - } - /* Return the CRYP_IT status */ - return bitstatus; -} - -/** - * @brief Checks whether the specified CRYP flag is set or not. - * @param CRYP_FLAG: specifies the CRYP flag to check. - * This parameter can be one of the following values: - * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. - * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. - * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. - * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. - * @arg CRYP_FLAG_BUSY: Busy flag. - * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. - * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. - * @retval The new state of CRYP_FLAG (SET or RESET). - */ -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); - - /* check if the FLAG is in RISR register */ - if ((CRYP_FLAG & FLAG_MASK) != 0x00) - { - tempreg = CRYP->RISR; - } - else /* The FLAG is in SR register */ - { - tempreg = CRYP->SR; - } - - - /* Check the status of the specified CRYP flag */ - if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) - { - /* CRYP_FLAG is set */ - bitstatus = SET; - } - else - { - /* CRYP_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CRYP_FLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c deleted file mode 100644 index a13aca304..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_cryp_aes.c +++ /dev/null @@ -1,644 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_cryp_aes.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR modes. - * It uses the stm32f2xx_cryp.c/.h drivers to access the STM32F2xx CRYP - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The CRYP controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - * - * 2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() - * function. - * - * 3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() - * function. - * - * 4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() - * function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group6 High Level AES functions - * @brief High Level AES functions - * -@verbatim - =============================================================================== - High Level AES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using AES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer, must be a multiple of 16. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t Ilength, uint8_t* Output) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /*------------------ AES Decryption ------------------*/ - if(Mode == MODE_DECRYPT) /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* wait until the Busy flag is RESET */ - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Crypto Init for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - } - /*------------------ AES Encryption ------------------*/ - else /* AES encryption */ - { - - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group8 High Level DES functions - * @brief High Level DES functions - * -@verbatim - =============================================================================== - High Level DES functions - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using DES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for DES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef DES_CRYP_InitStructure; - CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if( Mode == MODE_ENCRYPT ) /* DES encryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; - DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&DES_CRYP_InitStructure); - - /* Key Initialisation */ - DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& DES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_cryp.h" - - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group7 High Level TDES functions - * @brief High Level TDES functions - * -@verbatim - =============================================================================== - High Level TDES functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using TDES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for TDES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef TDES_CRYP_InitStructure; - CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if(Mode == MODE_ENCRYPT) /* TDES encryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&TDES_CRYP_InitStructure); - - /* Key Initialisation */ - TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - for(i=0; ((i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dac.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - DAC channels configuration: trigger, output buffer, data format - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - DMA management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c deleted file mode 100644 index 160f2b4b4..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dbgmcu.c +++ /dev/null @@ -1,180 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dbgmcu.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dbgmcu.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c deleted file mode 100644 index 5bf4c9cc1..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dcmi.c +++ /dev/null @@ -1,540 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dcmi.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the DCMI peripheral: - * - Initialization and Configuration - * - Image capture functions - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * The sequence below describes how to use this driver to capture image - * from a camera module connected to the DCMI Interface. - * This sequence does not take into account the configuration of the - * camera module, which should be made before to configure and enable - * the DCMI to capture images. - * - * 1. Enable the clock for the DCMI and associated GPIOs using the following functions: - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. DCMI pins configuration - * - Connect the involved DCMI pins to AF13 using the following function - * GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - * - Configure these DCMI pins in alternate function mode by calling the function - * GPIO_Init(); - * - * 3. Declare a DCMI_InitTypeDef structure, for example: - * DCMI_InitTypeDef DCMI_InitStructure; - * and fill the DCMI_InitStructure variable with the allowed values - * of the structure member. - * - * 4. Initialize the DCMI interface by calling the function - * DCMI_Init(&DCMI_InitStructure); - * - * 5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - * register to the destination memory buffer. - * - * 6. Enable DCMI interface using the function - * DCMI_Cmd(ENABLE); - * - * 7. Start the image capture using the function - * DCMI_CaptureCmd(ENABLE); - * - * 8. At this stage the DCMI interface waits for the first start of frame, - * then a DMA request is generated continuously/once (depending on the - * mode used, Continuous/Snapshot) to transfer the received data into - * the destination memory. - * - * @note If you need to capture only a rectangular window from the received - * image, you have to use the DCMI_CROPConfig() function to configure - * the coordinates and size of the window to be captured, then enable - * the Crop feature using DCMI_CROPCmd(ENABLE); - * In this case, the Crop configuration should be made before to enable - * and start the DCMI interface. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dcmi.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DCMI - * @brief DCMI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DCMI_Private_Functions - * @{ - */ - -/** @defgroup DCMI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DCMI registers to their default reset values. - * @param None - * @retval None - */ -void DCMI_DeInit(void) -{ - DCMI->CR = 0x0; - DCMI->IER = 0x0; - DCMI->ICR = 0x1F; - DCMI->ESCR = 0x0; - DCMI->ESUR = 0x0; - DCMI->CWSTRTR = 0x0; - DCMI->CWSIZER = 0x0; -} - -/** - * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. - * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) -{ - uint32_t temp = 0x0; - - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); - assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); - assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); - assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); - - /* The DCMI configuration registers should be programmed correctly before - enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ - DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); - - /* Reset the old DCMI configuration */ - temp = DCMI->CR; - - temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | - DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | - DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); - - /* Sets the new configuration of the DCMI peripheral */ - temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | - DCMI_InitStruct->DCMI_SynchroMode | - DCMI_InitStruct->DCMI_PCKPolarity | - DCMI_InitStruct->DCMI_VSPolarity | - DCMI_InitStruct->DCMI_HSPolarity | - DCMI_InitStruct->DCMI_CaptureRate | - DCMI_InitStruct->DCMI_ExtendedDataMode); - - DCMI->CR = temp; -} - -/** - * @brief Fills each DCMI_InitStruct member with its default value. - * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) -{ - /* Set the default configuration */ - DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; - DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; - DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; - DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; - DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; - DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; - DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; -} - -/** - * @brief Initializes the DCMI peripheral CROP mode according to the specified - * parameters in the DCMI_CROPInitStruct. - * @note This function should be called before to enable and start the DCMI interface. - * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that - * contains the configuration information for the DCMI peripheral CROP mode. - * @retval None - */ -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) -{ - /* Sets the CROP window coordinates */ - DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); - - /* Sets the CROP window size */ - DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); -} - -/** - * @brief Enables or disables the DCMI Crop feature. - * @note This function should be called before to enable and start the DCMI interface. - * @param NewState: new state of the DCMI Crop feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CROPCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; - } - else - { - /* Disable the DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; - } -} - -/** - * @brief Sets the embedded synchronization codes - * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that - * contains the embedded synchronization codes for the DCMI peripheral. - * @retval None - */ -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) -{ - DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); -} - -/** - * @brief Enables or disables the DCMI JPEG format. - * @note The Crop and Embedded Synchronization features cannot be used in this mode. - * @param NewState: new state of the DCMI JPEG format. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_JPEGCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI JPEG format */ - DCMI->CR |= (uint32_t)DCMI_CR_JPEG; - } - else - { - /* Disable the DCMI JPEG format */ - DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; - } -} -/** - * @} - */ - -/** @defgroup DCMI_Group2 Image capture functions - * @brief Image capture functions - * -@verbatim - =============================================================================== - Image capture functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface. - * @param NewState: new state of the DCMI interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI by setting ENABLE bit */ - DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; - } - else - { - /* Disable the DCMI by clearing ENABLE bit */ - DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; - } -} - -/** - * @brief Enables or disables the DCMI Capture. - * @param NewState: new state of the DCMI capture. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CaptureCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Capture */ - DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; - } - else - { - /* Disable the DCMI Capture */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; - } -} - -/** - * @brief Reads the data stored in the DR register. - * @param None - * @retval Data register value - */ -uint32_t DCMI_ReadData(void) -{ - return DCMI->DR; -} -/** - * @} - */ - -/** @defgroup DCMI_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface interrupts. - * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @param NewState: new state of the specified DCMI interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - DCMI->IER |= DCMI_IT; - } - else - { - /* Disable the Interrupt sources */ - DCMI->IER &= (uint16_t)(~DCMI_IT); - } -} - -/** - * @brief Checks whether the DCMI interface flag is set or not. - * @param DCMI_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask - * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask - * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask - * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask - * @arg DCMI_FLAG_LINEMI: Line Masked flag mask - * @arg DCMI_FLAG_HSYNC: HSYNC flag mask - * @arg DCMI_FLAG_VSYNC: VSYNC flag mask - * @arg DCMI_FLAG_FNE: Fifo not empty flag mask - * @retval The new state of DCMI_FLAG (SET or RESET). - */ -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t dcmireg, tempreg = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); - - /* Get the DCMI register index */ - dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - - if (dcmireg == 0x00) /* The FLAG is in RISR register */ - { - tempreg= DCMI->RISR; - } - else if (dcmireg == 0x02) /* The FLAG is in SR register */ - { - tempreg = DCMI->SR; - } - else /* The FLAG is in MISR register */ - { - tempreg = DCMI->MISR; - } - - if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the DCMI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DCMI's pending flags. - * @param DCMI_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @retval None - */ -void DCMI_ClearFlag(uint16_t DCMI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); - - /* Clear the flag by writing in the ICR register 1 in the corresponding - Flag position*/ - - DCMI->ICR = DCMI_FLAG; -} - -/** - * @brief Checks whether the DCMI interrupt has occurred or not. - * @param DCMI_IT: specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The new state of DCMI_IT (SET or RESET). - */ -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_IT(DCMI_IT)); - - itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ - - if ((itstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DCMI's interrupt pending bits. - * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -void DCMI_ClearITPendingBit(uint16_t DCMI_IT) -{ - /* Clear the interrupt pending Bit by writing in the ICR register 1 in the - corresponding pending Bit position*/ - - DCMI->ICR = DCMI_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c deleted file mode 100644 index 92f9e8584..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_dma.c +++ /dev/null @@ -1,1289 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_dma.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * - Initialization and Configuration - * - Data Counter - * - Double Buffer mode configuration and command - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - * function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - * function for DMA2. - * - * 2. Enable and configure the peripheral to be connected to the DMA Stream - * (except for internal SRAM / FLASH memories: no initialization is - * necessary). - * - * 3. For a given Stream, program the required configuration through following parameters: - * Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - * data formats, Circular or Normal mode, Stream Priority level, Source and Destination - * Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or - * Destination (if needed) using the DMA_Init() function. - * To avoid filling un-nesecessary fields, you can call DMA_StructInit() function - * to initialize a given structure with default values (reset values), the modify - * only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats). - * - * 4. Enable the NVIC and the corresponding interrupt(s) using the function - * DMA_ITConfig() if you need to use DMA interrupts. - * - * 5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - * the second Memory address and the first Memory to be used through the function - * DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - * DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - * - * 6. Enable the DMA stream using the DMA_Cmd() function. - * - * 7. Activate the needed Stream Request using PPP_DMACmd() function for - * any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - * The function allowing this operation is provided in each PPP peripheral - * driver (ie. SPI_DMACmd for SPI peripheral). - * Once the Stream is enabled, it is not possible to modify its configuration - * unless the stream is stopped and disabled. - * After enabling the Stream, it is advised to monitor the EN bit status using - * the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - * this bit will remain reset and all transfers on this Stream will remain on hold. - * - * 8. Optionally, you can configure the number of data to be transferred - * when the Stream is disabled (ie. after each Transfer Complete event - * or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - * And you can get the number of remaining data to be transferred using - * the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - * enabled and running). - * - * 9. To control DMA events you can use one of the following - * two methods: - * a- Check on DMA Stream flags using the function DMA_GetFlagStatus(). - * b- Use DMA interrupts through the function DMA_ITConfig() at initialization - * phase and DMA_GetITStatus() function into interrupt routines in - * communication phase. - * After checking on a flag you should clear it using DMA_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using DMA_ClearITPendingBit() function. - * - * 10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - * the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - * the Memory Address to be modified is not the one currently in use by DMA Stream. - * This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - * - * 11. Optionally, Pause-Resume operations may be performed: - * The DMA_Cmd() function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will cause the - * transfer to be paused. All configuration registers and the number of remaining - * data will be preserved. When calling again this function to re-enable the Stream, - * the transfer will be resumed from the point where it was paused. - * - * @note Memory-to-Memory transfer is possible by setting the address of the memory into - * the Peripheral registers. In this mode, Circular mode and Double Buffer mode - * are not allowed. - * - * @note The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - * possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - * Half-Word data size for the peripheral to access its data register and set Word data size - * for the Memory to gain in access time. Each two Half-words will be packed and written in - * a single access to a Word in the Memory). - * - * @note When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - * and Destination. In this case the Peripheral Data Size will be applied to both Source - * and Destination. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_dma.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0033) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - Data Counter functions - =============================================================================== - - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - - The following function can be used to write the Stream data counter value: - - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@note It is advised to use this function rather than DMA_Init() in situations where - only the Data buffer needs to be reloaded. - -@note If the Source and Destination Data Sizes are different, then the value written in - data counter, expressing the number of transfers, is relative to the number of - transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value - to be configured in the data counter is the number of Half-Words to be transferred - from/to the peripheral. - - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - - If Normal mode is selected: the counter is set to 0. - - If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - - The following function can be used to read the Stream data counter value: - - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - Double Buffer mode functions - =============================================================================== - - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from target - memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - Two functions must be called before calling the DMA_Init() function: - - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); - - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first - Memory target from/to which the transfer will start after enabling the DMA Stream. - Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable - it when it should not be used). - - - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check wich Memory target is currently - used: - - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); - - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories. - The Memory of which the base address will be modified must not be currently be used by the DMA Stream - (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address - of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides functions allowing to - - Check the DMA enable status - - Check the FIFO status - - Configure the DMA Interrupts sources and check or clear the flags or pending bits status. - - 1. DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling the stream, - it is recommended to check (or wait until) the DMA Stream is effectively enabled. - A Stream may remain disabled if a configuration parameter is wrong. - After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA - Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, - the current data will be transferred and the Stream will be effectively disabled only after - this data transfer completion. - To monitor this state it is possible to use the following function: - - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 2. FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - 3. DMA Interrupts and Flags: - The user should identify which mode will be used in his application to manage the - DMA controller events: Polling mode or Interrupt mode. - - Polling Mode - ============= - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - 1. DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - 2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - 3. DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - 4. DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - 5. DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - - In this Mode it is advised to use the following functions: - - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - Interrupt Mode - =============== - Each DMA Stream can be managed through 4 Interrupts: - - Interrupt Source - ---------------- - 1. DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - 2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - 3. DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - 4. DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - 5. DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - - In this Mode it is advised to use the following functions: - - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c deleted file mode 100644 index 9cf97ee91..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_exti.c +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_exti.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * - Initialization and Configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * EXTI features - * =================================================================== - * - * External interrupt/event lines are mapped as following: - * 1- All available GPIO pins are connected to the 16 external - * interrupt/event lines from EXTI0 to EXTI15. - * 2- EXTI line 16 is connected to the PVD Output - * 3- EXTI line 17 is connected to the RTC Alarm event - * 4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - * 5- EXTI line 19 is connected to the Ethernet Wakeup event - * 6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - * 7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events - * 8- EXTI line 22 is connected to the RTC Wakeup event - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * In order to use an I/O pin as an external interrupt source, follow - * steps below: - * 1- Configure the I/O in input mode using GPIO_Init() - * 2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - * 3- Select the mode(interrupt, event) and configure the trigger - * selection (Rising, falling or both) using EXTI_Init() - * 4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - * registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_exti.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - enablestatus = EXTI->IMR & EXTI_Line; - if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c deleted file mode 100644 index ff0f65eb6..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_flash.c +++ /dev/null @@ -1,1060 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_flash.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * - FLASH Interface configuration - * - FLASH Memory Programming - * - Option Bytes Programming - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions to configure and program the FLASH - * memory of all STM32F2xx devices. - * These functions are split in 4 groups: - * - * 1. FLASH Interface configuration functions: this group includes the - * management of the following features: - * - Set the latency - * - Enable/Disable the prefetch buffer - * - Enable/Disable the Instruction cache and the Data cache - * - Reset the Instruction cache and the Data cache - * - * 2. FLASH Memory Programming functions: this group includes all needed - * functions to erase and program the main memory: - * - Lock and Unlock the FLASH interface - * - Erase function: Erase sector, erase all sectors - * - Program functions: byte, half word, word and double word - * - * 3. Option Bytes Programming functions: this group includes all needed - * functions to manage the Option Bytes: - * - Set/Reset the write protection - * - Set the Read protection Level - * - Set the BOR level - * - Program the user Option Bytes - * - Launch the Option Bytes loader - * - * 4. Interrupts and flags management functions: this group - * includes all needed functions to: - * - Enable/Disable the FLASH interrupt sources - * - Get flags status - * - Clear flags - * - Get FLASH operation status - * - Wait for last FLASH operation - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_flash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - FLASH Interface configuration functions - =============================================================================== - - This group includes the following functions: - - void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - |***************|****************|****************|*****************|*****************|*****************************+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - - void FLASH_PrefetchBufferCmd(FunctionalState NewState) - - void FLASH_InstructionCacheCmd(FunctionalState NewState) - - void FLASH_DataCacheCmd(FunctionalState NewState) - - void FLASH_InstructionCacheReset(void) - - void FLASH_DataCacheReset(void) - - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - FLASH Memory Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_Unlock(void) - - void FLASH_Lock(void) - - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_Unlock() function to enable the FLASH control register access - - 2. Call the desired function to erase sector(s) or program data - - 3. Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @param FLASH_Sector: The Sector number to be erased. - * This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11 - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - Option Bytes Programming functions - =============================================================================== - - This group includes the following functions: - - void FLASH_OB_Unlock(void) - - void FLASH_OB_Lock(void) - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - - void FLASH_OB_BORConfig(uint8_t OB_BOR) - - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - - FLASH_Status FLASH_OB_Launch(void) - - uint32_t FLASH_OB_GetUser(void) - - uint8_t FLASH_OB_GetWRP(void) - - uint8_t FLASH_OB_GetRDP(void) - - uint8_t FLASH_OB_GetBOR(void) - - Any operation of erase or program should follow these steps: - 1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access - - 2. Call one or several functions to program the desired Option Bytes: - - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable - the desired sector write protection - - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level - - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure - the user Option Bytes. - - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - 3. Once all needed Option Bytes to be programmed are correctly written, call the - FLASH_OB_Launch() function to launch the Option Bytes programming process. - - @note When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - 4. Call the FLASH_OB_Lock() function to disable the FLASH option control register - access (recommended to protect the Option Bytes against possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c deleted file mode 100644 index 357188281..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_fsmc.c +++ /dev/null @@ -1,987 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_fsmc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * - Interface with SRAM, PSRAM, NOR and OneNAND memories - * - Interface with NAND memories - * - Interface with 16-bit PC Card compatible memories - * - Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_fsmc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - NOR/SRAM Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - 5. Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Bank1 NOR/SRAM control register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - /* Bank1 NOR/SRAM timing register configuration */ - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = - (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF; - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - NAND Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 8-bit or 16-bit NAND memory connected to the NAND Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - 5. Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the NAND Bank. - -@note To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - PCCARD Controller functions - =============================================================================== - - The following sequence should be followed to configure the FSMC to interface with - 16-bit PC Card compatible memory connected to the PCCARD Bank: - - 1. Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - 2. FSMC pins configuration - - Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - - Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - 3. Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - 4. Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - 5. Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - 6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c deleted file mode 100644 index c53371e3d..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_gpio.c +++ /dev/null @@ -1,566 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_gpio.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * - Initialization and Configuration - * - GPIO Read and Write - * - GPIO Alternate functions configuration - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable the GPIO AHB clock using the following function - * RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - * - * 2. Configure the GPIO pin(s) using GPIO_Init() - * Four possible configuration are available for each pin: - * - Input: Floating, Pull-up, Pull-down. - * - Output: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * In output mode, the speed is configurable: 2 MHz, 25 MHz, - * 50 MHz or 100 MHz. - * - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) - * Open Drain (Pull-up, Pull-down or no Pull). - * - Analog: required mode when a pin is to be used as ADC channel - * or DAC output. - * - * 3- Peripherals alternate function: - * - For ADC and DAC, configure the desired pin in analog mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - * - For other peripherals (TIM, USART...): - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function mode using - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - * - * 5. To set/reset the level of a pin configured in output mode use - * GPIO_SetBits()/GPIO_ResetBits() - * - * 6. During and just after reset, the alternate functions are not - * active and the GPIO pins are configured in input floating mode - * (except JTAG pins). - * - * 7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as - * general-purpose (PC14 and PC15, respectively) when the LSE - * oscillator is off. The LSE has priority over the GPIO function. - * - * 8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as - * general-purpose PH0 and PH1, respectively, when the HSE - * oscillator is off. The HSE has priority over the GPIO function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_gpio.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - Initialization and Configuration - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - else - { - if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* -------------------------Configure the port pins---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - GPIO Read and Write - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - GPIO Alternate functions configuration function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c deleted file mode 100644 index c5c799b98..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash.c +++ /dev/null @@ -1,706 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the HASH / HMAC Processor (HASH) peripheral: - * - Initialization and Configuration functions - * - Message Digest generation functions - * - context swapping functions - * - DMA interface function - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * HASH operation : - * ---------------- - * 1. Enable the HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - * - * 2. Initialise the HASH using HASH_Init() function. - * - * 3 . Reset the HASH processor core, so that the HASH will be ready - * to compute he message digest of a new message by using - * HASH_Reset() function. - * - * 4. Enable the HASH controller using the HASH_Cmd() function. - * - * 5. if using DMA for Data input transfer, Activate the DMA Request - * using HASH_DMACmd() function - * - * 6. if DMA is not used for data transfer, use HASH_DataIn() function - * to enter data to IN FIFO. - * - * - * 7. Configure the Number of valid bits in last word of the message - * using HASH_SetLastWordValidBitsNbr() function. - * - * 8. if the message length is not an exact multiple of 512 bits, - * then the function HASH_StartDigest() must be called to - * launch the computation of the final digest. - * - * 9. Once computed, the digest can be read using HASH_GetDigest() - * function. - * - * 10. To control HASH events you can use one of the following - * two methods: - * a- Check on HASH flags using the HASH_GetFlagStatus() function. - * b- Use HASH interrupts through the function HASH_ITConfig() at - * initialization phase and HASH_GetITStatus() function into - * interrupt routines in hashing phase. - * After checking on a flag you should clear it using HASH_ClearFlag() - * function. And after checking on an interrupt event you should - * clear it using HASH_ClearITPendingBit() function. - * - * 11. Save and restore hash processor context using - * HASH_SaveContext() and HASH_RestoreContext() functions. - * - * - * - * HMAC operation : - * ---------------- - * The HMAC algorithm is used for message authentication, by - * irreversibly binding the message being processed to a key chosen - * by the user. - * For HMAC specifications, refer to "HMAC: keyed-hashing for message - * authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - * - * Basically, the HMAC algorithm consists of two nested hash operations: - * HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - * where: - * - "pad" is a sequence of zeroes needed to extend the key to the - * length of the underlying hash function data block (that is - * 512 bits for both the SHA-1 and MD5 hash algorithms) - * - "|" represents the concatenation operator - * - * - * To compute the HMAC, four different phases are required: - * - * 1. Initialise the HASH using HASH_Init() function to do HMAC - * operation. - * - * 2. The key (to be used for the inner hash function) is then given - * to the core. This operation follows the same mechanism as the - * one used to send the message in the hash operation (that is, - * by HASH_DataIn() function and, finally, - * HASH_StartDigest() function. - * - * 3. Once the last word has been entered and computation has started, - * the hash processor elaborates the key. It is then ready to - * accept the message text using the same mechanism as the one - * used to send the message in the hash operation. - * - * 4. After the first hash round, the hash processor returns "ready" - * to indicate that it is ready to receive the key to be used for - * the outer hash function (normally, this key is the same as the - * one used for the inner hash function). When the last word of - * the key is entered and computation starts, the HMAC result is - * made available using HASH_GetDigest() function. - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the HASH peripheral - - Configure the HASH Processor - - MD5/SHA1, - - HASH/HMAC, - - datatype - - HMAC Key (if mode = HMAC) - - Reset the HASH Processor - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HASH peripheral registers to their default reset values - * @param None - * @retval None - */ -void HASH_DeInit(void) -{ - /* Enable HASH reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); - /* Release HASH from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); -} - -/** - * @brief Initializes the HASH peripheral according to the specified parameters - * in the HASH_InitStruct structure. - * @note the hash processor is reset when calling this function so that the - * HASH will be ready to compute the message digest of a new message. - * There is no need to call HASH_Reset() function. - * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains - * the configuration information for the HASH peripheral. - * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only - * if the algorithm mode is HMAC. - * @retval None - */ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); - assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); - assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); - - /* Configure the Algorithm used, algorithm mode and the datatype */ - HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); - HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ - HASH_InitStruct->HASH_DataType | \ - HASH_InitStruct->HASH_AlgoMode); - - /* if algorithm mode is HMAC, set the Key */ - if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) - { - assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); - HASH->CR &= ~HASH_CR_LKEY; - HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; - } - - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; -} - -/** - * @brief Fills each HASH_InitStruct member with its default value. - * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will - * be initialized. - * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, - * Data type selected is 32b and HMAC Key Type is short key. - * @retval None - */ -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Initialize the HASH_AlgoSelection member */ - HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - - /* Initialize the HASH_AlgoMode member */ - HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; - - /* Initialize the HASH_DataType member */ - HASH_InitStruct->HASH_DataType = HASH_DataType_32b; - - /* Initialize the HASH_HMACKeyType member */ - HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; -} - -/** - * @brief Resets the HASH processor core, so that the HASH will be ready - * to compute the message digest of a new message. - * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation - * completion interrupt status) bit corresponding to HASH_IT_DCI - * interrupt and HASH_FLAG_DCIS flag. - * @param None - * @retval None - */ -void HASH_Reset(void) -{ - /* Reset the HASH processor core */ - HASH->CR |= HASH_CR_INIT; -} -/** - * @} - */ - -/** @defgroup HASH_Group2 Message Digest generation functions - * @brief Message Digest generation functions - * -@verbatim - =============================================================================== - Message Digest generation functions - =============================================================================== - This section provides functions allowing the generation of message digest: - - Push data in the IN FIFO : using HASH_DataIn() - - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - - start digest calculation : using HASH_StartDigest() - - Get the Digest message : using HASH_GetDigest() - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the Number of valid bits in last word of the message - * @param ValidNumber: Number of valid bits in last word of the message. - * This parameter must be a number between 0 and 0x1F. - * - 0x00: All 32 bits of the last data written are valid - * - 0x01: Only bit [0] of the last data written is valid - * - 0x02: Only bits[1:0] of the last data written are valid - * - 0x03: Only bits[2:0] of the last data written are valid - * - ... - * - 0x1F: Only bits[30:0] of the last data written are valid - * @note The Number of valid bits must be set before to start the message - * digest competition (in Hash and HMAC) and key treatment(in HMAC). - * @retval None - */ -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) -{ - /* Check the parameters */ - assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); - - /* Configure the Number of valid bits in last word of the message */ - HASH->STR &= ~(HASH_STR_NBW); - HASH->STR |= ValidNumber; -} - -/** - * @brief Writes data in the Data Input FIFO - * @param Data: new data of the message to be processed. - * @retval None - */ -void HASH_DataIn(uint32_t Data) -{ - /* Write in the DIN register a new data */ - HASH->DIN = Data; -} - -/** - * @brief Returns the number of words already pushed into the IN FIFO. - * @param None - * @retval The value of words already pushed into the IN FIFO. - */ -uint8_t HASH_GetInFIFOWordsNbr(void) -{ - /* Return the value of NBW bits */ - return ((HASH->CR & HASH_CR_NBW) >> 8); -} - -/** - * @brief Provides the message digest result. - * @note In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will - * hold the message digest result - * @retval None - */ -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) -{ - /* Get the data field */ - HASH_MessageDigest->Data[0] = HASH->HR[0]; - HASH_MessageDigest->Data[1] = HASH->HR[1]; - HASH_MessageDigest->Data[2] = HASH->HR[2]; - HASH_MessageDigest->Data[3] = HASH->HR[3]; - HASH_MessageDigest->Data[4] = HASH->HR[4]; -} - -/** - * @brief Starts the message padding and calculation of the final message - * @param None - * @retval None - */ -void HASH_StartDigest(void) -{ - /* Start the Digest calculation */ - HASH->STR |= HASH_STR_DCAL; -} -/** - * @} - */ - -/** @defgroup HASH_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - Context swapping functions - =============================================================================== - - This section provides functions allowing to save and store HASH Context - - It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. - - 1. To save the current context, use HASH_SaveContext() function - 2. To restore the saved context, use HASH_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Save the Hash peripheral Context. - * @note The context can be saved only when no block is currently being - * processed. So user must wait for DINIS = 1 (the last block has been - * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not - * full and no processing is ongoing). - * @param HASH_ContextSave: pointer to a HASH_Context structure that contains - * the repository for current context. - * @retval None - */ -void HASH_SaveContext(HASH_Context* HASH_ContextSave) -{ - uint8_t i = 0; - - /* save context registers */ - HASH_ContextSave->HASH_IMR = HASH->IMR; - HASH_ContextSave->HASH_STR = HASH->STR; - HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=50;i++) - { - HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; - } -} - -/** - * @brief Restore the Hash peripheral Context. - * @note After calling this function, user can restart the processing from the - * point where it has been interrupted. - * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains - * the repository for saved context. - * @retval None - */ -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) -{ - uint8_t i = 0; - - /* restore context registers */ - HASH->IMR = HASH_ContextRestore->HASH_IMR; - HASH->STR = HASH_ContextRestore->HASH_STR; - HASH->CR = HASH_ContextRestore->HASH_CR; - - /* Initialize the hash processor */ - HASH->CR |= HASH_CR_INIT; - - /* continue restoring context registers */ - for(i=0; i<=50;i++) - { - HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group4 HASH's DMA interface Configuration function - * @brief HASH's DMA interface Configuration function - * -@verbatim - =============================================================================== - HASH's DMA interface Configuration function - =============================================================================== - - This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. - - When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the HASH DMA interface. - * @note The DMA is disabled by hardware after the end of transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the HASH DMA request */ - HASH->CR |= HASH_CR_DMAE; - } - else - { - /* Disable the HASH DMA request */ - HASH->CR &= ~HASH_CR_DMAE; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The HASH provides 2 Interrupts sources and 5 Flags: - - Flags : - ---------- - 1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered - into the input buffer. - - 2. HASH_FLAG_DCIS : set when Digest calculation is complete - - 3. HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. - This Flag is cleared only by hardware. - - 4. HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. - - 5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. - This Flag is cleared only by hardware. - - Interrupts : - ------------ - - 1. HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that - a new block (512 bit) can be entered into the input buffer. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. - - 2. HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. - This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - Managing the HASH controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - HASH_GetFlagStatus() : to check if flags events occur. - - HASH_ClearFlag() : to clear the flags events. - - 2. In the Interrupt Mode it is advised to use the following functions: - - HASH_ITConfig() : to enable or disable the interrupt source. - - HASH_GetITStatus() : to check if Interrupt occurs. - - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified HASH interrupts. - * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @param NewState: new state of the specified HASH interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected HASH interrupt */ - HASH->IMR |= HASH_IT; - } - else - { - /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint8_t) ~HASH_IT; - } -} - -/** - * @brief Checks whether the specified HASH flag is set or not. - * @param HASH_FLAG: specifies the HASH flag to check. - * This parameter can be one of the following values: - * @arg HASH_FLAG_DINIS: Data input interrupt status flag - * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag - * @arg HASH_FLAG_BUSY: Busy flag - * @arg HASH_FLAG_DMAS: DMAS Status flag - * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag - * @retval The new state of HASH_FLAG (SET or RESET) - */ -FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); - - /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) - { - tempreg = HASH->CR; - } - else /* The FLAG is in SR register */ - { - tempreg = HASH->SR; - } - - /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint16_t)RESET) - { - /* HASH is set */ - bitstatus = SET; - } - else - { - /* HASH_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the HASH_FLAG status */ - return bitstatus; -} -/** - * @brief Clears the HASH flags. - * @param HASH_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg HASH_FLAG_DINIS: Data Input Flag - * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag - * @retval None - */ -void HASH_ClearFlag(uint16_t HASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); - - /* Clear the selected HASH flags */ - HASH->SR = ~(uint32_t)HASH_FLAG; -} -/** - * @brief Checks whether the specified HASH interrupt has occurred or not. - * @param HASH_IT: specifies the HASH interrupt source to check. - * This parameter can be one of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval The new state of HASH_IT (SET or RESET). - */ -ITStatus HASH_GetITStatus(uint8_t HASH_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_IT(HASH_IT)); - - - /* Check the status of the specified HASH interrupt */ - tmpreg = HASH->SR; - - if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) - { - /* HASH_IT is set */ - bitstatus = SET; - } - else - { - /* HASH_IT is reset */ - bitstatus = RESET; - } - /* Return the HASH_IT status */ - return bitstatus; -} - -/** - * @brief Clears the HASH interrupt pending bit(s). - * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval None - */ -void HASH_ClearITPendingBit(uint8_t HASH_IT) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - - /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint8_t)~HASH_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c deleted file mode 100644 index 21b929f4f..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_hash_md5.c +++ /dev/null @@ -1,320 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_hash_md5.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides high level functions to compute the HASH MD5 and - * HMAC MD5 Digest of an input message. - * It uses the stm32f2xx_hash.c/.h drivers to access the STM32F2xx HASH - * peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The HASH controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. - * - * 2. Calculate the HASH MD5 Digest using HASH_MD5() function. - * - * 3. Calculate the HMAC MD5 Digest using HMAC_MD5() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group7 High Level MD5 functions - * @brief High Level MD5 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level MD5 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH MD5 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) -{ - HASH_InitTypeDef MD5_HASH_InitStructure; - HASH_MsgDigest MD5_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; - MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2012 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_hash.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group6 High Level SHA1 functions - * @brief High Level SHA1 Hash and HMAC functions - * -@verbatim - =============================================================================== - High Level SHA1 Hash and HMAC functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH SHA1 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) -{ - HASH_InitTypeDef SHA1_HASH_InitStructure; - HASH_MsgDigest SHA1_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; iGPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * Recommended configuration is Push-Pull, Pull-up, Open-Drain. - * Add an external pull up if necessary (typically 4.7 KOhm). - * - * 4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - * Address using the I2C_Init() function. - * - * 5. Optionally you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again I2C_Init() function): - * - Enable the acknowledge feature using I2C_AcknowledgeConfig() function - * - Enable the dual addressing mode using I2C_DualAddressCmd() function - * - Enable the general call using the I2C_GeneralCallCmd() function - * - Enable the clock stretching using I2C_StretchClockCmd() function - * - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - * function. - * - Configure the NACK position for Master Receiver mode in case of - * 2 bytes reception using the function I2C_NACKPositionConfig(). - * - Enable the PEC Calculation using I2C_CalculatePEC() function - * - For SMBus Mode: - * - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - * - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - * - * 6. Enable the NVIC and the corresponding interrupt using the function - * I2C_ITConfig() if you need to use interrupt mode. - * - * 7. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using I2C_DMACmd() or - * I2C_DMALastTransferCmd() function. - * @note When using DMA mode, I2C interrupts may be used at the same time to - * control the communication flow (Start/Stop/Ack... events and errors). - * - * 8. Enable the I2C using the I2C_Cmd() function. - * - * 9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the - * transfers. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_i2c.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable generall call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable generall call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - PEC management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - Interrupts, events and flags management functions - =============================================================================== - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0033). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - @note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - the library (stm32f2xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f2xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f2xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f2xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c deleted file mode 100644 index 3939a1791..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_iwdg.c +++ /dev/null @@ -1,269 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_iwdg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * - Prescaler and Counter configuration - * - IWDG activation - * - Flag management - * - * @verbatim - * - * =================================================================== - * IWDG features - * =================================================================== - * - * The IWDG can be started by either software or hardware (configurable - * through option byte). - * - * The IWDG is clocked by its own dedicated low-speed clock (LSI) and - * thus stays active even if the main clock fails. - * Once the IWDG is started, the LSI is forced ON and cannot be disabled - * (LSI cannot be disabled too), and the counter starts counting down from - * the reset value of 0xFFF. When it reaches the end of count value (0x000) - * a system reset is generated. - * The IWDG counter should be reloaded at regular intervals to prevent - * an MCU reset. - * - * The IWDG is implemented in the VDD voltage domain that is still functional - * in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - * - * IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - * reset occurs. - * - * Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - * The IWDG timeout may vary due to LSI frequency dispersion. STM32F2xx - * devices provide the capability to measure the LSI frequency (LSI clock - * connected internally to TIM5 CH4 input capture). The measured value - * can be used to have an IWDG timeout with an acceptable accuracy. - * For more information, please refer to the STM32F2xx Reference manual - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable write access to IWDG_PR and IWDG_RLR registers using - * IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - * - * 2. Configure the IWDG prescaler using IWDG_SetPrescaler() function - * - * 3. Configure the IWDG counter value using IWDG_SetReload() function. - * This value will be loaded in the IWDG counter each time the counter - * is reloaded, then the IWDG will start counting down from this value. - * - * 4. Start the IWDG using IWDG_Enable() function, when the IWDG is used - * in software mode (no need to enable the LSI, it will be enabled - * by hardware) - * - * 5. Then the application program must reload the IWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * IWDG_ReloadCounter() function. - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_iwdg.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - IWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - Flag management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c deleted file mode 100644 index 99ad2dc83..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_pwr.c +++ /dev/null @@ -1,620 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_pwr.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * - Backup Domain Access - * - PVD configuration - * - WakeUp pin configuration - * - Backup Regulator configuration - * - FLASH Power Down configuration - * - Low Power modes configuration - * - Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_pwr.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* --- CSR Register ---*/ - -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFFFFC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - Backup Domain Access function - =============================================================================== - - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - - Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - PVD configuration functions - =============================================================================== - - - The PVD is used to monitor the VDD power supply by comparing it to a threshold - selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line16 - and can generate an interrupt if enabled through the EXTI registers. - - The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - WakeUp pin configuration functions - =============================================================================== - - - WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - - There is only one WakeUp pin: WakeUp Pin 1 on PA.00. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group4 Backup Regulator configuration functions - * @brief Backup Regulator configuration functions - * -@verbatim - =============================================================================== - Backup Regulator configuration functions - =============================================================================== - - - The backup domain includes 4 Kbytes of backup SRAM accessible only from the - CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained - even in Standby or VBAT mode when the low power backup regulator is enabled. - It can be considered as an internal EEPROM when VBAT is always present. - You can use the PWR_BackupRegulatorCmd() function to enable the low power - backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is - ready or not. - - - When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - - The backup SRAM is not mass erased by an tamper event. It is read protected - to prevent confidential data, such as cryptographic private key, from being - accessed. The backup SRAM can be erased only through the Flash interface when - a protection level change from level 1 to level 0 is requested. - Refer to the description of Read protection (RDP) in the Flash programming manual. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group5 FLASH Power Down configuration functions - * @brief FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - FLASH Power Down configuration functions - =============================================================================== - - - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd() - function, the Flash memory also enters power down mode when the device enters - Stop mode. When the Flash memory is in power down mode, an additional startup - delay is incurred when waking up from Stop mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - Low Power modes configuration functions - =============================================================================== - - The devices feature 3 low-power modes: - - Sleep mode: Cortex-M3 core stopped, peripherals kept running. - - Stop mode: all clocks are stopped, regulator running, regulator in low power mode - - Standby mode: 1.2V domain powered off. - - Sleep mode - =========== - - Entry: - - The Sleep mode is entered by using the __WFI() or __WFE() functions. - - Exit: - - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - Stop mode - ========== - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - - Entry: - - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) - function with regulator in LowPower or with Regulator ON. - - Exit: - - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - Standby mode - ============ - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M3 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - - Entry: - - The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - - Exit: - - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - Auto-wakeup (AWU) from low-power mode - ===================================== - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - - RTC auto-wakeup (AWU) from the Stop mode - ---------------------------------------- - - - To wake up from the Stop mode with an RTC alarm event, it is necessary to: - - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - RTC auto-wakeup (AWU) from the Standby mode - ------------------------------------------- - - To wake up from the Standby mode with an RTC alarm event, it is necessary to: - - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - - To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - - Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_Regulator_ON: STOP mode with regulator ON - * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDSR bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDSR bit according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Clear Wakeup flag */ - PWR->CR |= PWR_CR_CWUF; - - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - -/* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - Flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - - PWR->CR |= PWR_FLAG << 2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c deleted file mode 100644 index 2dd960a33..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rcc.c +++ /dev/null @@ -1,1817 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rcc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * - Internal/external clocks, PLL, CSS and MCO configuration - * - System, AHB and APB busses clocks configuration - * - Peripheral clocks configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * RCC specific features - * =================================================================== - * - * After reset the device is running from Internal High Speed oscillator - * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - * and I-Cache are disabled, and all peripherals are off except internal - * SRAM, Flash and JTAG. - * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; - * all peripherals mapped on these busses are running at HSI speed. - * - The clock for all peripherals is switched off, except the SRAM and FLASH. - * - All GPIOs are in input floating state, except the JTAG pins which - * are assigned to be used for debug purpose. - * - * Once the device started from reset, the user application has to: - * - Configure the clock source to be used to drive the System clock - * (if the application needs higher frequency/performance) - * - Configure the System clock frequency and Flash settings - * - Configure the AHB and APB busses prescalers - * - Enable the clock for the peripheral(s) to be used - * - Configure the clock source(s) for peripherals which clocks are not - * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =============================================================================== - Internal/external clocks, PLL, CSS and MCO configuration functions - =============================================================================== - - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - - The first output is used to generate the high speed system clock (up to 120 MHz) - - The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface. - - 7. CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) - exception vector. - - 8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - 9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 120 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note PLLI2S is available only in Silicon RevisionB and RevisionY. - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 192 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 192 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} - -/** - * @brief Enables or disables the PLLI2S. - * @note PLLI2S is available only in RevisionB and RevisionY - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - System, AHB and APB busses clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - 1. Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable prescaler - and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...). - APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through - configurable prescalers and used to clock the peripherals mapped on these busses. - You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - -@note All the peripheral clocks are derived from the System clock (SYSCLK) except: - - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - - IWDG clock which is always the LSI clock. - - 2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| - +-------------------------------------------------------------------------------------+ - - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - Peripheral clocks configuration functions - =============================================================================== - - This section provide functions allowing to configure the Peripheral clocks. - - 1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31. - - 2. After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral you - have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd() - , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - 3. To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - 4. To further reduce power consumption in SLEEP mode the peripheral clocks can - be disabled prior to executing the WFI or WFE instructions. You can do this - using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and - RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the I2S clock source (I2SCLK). - * - * @note This function must be called before enabling the I2S APB clock. - * @note This function applies only to Silicon RevisionB and RevisionY. - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: RCC_AHB3Periph_FSMC - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @} - */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c deleted file mode 100644 index 9f0d6c291..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rng.c +++ /dev/null @@ -1,405 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rng.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * - Initialization and Configuration - * - Get 32 bit Random number - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable The RNG controller clock using - * RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - * - * 2. Activate the RNG peripheral using RNG_Cmd() function. - * - * 3. Wait until the 32 bit Random number Generator contains a valid - * random data (using polling/interrupt mode). For more details, - * refer to "Interrupts and flags management functions" module - * description. - * - * 4. Get the 32 bit Random number using RNG_GetRandomNumber() function - * - * 5. To get another 32 bit Random number, go to step 3. - * - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rng.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - This section provides functions allowing to - - Initialize the RNG peripheral - - Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - Get 32 bit Random number function - =============================================================================== - This section provides a function allowing to get the 32 bit Random number - - @note Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - The RNG provides 3 Interrupts sources and 3 Flags: - - Flags : - ---------- - 1. RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data - (using RNG_GetRandomNumber() function). - - 2. RNG_FLAG_CECS : In the case of a seed error detection. - - 3. RNG_FLAG_SECS : In the case of a clock error detection. - - - Interrupts : - ------------ - if enabled, an RNG interrupt is pending : - - 1. In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed. - - or - 2. In the case of a seed error : One of the following faulty sequences has - been detected: - - More than 64 consecutive bits at the same value (0 or 1) - - More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function. - - or - 3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI) - function. - @note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - Managing the RNG controller events : - ------------------------------------ - The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - 1. In the Polling Mode it is advised to use the following functions: - - RNG_GetFlagStatus() : to check if flags events occur. - - RNG_ClearFlag() : to clear the flags events. - - @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - 2. In the Interrupt Mode it is advised to use the following functions: - - RNG_ITConfig() : to enable or disable the interrupt source. - - RNG_GetITStatus() : to check if Interrupt occurs. - - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c deleted file mode 100644 index 00c6aa68a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_rtc.c +++ /dev/null @@ -1,2244 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_rtc.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * - Initialization - * - Calendar (Time and Date) configuration - * - Alarms (Alarm A and Alarm B) configuration - * - WakeUp Timer configuration - * - Daylight Saving configuration - * - Output pin Configuration - * - Coarse Calibration configuration - * - TimeStamp configuration - * - Tampers configuration - * - Backup Data Registers configuration - * - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * Backup Domain Operating Condition - * =================================================================== - * The real-time clock (RTC), the RTC backup registers, and the backup - * SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - * VDD supply is powered off. - * To retain the content of the RTC backup registers, backup SRAM, - * and supply the RTC when VDD is turned off, VBAT pin can be connected - * to an optional standby voltage supplied by a battery or by another - * source. - * - * To allow the RTC to operate even when the main digital supply (VDD) - * is turned off, the VBAT pin powers the following blocks: - * 1 - The RTC - * 2 - The LSE oscillator - * 3 - The backup SRAM when the low power backup regulator is enabled - * 4 - PC13 to PC15 I/Os, plus PI8 I/O (when available) - * - * When the backup domain is supplied by VDD (analog switch connected - * to VDD), the following functions are available: - * 1 - PC14 and PC15 can be used as either GPIO or LSE pins - * 2 - PC13 can be used as a GPIO or as the RTC_AF1 pin - * 3 - PI8 can be used as a GPIO or as the RTC_AF2 pin - * - * When the backup domain is supplied by VBAT (analog switch connected - * to VBAT because VDD is not present), the following functions are available: - * 1 - PC14 and PC15 can be used as LSE pins only - * 2 - PC13 can be used as the RTC_AF1 pin - * 3 - PI8 can be used as the RTC_AF2 pin - * - * =================================================================== - * Backup Domain Reset - * =================================================================== - * The backup domain reset sets all RTC registers and the RCC_BDCR - * register to their reset values. The BKPSRAM is not affected by this - * reset. The only way of resetting the BKPSRAM is through the Flash - * interface by requesting a protection level change from 1 to 0. - * A backup domain reset is generated when one of the following events - * occurs: - * 1 - Software reset, triggered by setting the BDRST bit in the - * RCC Backup domain control register (RCC_BDCR). You can use the - * RCC_BackupResetCmd(). - * 2 - VDD or VBAT power on, if both supplies have previously been - * powered off. - * - * =================================================================== - * Backup Domain Access - * =================================================================== - * After reset, the backup domain (RTC registers, RTC backup data - * registers and backup SRAM) is protected against possible unwanted - * write accesses. - * To enable access to the RTC Domain and RTC registers, proceed as follows: - * - Enable the Power Controller (PWR) APB1 interface clock using the - * RCC_APB1PeriphClockCmd() function. - * - Enable access to RTC domain using the PWR_BackupAccessCmd() function. - * - Select the RTC clock source using the RCC_RTCCLKConfig() function. - * - Enable RTC Clock using the RCC_RTCCLKCmd() function. - * - * =================================================================== - * RTC Driver: how to use it - * =================================================================== - * - Enable the RTC domain access (see description in the section above) - * - Configure the RTC Prescaler (Asynchronous and Synchronous) and - * RTC hour format using the RTC_Init() function. - * - * Time and Date configuration - * =========================== - * - To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - * and RTC_SetDate() functions. - * - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() - * functions. - * - Use the RTC_DayLightSavingConfig() function to add or sub one - * hour to the RTC Calendar. - * - * Alarm configuration - * =================== - * - To configure the RTC Alarm use the RTC_SetAlarm() function. - * - Enable the selected RTC Alarm using the RTC_AlarmCmd() function - * - To read the RTC Alarm, use the RTC_GetAlarm() function. - * - * RTC Wakeup configuration - * ======================== - * - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - * function. - * - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() - * function - * - Enable the RTC WakeUp using the RTC_WakeUpCmd() function - * - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - * function. - * - * Outputs configuration - * ===================== - * The RTC has 2 different outputs: - * - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - * and WaKeUp signals. - * To output the selected RTC signal on RTC_AF1 pin, use the - * RTC_OutputConfig() function. - * - AFO_CALIB: this output is used to manage the RTC Clock divided - * by 64 (512Hz) signal. - * To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd() - * function. - * - * Coarse Calibration configuration - * ================================= - * - Configure the RTC Coarse Calibration Value and the corresponding - * sign using the RTC_CoarseCalibConfig() function. - * - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() - * function - * - * TimeStamp configuration - * ======================= - * - Configure the RTC_AF1 trigger and enables the RTC TimeStamp - * using the RTC_TimeStampCmd() function. - * - To read the RTC TimeStamp Time and Date register, use the - * RTC_GetTimeStamp() function. - * - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - * or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - * RTC_TAFCR register. You can use the RTC_TamperPinSelection() - * function to select the corresponding pin. - * - * Tamper configuration - * ==================== - * - Configure the RTC Tamper trigger using the RTC_TamperConfig() - * function. - * - Enable the RTC Tamper using the RTC_TamperCmd() function. - * - The TIMESTAMP alternate function can be mapped to either RTC_AF1 - * or RTC_AF2 depending on the value of the TSINSEL bit in the - * RTC_TAFCR register. You can use the RTC_TimeStampPinSelection() - * function to select the corresponding pin. - * - * Backup Data Registers configuration - * =================================== - * - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - * function. - * - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - * function. - * - * =================================================================== - * RTC and low power modes - * =================================================================== - * The MCU can be woken up from a low power mode by an RTC alternate - * function. - * The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - * RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - * These RTC alternate functions can wake up the system from the Stop - * and Standby lowpower modes. - * The system can also wake up from low power modes without depending - * on an external interrupt (Auto-wakeup mode), by using the RTC alarm - * or the RTC wakeup events. - * The RTC provides a programmable time base for waking up from the - * Stop or Standby mode at regular intervals. - * Wakeup from STOP and Standby modes is possible only when the RTC - * clock source is LSE or LSI. - * - * =================================================================== - * Selection of RTC_AF1 alternate functions - * =================================================================== - * The RTC_AF1 pin (PC13) can be used for the following purposes: - * - AFO_ALARM output - * - AFO_CALIB output - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +-------------------------------------------------------------------------------------------------------------+ - * | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | | | selection | selection |Configuration | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Alarm out | | | | | Don't | Don't | | - * | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Calibration out | | | | | Don't | Don't | | - * | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | | | Don't | | - * | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | | | - * | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - * | floating | | | | | | | | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | | | Don't | | | - * | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - * +-------------------------------------------------------------------------------------------------------------+ - * - * - * =================================================================== - * Selection of RTC_AF2 alternate functions - * =================================================================== - * The RTC_AF2 pin (PI8) can be used for the following purposes: - * - AFI_TAMPER - * - AFI_TIMESTAMP - * - * +---------------------------------------------------------------------------------------+ - * | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - * | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - * | and function | | | selection | selection |Configuration | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TAMPER input | | | | Don't | | - * | floating | 1 | 0 | 1 | care | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP and | | | | | | - * | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - * | floating | | | | | | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | TIMESTAMP input | | | Don't | | | - * | floating | 0 | 1 | care | 1 | Don't care | - * |-----------------|-----------|--------------|------------|--------------|--------------| - * | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - * +---------------------------------------------------------------------------------------+ - * - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_rtc.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F )) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - 1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - - When both prescalers are used, it is recommended to configure the asynchronous - prescaler to a high value to minimize consumption. - - 2. All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - 3. To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - 4. To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - Time and Date configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - Alarms (Alarm A and Alarm B) configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - WakeUp Timer configuration functions - =============================================================================== - - This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - Daylight Saving configuration functions - =============================================================================== - - This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - Output pin Configuration function - =============================================================================== - - This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Coarse Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - Coarse Calibration configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - TimeStamp configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - Tampers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1. - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - Backup Data Registers configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - =============================================================================== - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin. - * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - All RTC interrupts are connected to the EXTI controller. - - - To enable the RTC Alarm interrupt, the following sequence is required: - - Configure and enable the EXTI Line 17 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - - To enable the RTC Wakeup interrupt, the following sequence is required: - - Configure and enable the EXTI Line 22 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - - To enable the RTC Tamper interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - - To enable the RTC TimeStamp interrupt, the following sequence is required: - - Configure and enable the EXTI Line 21 in interrupt mode and select the rising - edge sensitivity using the EXTI_Init() function. - - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init() - function. - - Configure the RTC to detect the RTC time-stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c deleted file mode 100644 index a4fafe50a..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_sdio.c +++ /dev/null @@ -1,1010 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_sdio.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * - Initialization and Configuration - * - Command path state machine (CPSM) management - * - Data path state machine (DPSM) management - * - SDIO IO Cards mode management - * - CE-ATA mode management - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output - * of PLL (PLL48CLK). Before to start working with SDIO peripheral - * make sure that the PLL is well configured. - * The SDIO peripheral uses two clock signals: - * - SDIO adapter clock (SDIOCLK = 48 MHz) - * - APB2 bus clock (PCLK2) - * PCLK2 and SDIO_CK clock frequencies must respect the following condition: - * Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - * - * 2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - * - * 3. According to the SDIO mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. - * The I/O can be one of the following configurations: - * - 1-bit data length: SDIO_CMD, SDIO_CK and D0. - * - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - * - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - * - * 4. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - * hardware, flow control and the Clock Divider using the SDIO_Init() - * function. - * - * 6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - * function. - * - * 7. Enable the clock using the SDIO_ClockCmd() function. - * - * 8. Enable the NVIC and the corresponding interrupt using the function - * SDIO_ITConfig() if you need to use interrupt mode. - * - * 9. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SDIO_DMACmd() function - * - * 10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * 11. To control the CPSM (Command Path State Machine) and send - * commands to the card use the SDIO_SendCommand(), - * SDIO_GetCommandResponse() and SDIO_GetResponse() functions. - * First, user has to fill the command structure (pointer to - * SDIO_CmdInitTypeDef) according to the selected command to be sent. - * The parameters that should be filled are: - * - Command Argument - * - Command Index - * - Command Response type - * - Command Wait - * - CPSM Status (Enable or Disable) - * - * To check if the command is well received, read the SDIO_CMDRESP - * register using the SDIO_GetCommandResponse(). - * The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - * SDIO_GetResponse() function. - * - * 12. To control the DPSM (Data Path State Machine) and send/receive - * data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - * SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - * - * Read Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be from card (To SDIO) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to receive the data from the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Read command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * Write Operations - * --------------- - * a) First, user has to fill the data structure (pointer to - * SDIO_DataInitTypeDef) according to the selected data type to - * be received. - * The parameters that should be filled are: - * - Data TimeOut - * - Data Length - * - Data Block size - * - Data Transfer direction: should be to card (To CARD) - * - Data Transfer mode - * - DPSM Status (Enable or Disable) - * - * b) Configure the SDIO resources to send the data to the card - * according to selected transfer mode (Refer to Step 8, 9 and 10). - * - * c) Send the selected Write command (refer to step 11). - * - * d) Use the SDIO flags/interrupts to check the transfer status. - * - * - * @endverbatim - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_sdio.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - Command path state machine (CPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - Data path state machine (DPSM) management functions - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - SDIO IO Cards mode management functions - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - CE-ATA mode management functions - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c deleted file mode 100644 index df2f66610..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_spi.c +++ /dev/null @@ -1,1183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_spi.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * - Initialization and Configuration - * - Data transfers functions - * - Hardware CRC Calculation - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the following functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - * RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3. - * - * 2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - * function. - * In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO - * clock should also be enabled. - * - * 3. Peripherals alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * In I2S mode, if an external clock source is used then the I2S CKIN pin - * should be also configured in Alternate function Push-pull pull-up mode. - * - * 4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - * Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - * function. - * In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - * frequency and Polarity using I2S_Init() function. - * For I2S mode, make sure that either: - * - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), - * RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY). - * or - * - External clock source is configured using the function - * RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant - * I2S_EXTERNAL_CLOCK_VAL in the stm32f2xx_conf.h file. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * SPI_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using SPI_I2S_DMACmd() function - * - * 7. Enable the SPI using the SPI_Cmd() function or enable the I2S using - * I2S_Cmd(). - * - * 8. Enable the DMA using the DMA_Cmd() function when using DMA mode. - * - * 9. Optionally, you can enable/configure the following parameters without - * re-initialization (i.e there is no need to call again SPI_Init() function): - * - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - * is programmed as Data direction parameter using the SPI_Init() function - * it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - * using the SPI_BiDirectionalLineConfig() function. - * - When SPI_NSS_Soft is selected as Slave Select Management parameter - * using the SPI_Init() function it can be possible to manage the - * NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - * - Reconfigure the data size using the SPI_DataSizeConfig() function - * - Enable or disable the SS output using the SPI_SSOutputCmd() function - * - * 10. To use the CRC Hardware calculation feature refer to the Peripheral - * CRC hardware Calculation subsection. - * - * - * @note This driver supports only the I2S clock scheme available in Silicon - * RevisionB and RevisionY. - * - * @note In I2S mode: if an external clock is used as source clock for the I2S, - * then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should - * be enabled and set to the value of the source clock frequency (in Hz). - * - * @note In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - * just after calling the function SPI_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "../inc/stm32f2xx_spi.h" -#include "../inc/stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This section provides a set of functions allowing to initialize the SPI Direction, - SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud - Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - The SPI_Init() function follows the SPI configuration procedures for Master mode - and Slave mode (details for these procedures are available in reference manual - (RM0033)). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else - { - if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f2xx_conf.h should be enabled and set - * to the value of the the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f2xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg; -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2 or 3 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI data transfers - - In reception, data are received and then stored into an internal Rx buffer while - In transmission, data are first stored into an internal Tx buffer before being - transmitted. - - The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - Hardware CRC Calculation functions - =============================================================================== - - This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - SPI communication using CRC is possible through the following procedure: - 1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - 2. Enable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the SPI using the SPI_Cmd() function - 4. Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - 5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - -@note It is advised not to read the calculated CRC values during the communication. - -@note When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - -@note With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - -@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - -@note When the STM32F2xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - -@note When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - -@note Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - -@note To clear the CRC, follow the procedure below: - 1. Disable SPI using the SPI_Cmd() function - 2. Disable the CRC calculation using the SPI_CalculateCRC() function. - 3. Enable the CRC calculation using the SPI_CalculateCRC() function. - 4. Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2 or 3 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - 1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - 3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - 4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - 5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur - 6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - 7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - 8. I2S_FLAG_UDR: to indicate an Underrun error occurs. - 9. I2S_FLAG_CHSIDE: to indicate Channel Side. - -@note Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - In this Mode it is advised to use the following functions: - - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - Pending Bits: - ------------- - 1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - 2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - 3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - 4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - 5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur - 6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - 7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - Interrupt Source: - ----------------- - 1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - 2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - In this Mode it is advised to use the following functions: - - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - DMA Mode - ======== - In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - 1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 - * in SPI mode or 2 or 3 in I2S mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c deleted file mode 100644 index ba87ffa52..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_syscfg.c +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_syscfg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * - * This driver provides functions for: - * - * 1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - * - * 2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - * - * 3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - * - * @note SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - * using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_syscfg.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * - * @note In remap mode, the FSMC addressing is fixed to the remap address area only - * (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not - * accessible. The FSMC remap function must be disabled to allows addressing - * other memory devices through the FSMC and/or to access FSMC control - * registers. - * - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..I). - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11). - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c deleted file mode 100644 index f16077088..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_tim.c +++ /dev/null @@ -1,3358 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_tim.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * - TimeBase management - * - Output Compare management - * - Input Capture management - * - Advanced-control timers (TIM1 and TIM8) specific features - * - Interrupts, DMA and flags management - * - Clocks management - * - Synchronization management - * - Specific interface management - * - Specific remapping management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * This driver provides functions to configure and program the TIM - * of all STM32F2xx devices. - * These functions are split in 9 groups: - * - * 1. TIM TimeBase management: this group includes all needed functions - * to configure the TM Timebase unit: - * - Set/Get Prescaler - * - Set/Get Autoreload - * - Counter modes configuration - * - Set Clock division - * - Select the One Pulse mode - * - Update Request Configuration - * - Update Disable Configuration - * - Auto-Preload Configuration - * - Enable/Disable the counter - * - * 2. TIM Output Compare management: this group includes all needed - * functions to configure the Capture/Compare unit used in Output - * compare mode: - * - Configure each channel, independently, in Output Compare mode - * - Select the output compare modes - * - Select the Polarities of each channel - * - Set/Get the Capture/Compare register values - * - Select the Output Compare Fast mode - * - Select the Output Compare Forced mode - * - Output Compare-Preload Configuration - * - Clear Output Compare Reference - * - Select the OCREF Clear signal - * - Enable/Disable the Capture/Compare Channels - * - * 3. TIM Input Capture management: this group includes all needed - * functions to configure the Capture/Compare unit used in - * Input Capture mode: - * - Configure each channel in input capture mode - * - Configure Channel1/2 in PWM Input mode - * - Set the Input Capture Prescaler - * - Get the Capture/Compare values - * - * 4. Advanced-control timers (TIM1 and TIM8) specific features - * - Configures the Break input, dead time, Lock level, the OSSI, - * the OSSR State and the AOE(automatic output enable) - * - Enable/Disable the TIM peripheral Main Outputs - * - Select the Commutation event - * - Set/Reset the Capture Compare Preload Control bit - * - * 5. TIM interrupts, DMA and flags management - * - Enable/Disable interrupt sources - * - Get flags status - * - Clear flags/ Pending bits - * - Enable/Disable DMA requests - * - Configure DMA burst mode - * - Select CaptureCompare DMA request - * - * 6. TIM clocks management: this group includes all needed functions - * to configure the clock controller unit: - * - Select internal/External clock - * - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - * - * 7. TIM synchronization management: this group includes all needed - * functions to configure the Synchronization unit: - * - Select Input Trigger - * - Select Output Trigger - * - Select Master Slave Mode - * - ETR Configuration when used as external trigger - * - * 8. TIM specific interface management, this group includes all - * needed functions to use the specific TIM interface: - * - Encoder Interface Configuration - * - Select Hall Sensor - * - * 9. TIM specific remapping management includes the Remapping - * configuration of specific timers - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_tim.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - TimeBase management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Timing(Time base) Mode - =================================================================== - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Fill the TIM_TimeBaseInitStruct with the desired parameters. - - 3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - 4. Enable the NVIC if you need to generate the update interrupt. - - 5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - 6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediatly */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - Output Compare management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Output Compare Mode - =================================================================== - To use the Timer in Output Compare mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_OCInitStruct with the desired parameters including: - - The TIM Output Compare mode: TIM_OCMode - - TIM Output State: TIM_OutputState - - TIM Pulse value: TIM_Pulse - - TIM Output Compare Polarity : TIM_OCPolarity - - 4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the - corresponding configuration - - 5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - Note2: In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - Note3: If the corresponding interrupt or DMA request are needed, the user should: - 1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - 2. Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - Input Capture management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in Input Capture Mode - =================================================================== - To use the Timer in Input Capture mode, the following steps are mandatory: - - 1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - 2. Configure the TIM pins by configuring the corresponding GPIO pins - - 2. Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - - Autoreload value = 0xFFFF - - Prescaler value = 0x0000 - - Counter mode = Up counting - - Clock Division = TIM_CKD_DIV1 - - 3. Fill the TIM_ICInitStruct with the desired parameters including: - - TIM Channel: TIM_Channel - - TIM Input Capture polarity: TIM_ICPolarity - - TIM Input Capture selection: TIM_ICSelection - - TIM Input Capture Prescaler: TIM_ICPrescaler - - TIM Input CApture filter value: TIM_ICFilter - - 4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the - corresponding configuration and to measure only frequency or duty cycle of the input signal, - or, - Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the - corresponding configuration and to measure the frequency and the duty cycle of the input signal - - 5. Enable the NVIC or the DMA to read the measured frequency. - - 6. Enable the corresponding interrupt (or DMA request) to read the Captured value, - using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - 7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - 8. Use TIM_GetCapturex(TIMx); to read the captured value. - - Note1: All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - Advanced-control timers (TIM1 and TIM8) specific features - =============================================================================== - - =================================================================== - TIM Driver: how to use the Break feature - =================================================================== - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - 1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - 2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - 3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - 4. Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - Interrupts, DMA and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - Clocks management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - Synchronization management functions - =============================================================================== - - =================================================================== - TIM Driver: how to use it in synchronization Mode - =================================================================== - Case of two/several Timers - ************************** - 1. Configure the Master Timers using the following functions: - - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - Case of Timers and external trigger(ETR pin) - ******************************************** - 1. Configure the External trigger using this function: - - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - 2. Configure the Slave Timers using the following functions: - - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - Specific interface management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - Specific remapping management function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c deleted file mode 100644 index 8f41b581d..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_usart.c +++ /dev/null @@ -1,1469 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_usart.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * - Initialization and Configuration - * - Data transfers - * - Multi-Processor Communication - * - LIN mode - * - Half-duplex mode - * - Smartcard mode - * - IrDA mode - * - DMA transfers management - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable peripheral clock using the follwoing functions - * RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - * RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5. - * - * 2. According to the USART mode, enable the GPIO clocks using - * RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - * or/and SCLK). - * - * 3. Peripheral's alternate function: - * - Connect the pin to the desired peripherals' Alternate - * Function (AF) using GPIO_PinAFConfig() function - * - Configure the desired pin in alternate function by: - * GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - * - Select the type, pull-up/pull-down and output speed via - * GPIO_PuPd, GPIO_OType and GPIO_Speed members - * - Call GPIO_Init() function - * - * 4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - * flow control and Mode(Receiver/Transmitter) using the USART_Init() - * function. - * - * 5. For synchronous mode, enable the clock and program the polarity, - * phase and last bit using the USART_ClockInit() function. - * - * 5. Enable the NVIC and the corresponding interrupt using the function - * USART_ITConfig() if you need to use interrupt mode. - * - * 6. When using the DMA mode - * - Configure the DMA using DMA_Init() function - * - Active the needed channel Request using USART_DMACmd() function - * - * 7. Enable the USART using the USART_Cmd() function. - * - * 8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. - * - * Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - * for more details - * - * In order to reach higher communication baudrates, it is possible to - * enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - * This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - * and before calling the function USART_Init(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_usart.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - Initialization and Configuration functions - =============================================================================== - - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - - For the asynchronous mode only these parameters can be configured: - - Baud Rate - - Word Length - - Stop Bit - - Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - - Hardware flow control - - Receiver/transmitter modes - - The USART_Init() function follows the USART asynchronous configuration procedure - (details for the procedure are available in reference manual (RM0033)). - - - For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - - USART Clock Enabled - - USART polarity - - USART phase - - USART LastBit - - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else - { - if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - Data transfers functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART data - transfers. - - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - Multi-Processor Communication functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - - For instance one of the USARTs can be the master, its TX output is connected to - the RX input of the other USART. The others are slaves, their respective TX outputs - are logically ANDed together and connected to the RX input of the master. - - USART multiprocessor communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - 4. Enable the USART using the USART_Cmd() function. - 5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - LIN mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - - Only this LIN Feature is supported by the USART IP: - - LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - - USART LIN Master transmitter communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Enable the LIN mode using the USART_LINCmd() function. - 4. Send the break character using USART_SendBreak() function. - - USART LIN Master receiver communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - 4. Enable the LIN mode using the USART_LINCmd() function. - - -@note In LIN mode, the following bits must be kept cleared: - - CLKEN in the USART_CR2 register, - - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - Half-duplex mode function - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - - USART Half duplex communication is possible through the following procedure: - 1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - 2. Configures the USART address using the USART_SetAddress() function. - 3. Enable the USART using the USART_Cmd() function. - 4. Enable the half duplex mode using USART_HalfDuplexCmd() function. - - -@note The RX pin is no longer used -@note In Half-duplex mode the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register. - - SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - Smartcard mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - - Smartcard communication is possible through the following procedure: - 1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - 2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - 3. Program the USART clock using the USART_ClockInit() function as following: - - USART Clock enabled - - USART CPOL Low - - USART CPHA on first edge - - USART Last Bit Clock Enabled - 4. Program the Smartcard interface using the USART_Init() function as following: - - Word Length = 9 Bits - - 1.5 Stop Bit - - Even parity - - BaudRate = 12096 baud - - Hardware flow control disabled (RTS and CTS signals) - - Tx and Rx enabled - 5. Optionally you can enable the parity error interrupt using the USART_ITConfig() - function - 6. Enable the USART using the USART_Cmd() function. - 7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - 8. Enable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@note It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. -@note In smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register. - - HDSEL and IREN bits in the USART_CR3 register. -@note Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - IrDA mode functions - =============================================================================== - - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - IrDA communication is possible through the following procedure: - 1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - 2. Enable the USART using the USART_Cmd() function. - 3. Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - 4. Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - 5. Enable the IrDA using the USART_IrDACmd() function. - -@note A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. -@note The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). -@note In IrDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register. - - SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - DMA transfers management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - Polling Mode - ============= - In Polling Mode, the SPI communication can be managed by 10 flags: - 1. USART_FLAG_TXE : to indicate the status of the transmit buffer register - 2. USART_FLAG_RXNE : to indicate the status of the receive buffer register - 3. USART_FLAG_TC : to indicate the status of the transmit operation - 4. USART_FLAG_IDLE : to indicate the status of the Idle Line - 5. USART_FLAG_CTS : to indicate the status of the nCTS input - 6. USART_FLAG_LBD : to indicate the status of the LIN break detection - 7. USART_FLAG_NE : to indicate if a noise error occur - 8. USART_FLAG_FE : to indicate if a frame error occur - 9. USART_FLAG_PE : to indicate if a parity error occur - 10. USART_FLAG_ORE : to indicate if an Overrun error occur - - In this Mode it is advised to use the following functions: - - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - Interrupt Mode - =============== - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - Pending Bits: - ------------- - 1. USART_IT_TXE : to indicate the status of the transmit buffer register - 2. USART_IT_RXNE : to indicate the status of the receive buffer register - 3. USART_IT_TC : to indicate the status of the transmit operation - 4. USART_IT_IDLE : to indicate the status of the Idle Line - 5. USART_IT_CTS : to indicate the status of the nCTS input - 6. USART_IT_LBD : to indicate the status of the LIN break detection - 7. USART_IT_NE : to indicate if a noise error occur - 8. USART_IT_FE : to indicate if a frame error occur - 9. USART_IT_PE : to indicate if a parity error occur - 10. USART_IT_ORE : to indicate if an Overrun error occur - - Interrupt Source: - ----------------- - 1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - 2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - 3. USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - 4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - 5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - 6. USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - 7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. - 8. USART_IT_ERR : specifies the interrupt source for the errors interrupt. - -@note Some parameters are coded in order to use them as interrupt source or as pending bits. - - In this Mode it is advised to use the following functions: - - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - DMA Mode - ======== - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - 1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - 2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - In this Mode it is advised to use the following function: - - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS : CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD : LIN Break detection interrupt - * @arg USART_IT_TXE : Transmit Data Register empty interrupt - * @arg USART_IT_TC : Transmission complete interrupt - * @arg USART_IT_RXNE : Receive Data register not empty interrupt - * @arg USART_IT_IDLE : Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE : Noise Error interrupt - * @arg USART_IT_FE : Framing Error interrupt - * @arg USART_IT_PE : Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c b/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c deleted file mode 100644 index 4d715dcba..000000000 --- a/radio/src/thirdparty/STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/src/stm32f2xx_wwdg.c +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f2xx_wwdg.c - * @author MCD Application Team - * @version V1.1.2 - * @date 05-March-2012 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * - Prescaler, Refresh window and Counter configuration - * - WWDG activation - * - Interrupts and flags management - * - * @verbatim - * - * =================================================================== - * WWDG features - * =================================================================== - * - * Once enabled the WWDG generates a system reset on expiry of a programmed - * time period, unless the program refreshes the counter (downcounter) - * before to reach 0x3F value (i.e. a reset is generated when the counter - * value rolls over from 0x40 to 0x3F). - * An MCU reset is also generated if the counter value is refreshed - * before the counter has reached the refresh window value. This - * implies that the counter must be refreshed in a limited window. - * - * Once enabled the WWDG cannot be disabled except by a system reset. - * - * WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - * reset occurs. - * - * The WWDG counter input clock is derived from the APB clock divided - * by a programmable prescaler. - * - * WWDG counter clock = PCLK1 / Prescaler - * WWDG timeout = (WWDG counter clock) * (counter value) - * - * Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms - * - * =================================================================== - * How to use this driver - * =================================================================== - * 1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - * - * 2. Configure the WWDG prescaler using WWDG_SetPrescaler() function - * - * 3. Configure the WWDG refresh window using WWDG_SetWindowValue() function - * - * 4. Set the WWDG counter value and start it using WWDG_Enable() function. - * When the WWDG is enabled the counter value should be configured to - * a value greater than 0x40 to prevent generating an immediate reset. - * - * 5. Optionally you can enable the Early wakeup interrupt which is - * generated when the counter reach 0x40. - * Once enabled this interrupt cannot be disabled except by a system reset. - * - * 6. Then the application program must refresh the WWDG counter at regular - * intervals during normal operation to prevent an MCU reset, using - * WWDG_SetCounter() function. This operation must occur only when - * the counter value is lower than the refresh window value, - * programmed using WWDG_SetWindowValue(). - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2012 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f2xx_wwdg.h" -#include "stm32f2xx_rcc.h" - -/** @addtogroup STM32F2xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - Prescaler, Refresh window and Counter configuration functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - WWDG activation function - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - Interrupts and flags management functions - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h deleted file mode 100644 index 813ad5c9a..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h +++ /dev/null @@ -1,12068 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx.h - * @author MCD Application Team - * @version V1.8.0 - * @date 09-November-2016 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. - * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32F4xx devices. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The device used in the target application - * - To use or not the peripheral�s drivers in application code(i.e. - * code will be based on direct access to peripheral�s registers - * rather than drivers API), this option is controlled by - * "#define USE_STDPERIPH_DRIVER" - * - To change few application-specific parameters such as the HSE - * crystal frequency - * - Data structures and the address mapping for all peripherals - * - Peripherals registers declarations and bits definition - * - Macros to access peripheral�s registers hardware - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx - * @{ - */ - -#ifndef __STM32F4xx_H -#define __STM32F4xx_H - -#define assert_param(xx) - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/* Uncomment the line below according to the target STM32 device used in your - application - */ - -#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ - !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx) - /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG, - STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE, - STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */ - - /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II, - STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */ - - /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, - STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI, - STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI, - STM32F439IG and STM32F439II Devices */ - - /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC, - STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */ - - /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */ - - /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */ - - /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ, - STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT, - STM32F412REY and STM32F412RGY Devices */ - - /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT, - STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ, - STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT, - STM32F423VHH and STM32F423ZHJ devices */ - - /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC - and STM32F446ZE Devices */ - - /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG, - STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */ - -#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx && STM32F469_479xx */ - -/* Old STM32F40XX definition, maintained for legacy purpose */ -#ifdef STM32F40XX - #define STM32F40_41xxx -#endif /* STM32F40XX */ - -/* Old STM32F427X definition, maintained for legacy purpose */ -#ifdef STM32F427X - #define STM32F427_437xx -#endif /* STM32F427X */ - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ - -#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \ - !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx) - #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)" -#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx && STM32F469_479xx */ - -#if !defined (USE_STDPERIPH_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_STDPERIPH_DRIVER */ -#endif /* USE_STDPERIPH_DRIVER */ - -/** - * @brief In the following line adjust the value of External High Speed oscillator (HSE) - used in your application - - Tip: To avoid modifying this file each time you need to use different HSE, you - can define the HSE value in your toolchain compiler preprocessor. - */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \ - defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) - #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #endif /* HSE_VALUE */ -#elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) - #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* HSE_VALUE */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ -/** - * @brief In the following line adjust the External High Speed oscillator (HSE) Startup - Timeout value - */ -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT ((uint16_t)0x05000) /*!< Time out for HSE start up */ -#endif /* HSE_STARTUP_TIMEOUT */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief STM32F4XX Standard Peripherals Library version number V1.8.0 - */ -#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */ -#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ - |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ - |(__STM32F4XX_STDPERIPH_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ -#define __CM4_REV 0x0001 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */ -#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ - -/** - * @brief STM32F4XX Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum IRQn -{ -/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - -#if defined(STM32F40_41xxx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81 /*!< FPU global interrupt */ -#endif /* STM32F40_41xxx */ - -#if defined(STM32F427_437xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F427_437xx */ - -#if defined(STM32F429_439xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */ -#endif /* STM32F429_439xx */ - -#if defined(STM32F410xx) - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - RNG_IRQn = 80, /*!< RNG global Interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ - FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */ - LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */ -#endif /* STM32F410xx */ - -#if defined(STM32F401xx) || defined(STM32F411xE) - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ -#if defined(STM32F401xx) - SPI4_IRQn = 84 /*!< SPI4 global Interrupt */ -#endif /* STM32F411xE */ -#if defined(STM32F411xE) - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85 /*!< SPI5 global Interrupt */ -#endif /* STM32F411xE */ -#endif /* STM32F401xx || STM32F411xE */ - -#if defined(STM32F469_479xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ - QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */ - DSI_IRQn = 92 /*!< DSI global Interrupt */ -#endif /* STM32F469_479xx */ - -#if defined(STM32F446xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ - QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ - CEC_IRQn = 93, /*!< QuadSPI global Interrupt */ - SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */ - FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */ - FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */ -#endif /* STM32F446xx */ - -#if defined(STM32F412xG) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FSMC_IRQn = 48, /*!< FSMC global Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - TIM6_IRQn = 54, /*!< TIM6 global interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - RNG_IRQn = 80, /*!< RNG global Interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ - FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ - FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */ -#endif /* STM32F412xG */ - -#if defined(STM32F413_423xx) - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - SDIO_IRQn = 49, /*!< SDIO global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC1&2 global Interrupt */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */ - DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */ - CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */ - CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */ - CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */ - RNG_IRQn = 80, /*!< RNG global Interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SAI1_IRQn = 87, /*!< Serial Audio Interface 1 global interrupt */ - UART9_IRQn = 88, /*!< UART9 global Interrupt */ - UART10_IRQn = 89, /*!< UART10 global Interrupt */ - QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */ - FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */ - FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */ - LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */ - DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */ - DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */ - DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */ - DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */ -#endif /* STM32F413_423xx */ -} IRQn_Type; - -/** - * @} - */ - -#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ -#include "system_stm32f4xx.h" -#include - -/** @addtogroup Exported_types - * @{ - */ -/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */ -typedef int32_t s32; -typedef int16_t s16; -typedef int8_t s8; - -typedef const int32_t sc32; /*!< Read Only */ -typedef const int16_t sc16; /*!< Read Only */ -typedef const int8_t sc8; /*!< Read Only */ - -typedef __IO int32_t vs32; -typedef __IO int16_t vs16; -typedef __IO int8_t vs8; - -typedef __I int32_t vsc32; /*!< Read Only */ -typedef __I int16_t vsc16; /*!< Read Only */ -typedef __I int8_t vsc8; /*!< Read Only */ - -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -typedef const uint32_t uc32; /*!< Read Only */ -typedef const uint16_t uc16; /*!< Read Only */ -typedef const uint8_t uc8; /*!< Read Only */ - -typedef __IO uint32_t vu32; -typedef __IO uint16_t vu16; -typedef __IO uint8_t vu8; - -typedef __I uint32_t vuc32; /*!< Read Only */ -typedef __I uint16_t vuc16; /*!< Read Only */ -typedef __I uint8_t vuc8; /*!< Read Only */ - -typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; - -typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; - -/** - * @} - */ - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -#if defined(STM32F446xx) -/** - * @brief Consumer Electronics Control - */ -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; -#endif /* STM32F446xx */ - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - -#if defined(STM32F412xG) || defined(STM32F413_423xx) -/** - * @brief DFSDM module registers - */ -typedef struct -{ - __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */ - __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */ - __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */ - __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */ - __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */ - __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */ - __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */ - __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */ - __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */ - __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */ - __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */ - __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */ - __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */ - __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */ - __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */ -} DFSDM_Filter_TypeDef; - -/** - * @brief DFSDM channel configuration registers - */ -typedef struct -{ - __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */ - __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */ - __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and - short circuit detector register, Address offset: 0x08 */ - __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */ - __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */ -} DFSDM_Channel_TypeDef; - -/* Legacy Defines */ -#define DFSDM_TypeDef DFSDM_Filter_TypeDef -#endif /* STM32F412xG || STM32F413_423xx */ -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - -#if defined(STM32F469_479xx) -/** - * @brief DSI Controller - */ - -typedef struct -{ - __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ - __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ - __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ - __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ - __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ - __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ - __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ - uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ - __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ - __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ - __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ - __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ - __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ - __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ - __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ - __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ - __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ - __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ - __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ - __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ - __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ - __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ - __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ - __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ - __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ - __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ - __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ - __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ - __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ - __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ - __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ - __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ - __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ - __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ - __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ - __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ - __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ - __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ - __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ - uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ - __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ - uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ - __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ - uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ - __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ - __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ - uint32_t RESERVED5; /*!< Reserved, 0x114 */ - __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ - uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ - __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ - __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ - __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ - __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ - __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ - __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ - __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ - __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ - __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ - __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ - uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ - __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ - uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ - __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ - __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ - __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ - __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ - __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ - uint32_t RESERVED9; /*!< Reserved, 0x414 */ - __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ - uint32_t RESERVED10; /*!< Reserved, 0x42C */ - __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ -} DSI_TypeDef; -#endif /* STM32F469_479xx */ - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1[2]; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - uint32_t RESERVED9[565]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ -} FLASH_TypeDef; - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -/** - * @brief Flexible Static Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FSMC_Bank1_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FSMC_Bank1E_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FSMC_Bank2_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FSMC_Bank3_TypeDef; - -/** - * @brief Flexible Static Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FSMC_Bank4_TypeDef; -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank2 - */ - -typedef struct -{ - __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */ - __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */ - __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */ - __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */ - uint32_t RESERVED0; /*!< Reserved, 0x70 */ - __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */ -} FMC_Bank2_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */ - __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */ - __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */ - __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank4 - */ - -typedef struct -{ - __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */ - __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */ - __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */ - __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */ - __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */ -} FMC_Bank4_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */ - __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ -#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) - uint32_t RESERVED; /*!< Reserved, 0x18 */ - __IO uint32_t CFGR2; /*!< Reserved, 0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */ - __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */ -#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -#endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */ -#if defined(STM32F413_423xx) - __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */ -#endif /* STM32F413_423xx */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ - uint16_t RESERVED9; /*!< Reserved, 0x26 */ -} I2C_TypeDef; - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */ -}FMPI2C_TypeDef; -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ -} IWDG_TypeDef; - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ - __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ -} PWR_TypeDef; - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ - __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */ - __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ - uint32_t RESERVED7; /*!< Reserved, 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ -} SDIO_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ -} SPI_TypeDef; - -#if defined(STM32F446xx) -/** - * @brief SPDIFRX Interface - */ -typedef struct -{ - __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ - uint16_t RESERVED0; /*!< Reserved, 0x06 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ - uint16_t RESERVED1; /*!< Reserved, 0x0E */ - __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ - __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ - __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ - uint16_t RESERVED2; /*!< Reserved, 0x1A */ -} SPDIFRX_TypeDef; -#endif /* STM32F446xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief QUAD Serial Peripheral Interface - */ -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F446xx) -/** - * @brief SPDIF-RX Interface - */ -typedef struct -{ - __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ - uint16_t RESERVED0; /*!< Reserved, 0x06 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ - uint16_t RESERVED1; /*!< Reserved, 0x0E */ - __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ - __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ - __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ - uint16_t RESERVED2; /*!< Reserved, 0x1A */ -} SPDIF_TypeDef; -#endif /* STM32F446xx */ - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ - __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - uint16_t RESERVED7; /*!< Reserved, 0x1E */ - __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - uint16_t RESERVED8; /*!< Reserved, 0x22 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - uint16_t RESERVED9; /*!< Reserved, 0x2A */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - uint16_t RESERVED10; /*!< Reserved, 0x32 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - uint16_t RESERVED11; /*!< Reserved, 0x46 */ - __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - uint16_t RESERVED12; /*!< Reserved, 0x4A */ - __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - uint16_t RESERVED13; /*!< Reserved, 0x4E */ - __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */ - uint16_t RESERVED14; /*!< Reserved, 0x52 */ -} TIM_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */ - uint16_t RESERVED0; /*!< Reserved, 0x02 */ - __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ - uint16_t RESERVED2; /*!< Reserved, 0x0A */ - __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ - uint16_t RESERVED3; /*!< Reserved, 0x0E */ - __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ - uint16_t RESERVED4; /*!< Reserved, 0x12 */ - __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ - uint16_t RESERVED5; /*!< Reserved, 0x16 */ - __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ - uint16_t RESERVED6; /*!< Reserved, 0x1A */ -} USART_TypeDef; - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/** - * @brief Crypto Processor - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */ - __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */ - __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */ - __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */ - __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */ - __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */ - __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */ - __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */ - __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */ - __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */ - __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */ - __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */ - __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */ - __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */ - __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */ - __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */ - __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */ - __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */ - __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */ - __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */ - __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */ - __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */ - __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */ - __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */ - __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */ - __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */ - __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */ - __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */ - __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */ - __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */ - __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */ - __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */ - __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */ - __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */ -} CRYP_TypeDef; - -/** - * @brief HASH - */ - -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ - -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -#if defined(STM32F410xx) || defined(STM32F413_423xx) -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */ -} LPTIM_TypeDef; -#endif /* STM32F410xx || STM32F413_423xx */ -/** - * @} - */ - -/** @addtogroup Peripheral_memory_map - * @{ - */ - -#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */ -#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ -#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) -#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */ -#elif defined(STM32F469_479xx) -#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */ -#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */ -#elif defined(STM32F413_423xx) -#define SRAM2_BASE ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */ -#else /* STM32F411xE || STM32F410xx || STM32F412xG */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */ -#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */ - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */ -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */ -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */ -#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) -#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#elif defined(STM32F469_479xx) -#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */ -#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */ -#elif defined(STM32F413_423xx) -#define SRAM2_BB_BASE ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */ -#else /* STM32F411xE || STM32F410xx || STM32F412xG */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */ -#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */ -#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */ - -/* Legacy defines */ -#define SRAM_BASE SRAM1_BASE -#define SRAM_BB_BASE SRAM1_BB_BASE - - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) -#if defined(STM32F410xx) || defined(STM32F413_423xx) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400) -#endif /* STM32F410xx || STM32F413_423xx */ -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) -#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) -#if defined(STM32F446xx) -#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000) -#endif /* STM32F446xx */ -#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) -#if defined(STM32F413_423xx) -#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00) -#endif /* STM32F413_423xx */ -#if defined(STM32F446xx) -#define CEC_BASE (APB1PERIPH_BASE + 0x6C00) -#endif /* STM32F446xx */ -#define PWR_BASE (APB1PERIPH_BASE + 0x7000) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400) -#define UART9_BASE (APB2PERIPH_BASE + 0x1800U) -#define UART10_BASE (APB2PERIPH_BASE + 0x1C00U) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300) -#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024) -#if defined(STM32F446xx) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024) -#endif /* STM32F446xx */ -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x84) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) -#if defined(STM32F469_479xx) -#define DSI_BASE (APB2PERIPH_BASE + 0x6C00) -#endif /* STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000) -#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00) -#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20) -#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40) -#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60) -#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100) -#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180) -#define DFSDM1_0 ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE) -#define DFSDM1_1 ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE) -/* Legacy Defines */ -#define DFSDM0 DFSDM1_0 -#define DFSDM1 DFSDM1_1 -#if defined(STM32F413_423xx) -#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U) -#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U) -#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U) -#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U) -#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U) -#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U) -#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U) -#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U) -#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U) -#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U) -#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U) -#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U) -#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U) -#define DFSDM2_0 ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE) -#define DFSDM2_1 ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE) -#define DFSDM2_2 ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE) -#define DFSDM2_3 ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE) -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx */ - -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100) -#define ETH_PTP_BASE (ETH_BASE + 0x0700) -#define ETH_DMA_BASE (ETH_BASE + 0x1000) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000) - -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) -#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) -#define HASH_BASE (AHB2PERIPH_BASE + 0x60400) -#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800) - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -/*!< FSMC Bankx registers base address */ -#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) -#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) -#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) -#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) -#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) -#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) -#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -/* Debug MCU registers base address */ -#define DBGMCU_BASE ((uint32_t )0xE0042000) - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#if defined(STM32F446xx) -#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) -#endif /* STM32F446xx */ -#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ -#if defined(STM32F410xx) || defined(STM32F413_423xx) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#endif /* STM32F410xx || STM32F413_423xx */ -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#if defined(STM32F413_423xx) -#define CAN3 ((CAN_TypeDef *) CAN3_BASE) -#endif /* STM32F413_423xx */ -#if defined(STM32F446xx) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#endif /* STM32F446xx */ -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define UART9 ((USART_TypeDef *) UART9_BASE) -#define UART10 ((USART_TypeDef *) UART10_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define SDIO ((SDIO_TypeDef *) SDIO_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#if defined(STM32F446xx) -#define SAI2 ((SAI_TypeDef *) SAI2_BASE) -#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) -#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) -#endif /* STM32F446xx */ -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#if defined(STM32F469_479xx) -#define DSI ((DSI_TypeDef *)DSI_BASE) -#endif /* STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE) -#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE) -#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE) -#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE) -#define DFSDM1_Filter0 ((DFSDM_TypeDef *) DFSDM_Filter0_BASE) -#define DFSDM1_Filter1 ((DFSDM_TypeDef *) DFSDM_Filter1_BASE) -#if defined(STM32F413_423xx) -#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE) -#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE) -#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE) -#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE) -#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE) -#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE) -#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE) -#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE) -#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE) -#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE) -#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE) -#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE) -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx */ -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define CRYP ((CRYP_TypeDef *) CRYP_BASE) -#define HASH ((HASH_TypeDef *) HASH_BASE) -#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) -#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) -#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) -#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) -#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************** Bit definition for ADC_SR register ********************/ -#define ADC_SR_AWD ((uint8_t)0x01) /*!
© COPYRIGHT 2016 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** - * @brief Define to prevent recursive inclusion - */ -#ifndef __SYSTEM_STM32F4XX_H -#define __SYSTEM_STM32F4XX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup STM32F4xx_System_Includes - * @{ - */ - -/** - * @} - */ - - -/** @addtogroup STM32F4xx_System_Exported_types - * @{ - */ - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Exported_Functions - * @{ - */ - -extern void SystemInit(void); -extern void SystemCoreClockUpdate(void); -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__SYSTEM_STM32F4XX_H */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index 039cc3d66..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,136 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_common_tables.h -* -* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -//extern const q31_t realCoefAQ31[1024]; -//extern const q31_t realCoefBQ31[1024]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) -#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) -#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) -#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 ) -#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 ) -#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 ) -#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 ) -#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 ) -#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 ) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 ) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 726d06eb6..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,79 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_const_structs.h -* -* Description: This file has constant structs that are initialized for -* user convenience. For example, some can be given as -* arguments to the arm_cfft_f32() function. -* -* Target Processor: Cortex-M4/Cortex-M3 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. -* -------------------------------------------------------------------- */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h deleted file mode 100644 index e4b2f62e8..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7556 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2015 ARM Limited. All rights reserved. -* -* $Date: 19. March 2015 -* $Revision: V.1.4.5 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) - * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) - * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY - #elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED -#elif defined __GNUC__ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED -#elif defined __TASKING__ - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -//#define __CLZ __clz -//#endif - -//note: function can be removed when all toolchain support __CLZ for Cortex-M0 -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in >= 0.0f) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -//SMMLAR -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//SMMLA -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -//SMMLS -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) //Keil - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #ifdef ARM_MATH_CM4 - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__TASKING__) // TASKING - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h deleted file mode 100644 index cf2b5d66b..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,740 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M0 - @{ - */ - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000 - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)(IRQn) < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)(IRQn) < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 123cb400a..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,854 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex-M0+ - @{ - */ - -/* CMSIS CM0P definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ - __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x00) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000 - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0 - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if (__VTOR_PRESENT == 1) - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if (__VTOR_PRESENT == 1) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M0+ Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)(IRQn) < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)(IRQn) < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h deleted file mode 100644 index 092ee23da..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1693 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M3 - @{ - */ - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200 - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if (__CM3_REV < 0x0201) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h deleted file mode 100644 index 9749c27d2..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1858 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16 /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h deleted file mode 100644 index 83db95b5f..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h +++ /dev/null @@ -1,673 +0,0 @@ -/**************************************************************************//** - * @file core_cm4_simd.h - * @brief CMSIS Cortex-M4 SIMD Header File - * @version V3.20 - * @date 25. February 2013 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2013 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifdef __cplusplus - extern "C" { -#endif - -#ifndef __CORE_CM4_SIMD_H -#define __CORE_CM4_SIMD_H - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -#include - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLALD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLALDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SMLSLD(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -#define __SMLSLDX(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \ - (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ - - -/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ -/* not yet supported */ -/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ - - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CORE_CM4_SIMD_H */ - -#ifdef __cplusplus -} -#endif diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h deleted file mode 100755 index 842e323f6..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2397 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M7 - @{ - */ - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x07) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000 - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0 - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0 - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0 - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16 /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1]; - __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93]; - __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15]; - __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ - uint32_t RESERVED5[1]; - __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1]; - __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6]; - __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1]; - __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* Cache Level ID register */ -#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* Cache Type register */ -#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* Cache Size ID Register */ -#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register */ -#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* Instruction Tightly-Coupled Memory Control Register*/ -#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Registers */ -#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register */ -#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register */ -#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS control register */ -#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register */ -#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \fn uint32_t SCB_GetFPUType(void) - \brief get FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { - return 2UL; // Double + Single precision FPU - } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { - return 1UL; // Single precision FPU - } else { - return 0UL; // No FPU - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## Cache functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) - - -/** \brief Enable I-Cache - - The function turns on I-Cache - */ -__STATIC_INLINE void SCB_EnableICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; // invalidate I-Cache - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable I-Cache - - The function turns off I-Cache - */ -__STATIC_INLINE void SCB_DisableICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0UL; // invalidate I-Cache - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate I-Cache - - The function invalidates I-Cache - */ -__STATIC_INLINE void SCB_InvalidateICache (void) -{ - #if (__ICACHE_PRESENT == 1) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** \brief Enable D-Cache - - The function turns on D-Cache - */ -__STATIC_INLINE void SCB_EnableDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Disable D-Cache - - The function turns off D-Cache - */ -__STATIC_INLINE void SCB_DisableDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache - - do { // clean & invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Invalidate D-Cache - - The function invalidates D-Cache - */ -__STATIC_INLINE void SCB_InvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean D-Cache - - The function cleans D-Cache - */ -__STATIC_INLINE void SCB_CleanDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // clean D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCSW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** \brief Clean & Invalidate D-Cache - - The function cleans and Invalidates D-Cache - */ -__STATIC_INLINE void SCB_CleanInvalidateDCache (void) -{ - #if (__DCACHE_PRESENT == 1) - uint32_t ccsidr, sshift, wshift, sw; - uint32_t sets, ways; - - SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache - ccsidr = SCB->CCSIDR; - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); - - __DSB(); - - do { // clean & invalidate D-Cache - uint32_t tmpways = ways; - do { - sw = ((tmpways << wshift) | (sets << sshift)); - SCB->DCCISW = sw; - } while(tmpways--); - } while(sets--); - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Invalidate by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t)addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCIMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Clean by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCCMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/** - \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) - \brief D-Cache Clean and Invalidate by address - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if (__DCACHE_PRESENT == 1) - int32_t op_size = dsize; - uint32_t op_addr = (uint32_t) addr; - uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) - - __DSB(); - - while (op_size > 0) { - SCB->DCCIMVAC = op_addr; - op_addr += linesize; - op_size -= (int32_t)linesize; - } - - __DSB(); - __ISB(); - #endif -} - - -/*@} end of CMSIS_Core_CacheFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h deleted file mode 100644 index 881904a1a..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h +++ /dev/null @@ -1,664 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMFUNC_H -#define __CORE_CMFUNC_H - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - -/* intrinsic void __enable_irq(); */ -/* intrinsic void __disable_irq(); */ - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xff); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/** \brief Enable IRQ Interrupts - - This function enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** \brief Disable IRQ Interrupts - - This function disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** \brief Get Control Register - - This function returns the content of the Control Register. - - \return Control Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -/** \brief Set Control Register - - This function writes the given value to the Control Register. - - \param [in] control Control Register value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -/** \brief Get IPSR Register - - This function returns the content of the IPSR Register. - - \return IPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get APSR Register - - This function returns the content of the APSR Register. - - \return APSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get xPSR Register - - This function returns the content of the xPSR Register. - - \return xPSR Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** \brief Get Process Stack Pointer - - This function returns the current value of the Process Stack Pointer (PSP). - - \return PSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Process Stack Pointer - - This function assigns the given value to the Process Stack Pointer (PSP). - - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); -} - - -/** \brief Get Main Stack Pointer - - This function returns the current value of the Main Stack Pointer (MSP). - - \return MSP Register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); - return(result); -} - - -/** \brief Set Main Stack Pointer - - This function assigns the given value to the Main Stack Pointer (MSP). - - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); -} - - -/** \brief Get Priority Mask - - This function returns the current state of the priority mask bit from the Priority Mask Register. - - \return Priority Mask value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Priority Mask - - This function assigns the given value to the Priority Mask Register. - - \param [in] priMask Priority Mask - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (__CORTEX_M >= 0x03) - -/** \brief Enable FIQ - - This function enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** \brief Disable FIQ - - This function disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** \brief Get Base Priority - - This function returns the current value of the Base Priority register. - - \return Base Priority register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -/** \brief Set Base Priority - - This function assigns the given value to the Base Priority register. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); -} - - -/** \brief Set Base Priority with condition - - This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - - \param [in] basePri Base Priority value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); -} - - -/** \brief Get Fault Mask - - This function returns the current value of the Fault Mask register. - - \return Fault Mask register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -/** \brief Set Fault Mask - - This function assigns the given value to the Fault Mask register. - - \param [in] faultMask Fault Mask value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) - -/** \brief Get FPSCR - - This function returns the current value of the Floating Point Status/Control register. - - \return Floating Point Status/Control register value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - uint32_t result; - - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - __ASM volatile (""); - return(result); -#else - return(0); -#endif -} - - -/** \brief Set FPSCR - - This function assigns the given value to the Floating Point Status/Control register. - - \param [in] fpscr Floating Point Status/Control value to set - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - /* Empty asm statement works as a scheduling barrier */ - __ASM volatile (""); - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); - __ASM volatile (""); -#endif -} - -#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of CMSIS_Core_RegAccFunctions */ - -#endif /* __CORE_CMFUNC_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h deleted file mode 100644 index fca425c51..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h +++ /dev/null @@ -1,916 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#ifndef __CORE_CMINSTR_H -#define __CORE_CMINSTR_H - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ - -#if (__ARMCC_VERSION < 400677) - #error "Please use ARM Compiler Toolchain V4.0.677 or later!" -#endif - - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0) - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero - return(result); -} -#endif - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH(value, ptr) __strex(value, ptr) - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -#define __CLREX __clrex - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constrant "l" - * Otherwise, use general registers, specified by constrant "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** \brief No Operation - - No Operation does nothing. This instruction can be used for code alignment purposes. - */ -__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) -{ - __ASM volatile ("nop"); -} - - -/** \brief Wait For Interrupt - - Wait For Interrupt is a hint instruction that suspends execution - until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) -{ - __ASM volatile ("wfi"); -} - - -/** \brief Wait For Event - - Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) -{ - __ASM volatile ("wfe"); -} - - -/** \brief Send Event - - Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) -{ - __ASM volatile ("sev"); -} - - -/** \brief Instruction Synchronization Barrier - - Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or - memory, after the instruction has been completed. - */ -__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** \brief Data Synchronization Barrier - - This function acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** \brief Data Memory Barrier - - This function ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** \brief Reverse byte order (32 bit) - - This function reverses the byte order in integer value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Reverse byte order (16 bit) - - This function reverses the byte order in two unsigned short values. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief Reverse byte order in signed short value - - This function reverses the byte order in a signed short value with sign extension to integer. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (short)__builtin_bswap16(value); -#else - uint32_t result; - - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -#endif -} - - -/** \brief Rotate Right in unsigned value (32 bit) - - This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - - \param [in] value Value to rotate - \param [in] value Number of Bits to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - return (op1 >> op2) | (op1 << (32 - op2)); -} - - -/** \brief Breakpoint - - This function causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** \brief Reverse bit order of value - - This function reverses the bit order of the given value. - - \param [in] value Value to reverse - \return Reversed value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end - - result = value; // r will be reversed bits of v; first get LSB of v - for (value >>= 1; value; value >>= 1) - { - result <<= 1; - result |= value & 1; - s--; - } - result <<= s; // shift when v's highest bits are zero -#endif - return(result); -} - - -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __builtin_clz - - -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - -/** \brief LDR Exclusive (8 bit) - - This function executes a exclusive LDR instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (16 bit) - - This function executes a exclusive LDR instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDR Exclusive (32 bit) - - This function executes a exclusive LDR instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STR Exclusive (8 bit) - - This function executes a exclusive STR instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (16 bit) - - This function executes a exclusive STR instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** \brief STR Exclusive (32 bit) - - This function executes a exclusive STR instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** \brief Remove the exclusive lock - - This function removes the exclusive lock which is created by LDREX. - - */ -__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - - -/** \brief Signed Saturate - - This function saturates a signed value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Unsigned Saturate - - This function saturates an unsigned value. - - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - - -/** \brief Rotate Right with Extend (32 bit) - - This function moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - - \param [in] value Value to rotate - \return Rotated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** \brief LDRT Unprivileged (8 bit) - - This function executes a Unprivileged LDRT instruction for 8 bit value. - - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (16 bit) - - This function executes a Unprivileged LDRT instruction for 16 bit values. - - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** \brief LDRT Unprivileged (32 bit) - - This function executes a Unprivileged LDRT instruction for 32 bit values. - - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** \brief STRT Unprivileged (8 bit) - - This function executes a Unprivileged STRT instruction for 8 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (16 bit) - - This function executes a Unprivileged STRT instruction for 16 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); -} - - -/** \brief STRT Unprivileged (32 bit) - - This function executes a Unprivileged STRT instruction for 32 bit values. - - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); -} - -#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */ - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - -#endif /* __CORE_CMINSTR_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h deleted file mode 100755 index 7b8e37fff..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h +++ /dev/null @@ -1,697 +0,0 @@ -/**************************************************************************//** - * @file core_cmSimd.h - * @brief CMSIS Cortex-M SIMD Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CMSIMD_H -#define __CORE_CMSIMD_H - -#ifdef __cplusplus - extern "C" { -#endif - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ -/* ARM armcc specific functions */ -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32) ) >> 32)) - - -#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ // Little endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else // Big endian - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - - -#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ -/* IAR iccarm specific functions */ -#include - - -#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ -/* TI CCS specific functions */ -#include - - -#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ -/* TASKING carm specific functions */ -/* not yet supported */ - - -#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ -/* Cosmic specific functions */ -#include - -#endif - -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CMSIMD_H */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h deleted file mode 100644 index 44cb02747..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,864 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC000 - @{ - */ - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (000) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000 - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31]; - __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31]; - __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31]; - __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31]; - uint32_t RESERVED4[64]; - __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1]; - __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2]; - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) - are only accessible over DAP and not via processor. Therefore - they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of SC000 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/* Interrupt Priorities are WORD accessible only under ARMv6M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)(IRQn) < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)(IRQn) < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } - else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h deleted file mode 100644 index 7e40672a9..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1675 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.10 - * @date 18. March 2015 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2015 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup SC3000 - @{ - */ - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_SC (300) /*!< Cortex secure core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0 - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI__VFP_SUPPORT____ - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000 - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31 /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30 /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29 /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28 /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27 /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31 /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29 /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28 /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24 /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - uint32_t RESERVED1[1]; -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if((int32_t)IRQn < 0) { - SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else { - NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if((int32_t)IRQn < 0) { - return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); - } - else { - return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); - } -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1) { __NOP(); } /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0UL) { __NOP(); } - ITM->PORT[0].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h deleted file mode 100644 index 3d05713bf..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h +++ /dev/null @@ -1,178 +0,0 @@ -/** - ****************************************************************************** - * @file misc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the miscellaneous - * firmware library functions (add-on to CMSIS functions). - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MISC_H -#define __MISC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup MISC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief NVIC Init Structure definition - */ - -typedef struct -{ - uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. - This parameter can be an enumerator of @ref IRQn_Type - enumeration (For the complete STM32 Devices IRQ Channels - list, please refer to stm32f4xx.h file) */ - - uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel - specified in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified - in NVIC_IRQChannel. This parameter can be a value - between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table - A lower priority value indicates a higher priority */ - - FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel - will be enabled or disabled. - This parameter can be set either to ENABLE or DISABLE */ -} NVIC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup MISC_Exported_Constants - * @{ - */ - -/** @defgroup MISC_Vector_Table_Base - * @{ - */ - -#define NVIC_VectTab_RAM ((uint32_t)0x20000000) -#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) -#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ - ((VECTTAB) == NVIC_VectTab_FLASH)) -/** - * @} - */ - -/** @defgroup MISC_System_Low_Power - * @{ - */ - -#define NVIC_LP_SEVONPEND ((uint8_t)0x10) -#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) -#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) -#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ - ((LP) == NVIC_LP_SLEEPDEEP) || \ - ((LP) == NVIC_LP_SLEEPONEXIT)) -/** - * @} - */ - -/** @defgroup MISC_Preemption_Priority_Group - * @{ - */ - -#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ - -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ - ((GROUP) == NVIC_PriorityGroup_1) || \ - ((GROUP) == NVIC_PriorityGroup_2) || \ - ((GROUP) == NVIC_PriorityGroup_3) || \ - ((GROUP) == NVIC_PriorityGroup_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) - -#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) - -/** - * @} - */ - -/** @defgroup MISC_SysTick_clock_source - * @{ - */ - -#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) -#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ - ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); - -#ifdef __cplusplus -} -#endif - -#endif /* __MISC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h deleted file mode 100644 index 6efce5184..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h +++ /dev/null @@ -1,656 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the ADC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_ADC_H -#define __STM32F4xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief ADC Init structure definition - */ -typedef struct -{ - uint32_t ADC_Resolution; /*!< Configures the ADC resolution dual mode. - This parameter can be a value of @ref ADC_resolution */ - FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion - is performed in Scan (multichannels) - or Single (one channel) mode. - This parameter can be set to ENABLE or DISABLE */ - FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion - is performed in Continuous or Single mode. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t ADC_ExternalTrigConvEdge; /*!< Select the external trigger edge and - enable the trigger of a regular group. - This parameter can be a value of - @ref ADC_external_trigger_edge_for_regular_channels_conversion */ - uint32_t ADC_ExternalTrigConv; /*!< Select the external event used to trigger - the start of conversion of a regular group. - This parameter can be a value of - @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */ - uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment - is left or right. This parameter can be - a value of @ref ADC_data_align */ - uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions - that will be done using the sequencer for - regular channel group. - This parameter must range from 1 to 16. */ -}ADC_InitTypeDef; - -/** - * @brief ADC Common Init structure definition - */ -typedef struct -{ - uint32_t ADC_Mode; /*!< Configures the ADC to operate in - independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ - uint32_t ADC_Prescaler; /*!< Select the frequency of the clock - to the ADC. The clock is common for all the ADCs. - This parameter can be a value of @ref ADC_Prescaler */ - uint32_t ADC_DMAAccessMode; /*!< Configures the Direct memory access - mode for multi ADC mode. - This parameter can be a value of - @ref ADC_Direct_memory_access_mode_for_multi_mode */ - uint32_t ADC_TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of - @ref ADC_delay_between_2_sampling_phases */ - -}ADC_CommonInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants - * @{ - */ -#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ - ((PERIPH) == ADC2) || \ - ((PERIPH) == ADC3)) - -/** @defgroup ADC_Common_mode - * @{ - */ -#define ADC_Mode_Independent ((uint32_t)0x00000000) -#define ADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001) -#define ADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002) -#define ADC_DualMode_InjecSimult ((uint32_t)0x00000005) -#define ADC_DualMode_RegSimult ((uint32_t)0x00000006) -#define ADC_DualMode_Interl ((uint32_t)0x00000007) -#define ADC_DualMode_AlterTrig ((uint32_t)0x00000009) -#define ADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011) -#define ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012) -#define ADC_TripleMode_InjecSimult ((uint32_t)0x00000015) -#define ADC_TripleMode_RegSimult ((uint32_t)0x00000016) -#define ADC_TripleMode_Interl ((uint32_t)0x00000017) -#define ADC_TripleMode_AlterTrig ((uint32_t)0x00000019) -#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \ - ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_DualMode_InjecSimult) || \ - ((MODE) == ADC_DualMode_RegSimult) || \ - ((MODE) == ADC_DualMode_Interl) || \ - ((MODE) == ADC_DualMode_AlterTrig) || \ - ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \ - ((MODE) == ADC_TripleMode_InjecSimult) || \ - ((MODE) == ADC_TripleMode_RegSimult) || \ - ((MODE) == ADC_TripleMode_Interl) || \ - ((MODE) == ADC_TripleMode_AlterTrig)) -/** - * @} - */ - - -/** @defgroup ADC_Prescaler - * @{ - */ -#define ADC_Prescaler_Div2 ((uint32_t)0x00000000) -#define ADC_Prescaler_Div4 ((uint32_t)0x00010000) -#define ADC_Prescaler_Div6 ((uint32_t)0x00020000) -#define ADC_Prescaler_Div8 ((uint32_t)0x00030000) -#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \ - ((PRESCALER) == ADC_Prescaler_Div4) || \ - ((PRESCALER) == ADC_Prescaler_Div6) || \ - ((PRESCALER) == ADC_Prescaler_Div8)) -/** - * @} - */ - - -/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode - * @{ - */ -#define ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000) /* DMA mode disabled */ -#define ADC_DMAAccessMode_1 ((uint32_t)0x00004000) /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAAccessMode_2 ((uint32_t)0x00008000) /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAAccessMode_3 ((uint32_t)0x0000C000) /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \ - ((MODE) == ADC_DMAAccessMode_1) || \ - ((MODE) == ADC_DMAAccessMode_2) || \ - ((MODE) == ADC_DMAAccessMode_3)) - -/** - * @} - */ - - -/** @defgroup ADC_delay_between_2_sampling_phases - * @{ - */ -#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) -#define ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100) -#define ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200) -#define ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300) -#define ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400) -#define ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500) -#define ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600) -#define ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700) -#define ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800) -#define ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900) -#define ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00) -#define ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00) -#define ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00) -#define ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00) -#define ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00) -#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) -#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \ - ((DELAY) == ADC_TwoSamplingDelay_20Cycles)) - -/** - * @} - */ - - -/** @defgroup ADC_resolution - * @{ - */ -#define ADC_Resolution_12b ((uint32_t)0x00000000) -#define ADC_Resolution_10b ((uint32_t)0x01000000) -#define ADC_Resolution_8b ((uint32_t)0x02000000) -#define ADC_Resolution_6b ((uint32_t)0x03000000) -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \ - ((RESOLUTION) == ADC_Resolution_10b) || \ - ((RESOLUTION) == ADC_Resolution_8b) || \ - ((RESOLUTION) == ADC_Resolution_6b)) - -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000) -#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000) -#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000) -#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling)) -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion - * @{ - */ -#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) -#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x01000000) -#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x02000000) -#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000) -#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x04000000) -#define ADC_ExternalTrigConv_T2_CC4 ((uint32_t)0x05000000) -#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000) -#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000) -#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x08000000) -#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x09000000) -#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x0A000000) -#define ADC_ExternalTrigConv_T5_CC2 ((uint32_t)0x0B000000) -#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x0C000000) -#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x0D000000) -#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x0E000000) -#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000) -#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \ - ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \ - ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11)) -/** - * @} - */ - - -/** @defgroup ADC_data_align - * @{ - */ -#define ADC_DataAlign_Right ((uint32_t)0x00000000) -#define ADC_DataAlign_Left ((uint32_t)0x00000800) -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \ - ((ALIGN) == ADC_DataAlign_Left)) -/** - * @} - */ - - -/** @defgroup ADC_channels - * @{ - */ -#define ADC_Channel_0 ((uint8_t)0x00) -#define ADC_Channel_1 ((uint8_t)0x01) -#define ADC_Channel_2 ((uint8_t)0x02) -#define ADC_Channel_3 ((uint8_t)0x03) -#define ADC_Channel_4 ((uint8_t)0x04) -#define ADC_Channel_5 ((uint8_t)0x05) -#define ADC_Channel_6 ((uint8_t)0x06) -#define ADC_Channel_7 ((uint8_t)0x07) -#define ADC_Channel_8 ((uint8_t)0x08) -#define ADC_Channel_9 ((uint8_t)0x09) -#define ADC_Channel_10 ((uint8_t)0x0A) -#define ADC_Channel_11 ((uint8_t)0x0B) -#define ADC_Channel_12 ((uint8_t)0x0C) -#define ADC_Channel_13 ((uint8_t)0x0D) -#define ADC_Channel_14 ((uint8_t)0x0E) -#define ADC_Channel_15 ((uint8_t)0x0F) -#define ADC_Channel_16 ((uint8_t)0x10) -#define ADC_Channel_17 ((uint8_t)0x11) -#define ADC_Channel_18 ((uint8_t)0x12) - -#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) -#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */ - -#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) -#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \ - ((CHANNEL) == ADC_Channel_1) || \ - ((CHANNEL) == ADC_Channel_2) || \ - ((CHANNEL) == ADC_Channel_3) || \ - ((CHANNEL) == ADC_Channel_4) || \ - ((CHANNEL) == ADC_Channel_5) || \ - ((CHANNEL) == ADC_Channel_6) || \ - ((CHANNEL) == ADC_Channel_7) || \ - ((CHANNEL) == ADC_Channel_8) || \ - ((CHANNEL) == ADC_Channel_9) || \ - ((CHANNEL) == ADC_Channel_10) || \ - ((CHANNEL) == ADC_Channel_11) || \ - ((CHANNEL) == ADC_Channel_12) || \ - ((CHANNEL) == ADC_Channel_13) || \ - ((CHANNEL) == ADC_Channel_14) || \ - ((CHANNEL) == ADC_Channel_15) || \ - ((CHANNEL) == ADC_Channel_16) || \ - ((CHANNEL) == ADC_Channel_17) || \ - ((CHANNEL) == ADC_Channel_18)) -/** - * @} - */ - - -/** @defgroup ADC_sampling_times - * @{ - */ -#define ADC_SampleTime_3Cycles ((uint8_t)0x00) -#define ADC_SampleTime_15Cycles ((uint8_t)0x01) -#define ADC_SampleTime_28Cycles ((uint8_t)0x02) -#define ADC_SampleTime_56Cycles ((uint8_t)0x03) -#define ADC_SampleTime_84Cycles ((uint8_t)0x04) -#define ADC_SampleTime_112Cycles ((uint8_t)0x05) -#define ADC_SampleTime_144Cycles ((uint8_t)0x06) -#define ADC_SampleTime_480Cycles ((uint8_t)0x07) -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \ - ((TIME) == ADC_SampleTime_15Cycles) || \ - ((TIME) == ADC_SampleTime_28Cycles) || \ - ((TIME) == ADC_SampleTime_56Cycles) || \ - ((TIME) == ADC_SampleTime_84Cycles) || \ - ((TIME) == ADC_SampleTime_112Cycles) || \ - ((TIME) == ADC_SampleTime_144Cycles) || \ - ((TIME) == ADC_SampleTime_480Cycles)) -/** - * @} - */ - - -/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000) -#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000) -#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \ - ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling)) - -/** - * @} - */ - - -/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion - * @{ - */ -#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00000000) -#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00010000) -#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00020000) -#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00030000) -#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00040000) -#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00050000) -#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000) -#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000) -#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000) -#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00090000) -#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x000A0000) -#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x000B0000) -#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x000C0000) -#define ADC_ExternalTrigInjecConv_T8_CC3 ((uint32_t)0x000D0000) -#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x000E0000) -#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000) -#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \ - ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15)) -/** - * @} - */ - - -/** @defgroup ADC_injected_channel_selection - * @{ - */ -#define ADC_InjectedChannel_1 ((uint8_t)0x14) -#define ADC_InjectedChannel_2 ((uint8_t)0x18) -#define ADC_InjectedChannel_3 ((uint8_t)0x1C) -#define ADC_InjectedChannel_4 ((uint8_t)0x20) -#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \ - ((CHANNEL) == ADC_InjectedChannel_2) || \ - ((CHANNEL) == ADC_InjectedChannel_3) || \ - ((CHANNEL) == ADC_InjectedChannel_4)) -/** - * @} - */ - - -/** @defgroup ADC_analog_watchdog_selection - * @{ - */ -#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) -#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) -#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) -#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) -#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) -#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) -#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) -#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \ - ((WATCHDOG) == ADC_AnalogWatchdog_None)) -/** - * @} - */ - - -/** @defgroup ADC_interrupts_definition - * @{ - */ -#define ADC_IT_EOC ((uint16_t)0x0205) -#define ADC_IT_AWD ((uint16_t)0x0106) -#define ADC_IT_JEOC ((uint16_t)0x0407) -#define ADC_IT_OVR ((uint16_t)0x201A) -#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \ - ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_flags_definition - * @{ - */ -#define ADC_FLAG_AWD ((uint8_t)0x01) -#define ADC_FLAG_EOC ((uint8_t)0x02) -#define ADC_FLAG_JEOC ((uint8_t)0x04) -#define ADC_FLAG_JSTRT ((uint8_t)0x08) -#define ADC_FLAG_STRT ((uint8_t)0x10) -#define ADC_FLAG_OVR ((uint8_t)0x20) - -#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00)) -#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \ - ((FLAG) == ADC_FLAG_EOC) || \ - ((FLAG) == ADC_FLAG_JEOC) || \ - ((FLAG)== ADC_FLAG_JSTRT) || \ - ((FLAG) == ADC_FLAG_STRT) || \ - ((FLAG)== ADC_FLAG_OVR)) -/** - * @} - */ - - -/** @defgroup ADC_thresholds - * @{ - */ -#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_offset - * @{ - */ -#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF) -/** - * @} - */ - - -/** @defgroup ADC_injected_length - * @{ - */ -#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_injected_rank - * @{ - */ -#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4)) -/** - * @} - */ - - -/** @defgroup ADC_regular_length - * @{ - */ -#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_rank - * @{ - */ -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10)) -/** - * @} - */ - - -/** @defgroup ADC_regular_discontinuous_mode_number - * @{ - */ -#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the ADC configuration to the default reset state *****/ -void ADC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct); -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); - -/* Analog Watchdog configuration functions ************************************/ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold); -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); - -/* Temperature Sensor, Vrefint and VBAT management functions ******************/ -void ADC_TempSensorVrefintCmd(FunctionalState NewState); -void ADC_VBATCmd(FunctionalState NewState); - -/* Regular Channels Configuration functions ***********************************/ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); -uint32_t ADC_GetMultiModeConversionValue(void); - -/* Regular Channels DMA Configuration functions *******************************/ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState); - -/* Injected channels Configuration functions **********************************/ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge); -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx); -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); - -/* Interrupts and flags management functions **********************************/ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_ADC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h deleted file mode 100644 index 67b3b611e..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h +++ /dev/null @@ -1,657 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the CAN firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CAN_H -#define __STM32F4xx_CAN_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -#if defined(STM32F413_423xx) -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2) || \ - ((PERIPH) == CAN3)) -#else -#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \ - ((PERIPH) == CAN2)) -#endif /* STM32F413_423xx */ - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum. - It ranges from 1 to 1024. */ - - uint8_t CAN_Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta - the CAN hardware is allowed to lengthen or - shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit - Segment 1. This parameter can be a value of - @ref CAN_time_quantum_in_bit_segment_1 */ - - uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set either to ENABLE or DISABLE. */ - - FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_InitTypeDef; - -/** - * @brief CAN filter init structure definition - */ -typedef struct -{ - uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter can be a value between 0x0000 and 0xFFFF */ - - uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */ - - uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint8_t CAN_FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter. - This parameter can be set either to ENABLE or DISABLE. */ -} CAN_FilterInitTypeDef; - -/** - * @brief CAN Tx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be transmitted. This parameter can be a value - of @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the message that will - be transmitted. This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be - transmitted. This parameter can be a value between - 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 - to 0xFF. */ -} CanTxMsg; - -/** - * @brief CAN Rx message structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter can be a value between 0 to 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter can be a value between 0 to 0x1FFFFFFF. */ - - uint8_t IDE; /*!< Specifies the type of identifier for the message that - will be received. This parameter can be a value of - @ref CAN_identifier_type */ - - uint8_t RTR; /*!< Specifies the type of frame for the received message. - This parameter can be a value of - @ref CAN_remote_transmission_request */ - - uint8_t DLC; /*!< Specifies the length of the frame that will be received. - This parameter can be a value between 0 to 8 */ - - uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to - 0xFF. */ - - uint8_t FMI; /*!< Specifies the index of the filter the message stored in - the mailbox passes through. This parameter can be a - value between 0 to 0xFF */ -} CanRxMsg; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants - * @{ - */ - -/** @defgroup CAN_InitStatus - * @{ - */ - -#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */ -#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */ - - -/* Legacy defines */ -#define CANINITFAILED CAN_InitStatus_Failed -#define CANINITOK CAN_InitStatus_Success -/** - * @} - */ - -/** @defgroup CAN_operating_mode - * @{ - */ - -#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */ -#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */ -#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */ -#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \ - ((MODE) == CAN_Mode_LoopBack)|| \ - ((MODE) == CAN_Mode_Silent) || \ - ((MODE) == CAN_Mode_Silent_LoopBack)) -/** - * @} - */ - - - /** - * @defgroup CAN_operating_mode - * @{ - */ -#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */ -#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */ -#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */ - - -#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\ - ((MODE) == CAN_OperatingMode_Normal)|| \ - ((MODE) == CAN_OperatingMode_Sleep)) -/** - * @} - */ - -/** - * @defgroup CAN_operating_mode_status - * @{ - */ - -#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */ -#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */ -/** - * @} - */ - -/** @defgroup CAN_synchronisation_jump_width - * @{ - */ -#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */ - -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \ - ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq)) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 - * @{ - */ -#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */ -#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */ -#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */ -#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */ -#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */ -#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */ -#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */ -#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */ -#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */ - -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq) -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 - * @{ - */ -#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */ -#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */ -#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */ -#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */ -#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */ -#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */ -#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */ -#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */ - -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq) -/** - * @} - */ - -/** @defgroup CAN_clock_prescaler - * @{ - */ -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024)) -/** - * @} - */ - -/** @defgroup CAN_filter_number - * @{ - */ -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27) -/** - * @} - */ - -/** @defgroup CAN_filter_mode - * @{ - */ -#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */ -#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */ - -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \ - ((MODE) == CAN_FilterMode_IdList)) -/** - * @} - */ - -/** @defgroup CAN_filter_scale - * @{ - */ -#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */ -#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */ - -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \ - ((SCALE) == CAN_FilterScale_32bit)) -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO - * @{ - */ -#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \ - ((FIFO) == CAN_FilterFIFO1)) - -/* Legacy defines */ -#define CAN_FilterFIFO0 CAN_Filter_FIFO0 -#define CAN_FilterFIFO1 CAN_Filter_FIFO1 -/** - * @} - */ - -/** @defgroup CAN_Start_bank_filter_for_slave_CAN - * @{ - */ -#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27)) -/** - * @} - */ - -/** @defgroup CAN_Tx - * @{ - */ -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF)) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF)) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) -/** - * @} - */ - -/** @defgroup CAN_identifier_type - * @{ - */ -#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */ -#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */ -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \ - ((IDTYPE) == CAN_Id_Extended)) - -/* Legacy defines */ -#define CAN_ID_STD CAN_Id_Standard -#define CAN_ID_EXT CAN_Id_Extended -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request - * @{ - */ -#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */ -#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */ -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote)) - -/* Legacy defines */ -#define CAN_RTR_DATA CAN_RTR_Data -#define CAN_RTR_REMOTE CAN_RTR_Remote -/** - * @} - */ - -/** @defgroup CAN_transmit_constants - * @{ - */ -#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */ -#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */ -#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */ -#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide - an empty mailbox */ -/* Legacy defines */ -#define CANTXFAILED CAN_TxStatus_Failed -#define CANTXOK CAN_TxStatus_Ok -#define CANTXPENDING CAN_TxStatus_Pending -#define CAN_NO_MB CAN_TxStatus_NoMailBox -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number_constants - * @{ - */ -#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ -#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ - -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -/** - * @} - */ - -/** @defgroup CAN_sleep_constants - * @{ - */ -#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */ -#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */ - -/* Legacy defines */ -#define CANSLEEPFAILED CAN_Sleep_Failed -#define CANSLEEPOK CAN_Sleep_Ok -/** - * @} - */ - -/** @defgroup CAN_wake_up_constants - * @{ - */ -#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */ -#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */ - -/* Legacy defines */ -#define CANWAKEUPFAILED CAN_WakeUp_Failed -#define CANWAKEUPOK CAN_WakeUp_Ok -/** - * @} - */ - -/** - * @defgroup CAN_Error_Code_constants - * @{ - */ -#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */ -#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */ -#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */ -#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */ -#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ -#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */ -#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */ -#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */ -/** - * @} - */ - -/** @defgroup CAN_flags - * @{ - */ -/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() - and CAN_ClearFlag() functions. */ -/* If the flag is 0x1XXXXXXX, it means that it can only be used with - CAN_GetFlagStatus() function. */ - -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */ -#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */ -#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */ - -/* Receive Flags */ -#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */ -#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */ -#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */ -#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */ -#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */ -#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */ -#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */ -/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. - In this case the SLAK bit can be polled.*/ - -/* Error Flags */ -#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */ -#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */ -#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */ -#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */ - -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_SLAK )) - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK)) -/** - * @} - */ - - -/** @defgroup CAN_interrupts - * @{ - */ -#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/ - -/* Receive Interrupts */ -#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/ -#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/ -#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/ -#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/ -#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/ -#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/ - -/* Operating Mode Interrupts */ -#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/ -#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/ - -/* Error Interrupts */ -#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/ -#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/ -#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/ -#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/ -#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/ - -/* Flags named as Interrupts : kept only for FW compatibility */ -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME - - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CAN configuration to the default reset state *****/ -void CAN_DeInit(CAN_TypeDef* CANx); - -/* Initialization and Configuration functions *********************************/ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); -#if defined(STM32F413_423xx) -void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct); -#else -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); -#endif /* STM32F413_423xx */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); -#if defined(STM32F413_423xx) -void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber); -#else -void CAN_SlaveStartBank(uint8_t CAN_BankNumber); -#endif /* STM32F413_423xx */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); - -/* CAN Frames Transmission functions ******************************************/ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); - -/* CAN Frames Reception functions *********************************************/ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); - -/* Operation modes functions **************************************************/ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); -uint8_t CAN_Sleep(CAN_TypeDef* CANx); -uint8_t CAN_WakeUp(CAN_TypeDef* CANx); - -/* CAN Bus Error management functions *****************************************/ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); - -/* Interrupts and flags management functions **********************************/ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CAN_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h deleted file mode 100644 index 58bc88569..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the CRC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRC_H -#define __STM32F4xx_CRC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void CRC_ResetDR(void); -uint32_t CRC_CalcCRC(uint32_t Data); -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); -uint32_t CRC_GetCRC(void); -void CRC_SetIDRegister(uint8_t IDValue); -uint8_t CRC_GetIDRegister(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_CRC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h deleted file mode 100644 index 33212ae67..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h +++ /dev/null @@ -1,384 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the Cryptographic - * processor(CRYP) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_CRYP_H -#define __STM32F4xx_CRYP_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief CRYP Init structure definition - */ -typedef struct -{ - uint32_t CRYP_AlgoDir; /*!< Encrypt or Decrypt. This parameter can be a - value of @ref CRYP_Algorithm_Direction */ - uint32_t CRYP_AlgoMode; /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, - AES-CBC, AES-CTR, AES-Key, AES-GCM and AES-CCM. - This parameter can be a value of @ref CRYP_Algorithm_Mode */ - uint32_t CRYP_DataType; /*!< 32-bit data, 16-bit data, bit data or bit string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint32_t CRYP_KeySize; /*!< Used only in AES mode only : 128, 192 or 256 bit - key length. This parameter can be a value of - @ref CRYP_Key_Size_for_AES_only */ -}CRYP_InitTypeDef; - -/** - * @brief CRYP Key(s) structure definition - */ -typedef struct -{ - uint32_t CRYP_Key0Left; /*!< Key 0 Left */ - uint32_t CRYP_Key0Right; /*!< Key 0 Right */ - uint32_t CRYP_Key1Left; /*!< Key 1 left */ - uint32_t CRYP_Key1Right; /*!< Key 1 Right */ - uint32_t CRYP_Key2Left; /*!< Key 2 left */ - uint32_t CRYP_Key2Right; /*!< Key 2 Right */ - uint32_t CRYP_Key3Left; /*!< Key 3 left */ - uint32_t CRYP_Key3Right; /*!< Key 3 Right */ -}CRYP_KeyInitTypeDef; -/** - * @brief CRYP Initialization Vectors (IV) structure definition - */ -typedef struct -{ - uint32_t CRYP_IV0Left; /*!< Init Vector 0 Left */ - uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */ - uint32_t CRYP_IV1Left; /*!< Init Vector 1 left */ - uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */ -}CRYP_IVInitTypeDef; - -/** - * @brief CRYP context swapping structure definition - */ -typedef struct -{ - /*!< Current Configuration */ - uint32_t CR_CurrentConfig; - /*!< IV */ - uint32_t CRYP_IV0LR; - uint32_t CRYP_IV0RR; - uint32_t CRYP_IV1LR; - uint32_t CRYP_IV1RR; - /*!< KEY */ - uint32_t CRYP_K0LR; - uint32_t CRYP_K0RR; - uint32_t CRYP_K1LR; - uint32_t CRYP_K1RR; - uint32_t CRYP_K2LR; - uint32_t CRYP_K2RR; - uint32_t CRYP_K3LR; - uint32_t CRYP_K3RR; - uint32_t CRYP_CSGCMCCMR[8]; - uint32_t CRYP_CSGCMR[8]; -}CRYP_Context; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Constants - * @{ - */ - -/** @defgroup CRYP_Algorithm_Direction - * @{ - */ -#define CRYP_AlgoDir_Encrypt ((uint16_t)0x0000) -#define CRYP_AlgoDir_Decrypt ((uint16_t)0x0004) -#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \ - ((ALGODIR) == CRYP_AlgoDir_Decrypt)) - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode - * @{ - */ - -/*!< TDES Modes */ -#define CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000) -#define CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008) - -/*!< DES Modes */ -#define CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010) -#define CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018) - -/*!< AES Modes */ -#define CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020) -#define CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028) -#define CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030) -#define CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038) -#define CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000) -#define CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008) - -#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \ - ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || \ - ((ALGOMODE) == CRYP_AlgoMode_AES_CCM)) -/** - * @} - */ - -/** @defgroup CRYP_Phase - * @{ - */ - -/*!< The phases are valid only for AES-GCM and AES-CCM modes */ -#define CRYP_Phase_Init ((uint32_t)0x00000000) -#define CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0 -#define CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1 -#define CRYP_Phase_Final CRYP_CR_GCM_CCMPH - -#define IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || \ - ((PHASE) == CRYP_Phase_Header) || \ - ((PHASE) == CRYP_Phase_Payload) || \ - ((PHASE) == CRYP_Phase_Final)) - -/** - * @} - */ - -/** @defgroup CRYP_Data_Type - * @{ - */ -#define CRYP_DataType_32b ((uint16_t)0x0000) -#define CRYP_DataType_16b ((uint16_t)0x0040) -#define CRYP_DataType_8b ((uint16_t)0x0080) -#define CRYP_DataType_1b ((uint16_t)0x00C0) -#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \ - ((DATATYPE) == CRYP_DataType_16b)|| \ - ((DATATYPE) == CRYP_DataType_8b)|| \ - ((DATATYPE) == CRYP_DataType_1b)) -/** - * @} - */ - -/** @defgroup CRYP_Key_Size_for_AES_only - * @{ - */ -#define CRYP_KeySize_128b ((uint16_t)0x0000) -#define CRYP_KeySize_192b ((uint16_t)0x0100) -#define CRYP_KeySize_256b ((uint16_t)0x0200) -#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \ - ((KEYSIZE) == CRYP_KeySize_192b)|| \ - ((KEYSIZE) == CRYP_KeySize_256b)) -/** - * @} - */ - -/** @defgroup CRYP_flags_definition - * @{ - */ -#define CRYP_FLAG_BUSY ((uint8_t)0x10) /*!< The CRYP core is currently - processing a block of data - or a key preparation (for - AES decryption). */ -#define CRYP_FLAG_IFEM ((uint8_t)0x01) /*!< Input Fifo Empty */ -#define CRYP_FLAG_IFNF ((uint8_t)0x02) /*!< Input Fifo is Not Full */ -#define CRYP_FLAG_INRIS ((uint8_t)0x22) /*!< Raw interrupt pending */ -#define CRYP_FLAG_OFNE ((uint8_t)0x04) /*!< Input Fifo service raw - interrupt status */ -#define CRYP_FLAG_OFFU ((uint8_t)0x08) /*!< Output Fifo is Full */ -#define CRYP_FLAG_OUTRIS ((uint8_t)0x21) /*!< Output Fifo service raw - interrupt status */ - -#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || \ - ((FLAG) == CRYP_FLAG_IFNF) || \ - ((FLAG) == CRYP_FLAG_OFNE) || \ - ((FLAG) == CRYP_FLAG_OFFU) || \ - ((FLAG) == CRYP_FLAG_BUSY) || \ - ((FLAG) == CRYP_FLAG_OUTRIS)|| \ - ((FLAG) == CRYP_FLAG_INRIS)) -/** - * @} - */ - -/** @defgroup CRYP_interrupts_definition - * @{ - */ -#define CRYP_IT_INI ((uint8_t)0x01) /*!< IN Fifo Interrupt */ -#define CRYP_IT_OUTI ((uint8_t)0x02) /*!< OUT Fifo Interrupt */ -#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00)) -#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI)) - -/** - * @} - */ - -/** @defgroup CRYP_Encryption_Decryption_modes_definition - * @{ - */ -#define MODE_ENCRYPT ((uint8_t)0x01) -#define MODE_DECRYPT ((uint8_t)0x00) - -/** - * @} - */ - -/** @defgroup CRYP_DMA_transfer_requests - * @{ - */ -#define CRYP_DMAReq_DataIN ((uint8_t)0x01) -#define CRYP_DMAReq_DataOUT ((uint8_t)0x02) -#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the CRYP configuration to the default reset state ****/ -void CRYP_DeInit(void); - -/* CRYP Initialization and Configuration functions ****************************/ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct); -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct); -void CRYP_Cmd(FunctionalState NewState); -void CRYP_PhaseConfig(uint32_t CRYP_Phase); -void CRYP_FIFOFlush(void); -/* CRYP Data processing functions *********************************************/ -void CRYP_DataIn(uint32_t Data); -uint32_t CRYP_DataOut(void); - -/* CRYP Context swapping functions ********************************************/ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct); -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore); - -/* CRYP DMA interface function ************************************************/ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState); -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT); -FunctionalState CRYP_GetCmdStatus(void); -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG); - -/* High Level AES functions **************************************************/ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CBC(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_CTR(uint8_t Mode, - uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16], - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t ILength, - uint8_t *Header, uint32_t HLength, - uint8_t *Output, uint8_t *AuthTAG); - -ErrorStatus CRYP_AES_CCM(uint8_t Mode, - uint8_t* Nonce, uint32_t NonceSize, - uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t ILength, - uint8_t* Header, uint32_t HLength, uint8_t *HBuffer, - uint8_t* Output, - uint8_t* AuthTAG, uint32_t TAGSize); - -/* High Level TDES functions **************************************************/ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, - uint8_t Key[24], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_TDES_CBC(uint8_t Mode, - uint8_t Key[24], - uint8_t InitVectors[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -/* High Level DES functions **************************************************/ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, - uint8_t Key[8], - uint8_t *Input, uint32_t Ilength, - uint8_t *Output); - -ErrorStatus CRYP_DES_CBC(uint8_t Mode, - uint8_t Key[8], - uint8_t InitVectors[8], - uint8_t *Input,uint32_t Ilength, - uint8_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_CRYP_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h deleted file mode 100644 index 0bea63362..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h +++ /dev/null @@ -1,304 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dac.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the DAC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DAC_H -#define __STM32F4xx_DAC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DAC Init structure definition - */ - -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves - are generated, or whether no wave is generated. - This parameter can be a value of @ref DAC_wave_generation */ - - uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or - the maximum amplitude triangle generation for the DAC channel. - This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ -}DAC_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants - * @{ - */ - -/** @defgroup DAC_trigger_selection - * @{ - */ - -#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ - -#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ - -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ - ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ - ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ - ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ - ((TRIGGER) == DAC_Trigger_Software)) - -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_WaveGeneration_None ((uint32_t)0x00000000) -#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) -#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ - ((WAVE) == DAC_WaveGeneration_Noise) || \ - ((WAVE) == DAC_WaveGeneration_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_lfsrunmask_triangleamplitude - * @{ - */ - -#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ -#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ -#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ -#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ -#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ -#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ -#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ -#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ -#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ -#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ - ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ - ((VALUE) == DAC_TriangleAmplitude_1) || \ - ((VALUE) == DAC_TriangleAmplitude_3) || \ - ((VALUE) == DAC_TriangleAmplitude_7) || \ - ((VALUE) == DAC_TriangleAmplitude_15) || \ - ((VALUE) == DAC_TriangleAmplitude_31) || \ - ((VALUE) == DAC_TriangleAmplitude_63) || \ - ((VALUE) == DAC_TriangleAmplitude_127) || \ - ((VALUE) == DAC_TriangleAmplitude_255) || \ - ((VALUE) == DAC_TriangleAmplitude_511) || \ - ((VALUE) == DAC_TriangleAmplitude_1023) || \ - ((VALUE) == DAC_TriangleAmplitude_2047) || \ - ((VALUE) == DAC_TriangleAmplitude_4095)) -/** - * @} - */ - -/** @defgroup DAC_output_buffer - * @{ - */ - -#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) -#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ - ((STATE) == DAC_OutputBuffer_Disable)) -/** - * @} - */ - -/** @defgroup DAC_Channel_selection - * @{ - */ - -#define DAC_Channel_1 ((uint32_t)0x00000000) -#define DAC_Channel_2 ((uint32_t)0x00000010) -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ - ((CHANNEL) == DAC_Channel_2)) -/** - * @} - */ - -/** @defgroup DAC_data_alignement - * @{ - */ - -#define DAC_Align_12b_R ((uint32_t)0x00000000) -#define DAC_Align_12b_L ((uint32_t)0x00000004) -#define DAC_Align_8b_R ((uint32_t)0x00000008) -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ - ((ALIGN) == DAC_Align_12b_L) || \ - ((ALIGN) == DAC_Align_8b_R)) -/** - * @} - */ - -/** @defgroup DAC_wave_generation - * @{ - */ - -#define DAC_Wave_Noise ((uint32_t)0x00000040) -#define DAC_Wave_Triangle ((uint32_t)0x00000080) -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ - ((WAVE) == DAC_Wave_Triangle)) -/** - * @} - */ - -/** @defgroup DAC_data - * @{ - */ - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) -/** - * @} - */ - -/** @defgroup DAC_interrupts_definition - * @{ - */ -#define DAC_IT_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) - -/** - * @} - */ - -/** @defgroup DAC_flags_definition - * @{ - */ - -#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) -#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DAC configuration to the default reset state *****/ -void DAC_DeInit(void); - -/* DAC channels configuration: trigger, output buffer, data format functions */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); - -/* DMA management functions ***************************************************/ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DAC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h deleted file mode 100644 index 9a7536ca4..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the DBGMCU firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DBGMCU_H -#define __STM32F4xx_DBGMCU_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DBGMCU - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Constants - * @{ - */ -#define DBGMCU_SLEEP ((uint32_t)0x00000001) -#define DBGMCU_STOP ((uint32_t)0x00000002) -#define DBGMCU_STANDBY ((uint32_t)0x00000004) -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004) -#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008) -#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010) -#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020) -#define DBGMCU_TIM12_STOP ((uint32_t)0x00000040) -#define DBGMCU_TIM13_STOP ((uint32_t)0x00000080) -#define DBGMCU_TIM14_STOP ((uint32_t)0x00000100) -#define DBGMCU_RTC_STOP ((uint32_t)0x00000400) -#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800) -#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000) -#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) -#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) -#define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) -#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000) -#define DBGMCU_CAN2_STOP ((uint32_t)0x04000000) -#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00)) - -#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001) -#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002) -#define DBGMCU_TIM9_STOP ((uint32_t)0x00010000) -#define DBGMCU_TIM10_STOP ((uint32_t)0x00020000) -#define DBGMCU_TIM11_STOP ((uint32_t)0x00040000) -#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -uint32_t DBGMCU_GetREVID(void); -uint32_t DBGMCU_GetDEVID(void); -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_DBGMCU_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h deleted file mode 100644 index d15020281..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the DCMI firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DCMI_H -#define __STM32F4xx_DCMI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DCMI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint16_t DCMI_CaptureMode; /*!< Specifies the Capture Mode: Continuous or Snapshot. - This parameter can be a value of @ref DCMI_Capture_Mode */ - - uint16_t DCMI_SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint16_t DCMI_PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint16_t DCMI_VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint16_t DCMI_HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint16_t DCMI_CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ -} DCMI_InitTypeDef; - -/** - * @brief DCMI CROP Init structure definition - */ -typedef struct -{ - uint16_t DCMI_VerticalStartLine; /*!< Specifies the Vertical start line count from which the image capture - will start. This parameter can be a value between 0x00 and 0x1FFF */ - - uint16_t DCMI_HorizontalOffsetCount; /*!< Specifies the number of pixel clocks to count before starting a capture. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_VerticalLineCount; /*!< Specifies the number of lines to be captured from the starting point. - This parameter can be a value between 0x00 and 0x3FFF */ - - uint16_t DCMI_CaptureCount; /*!< Specifies the number of pixel clocks to be captured from the starting - point on the same line. - This parameter can be a value between 0x00 and 0x3FFF */ -} DCMI_CROPInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t DCMI_LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t DCMI_LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t DCMI_FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants - * @{ - */ - -/** @defgroup DCMI_Capture_Mode - * @{ - */ -#define DCMI_CaptureMode_Continuous ((uint16_t)0x0000) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_CaptureMode_SnapShot ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame through the DMA */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \ - ((MODE) == DCMI_CaptureMode_SnapShot)) -/** - * @} - */ - - -/** @defgroup DCMI_Synchronization_Mode - * @{ - */ -#define DCMI_SynchroMode_Hardware ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SynchroMode_Embedded ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with - synchronization codes embedded in the data flow */ -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \ - ((MODE) == DCMI_SynchroMode_Embedded)) -/** - * @} - */ - - -/** @defgroup DCMI_PIXCK_Polarity - * @{ - */ -#define DCMI_PCKPolarity_Falling ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPolarity_Rising ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */ -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \ - ((POLARITY) == DCMI_PCKPolarity_Rising)) -/** - * @} - */ - - -/** @defgroup DCMI_VSYNC_Polarity - * @{ - */ -#define DCMI_VSPolarity_Low ((uint16_t)0x0000) /*!< Vertical synchronization active Low */ -#define DCMI_VSPolarity_High ((uint16_t)0x0080) /*!< Vertical synchronization active High */ -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \ - ((POLARITY) == DCMI_VSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_HSYNC_Polarity - * @{ - */ -#define DCMI_HSPolarity_Low ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPolarity_High ((uint16_t)0x0040) /*!< Horizontal synchronization active High */ -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \ - ((POLARITY) == DCMI_HSPolarity_High)) -/** - * @} - */ - - -/** @defgroup DCMI_Capture_Rate - * @{ - */ -#define DCMI_CaptureRate_All_Frame ((uint16_t)0x0000) /*!< All frames are captured */ -#define DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100) /*!< Every alternate frame captured */ -#define DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200) /*!< One frame in 4 frames captured */ -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \ - ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\ - ((RATE) == DCMI_CaptureRate_1of4_Frame)) -/** - * @} - */ - - -/** @defgroup DCMI_Extended_Data_Mode - * @{ - */ -#define DCMI_ExtendedDataMode_8b ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_10b ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_12b ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */ -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \ - ((DATA) == DCMI_ExtendedDataMode_10b) ||\ - ((DATA) == DCMI_ExtendedDataMode_12b) ||\ - ((DATA) == DCMI_ExtendedDataMode_14b)) -/** - * @} - */ - - -/** @defgroup DCMI_interrupt_sources - * @{ - */ -#define DCMI_IT_FRAME ((uint16_t)0x0001) -#define DCMI_IT_OVF ((uint16_t)0x0002) -#define DCMI_IT_ERR ((uint16_t)0x0004) -#define DCMI_IT_VSYNC ((uint16_t)0x0008) -#define DCMI_IT_LINE ((uint16_t)0x0010) -#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000)) -#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \ - ((IT) == DCMI_IT_OVF) || \ - ((IT) == DCMI_IT_ERR) || \ - ((IT) == DCMI_IT_VSYNC) || \ - ((IT) == DCMI_IT_LINE)) -/** - * @} - */ - - -/** @defgroup DCMI_Flags - * @{ - */ -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint16_t)0x2001) -#define DCMI_FLAG_VSYNC ((uint16_t)0x2002) -#define DCMI_FLAG_FNE ((uint16_t)0x2004) -/** - * @brief DCMI RISR register - */ -#define DCMI_FLAG_FRAMERI ((uint16_t)0x0001) -#define DCMI_FLAG_OVFRI ((uint16_t)0x0002) -#define DCMI_FLAG_ERRRI ((uint16_t)0x0004) -#define DCMI_FLAG_VSYNCRI ((uint16_t)0x0008) -#define DCMI_FLAG_LINERI ((uint16_t)0x0010) -/** - * @brief DCMI MISR register - */ -#define DCMI_FLAG_FRAMEMI ((uint16_t)0x1001) -#define DCMI_FLAG_OVFMI ((uint16_t)0x1002) -#define DCMI_FLAG_ERRMI ((uint16_t)0x1004) -#define DCMI_FLAG_VSYNCMI ((uint16_t)0x1008) -#define DCMI_FLAG_LINEMI ((uint16_t)0x1010) -#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \ - ((FLAG) == DCMI_FLAG_VSYNC) || \ - ((FLAG) == DCMI_FLAG_FNE) || \ - ((FLAG) == DCMI_FLAG_FRAMERI) || \ - ((FLAG) == DCMI_FLAG_OVFRI) || \ - ((FLAG) == DCMI_FLAG_ERRRI) || \ - ((FLAG) == DCMI_FLAG_VSYNCRI) || \ - ((FLAG) == DCMI_FLAG_LINERI) || \ - ((FLAG) == DCMI_FLAG_FRAMEMI) || \ - ((FLAG) == DCMI_FLAG_OVFMI) || \ - ((FLAG) == DCMI_FLAG_ERRMI) || \ - ((FLAG) == DCMI_FLAG_VSYNCMI) || \ - ((FLAG) == DCMI_FLAG_LINEMI)) - -#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DCMI configuration to the default reset state ****/ -void DCMI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct); -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct); -void DCMI_CROPCmd(FunctionalState NewState); -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct); -void DCMI_JPEGCmd(FunctionalState NewState); - -/* Image capture functions ****************************************************/ -void DCMI_Cmd(FunctionalState NewState); -void DCMI_CaptureCmd(FunctionalState NewState); -uint32_t DCMI_ReadData(void); - -/* Interrupts and flags management functions **********************************/ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState); -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG); -void DCMI_ClearFlag(uint16_t DCMI_FLAG); -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT); -void DCMI_ClearITPendingBit(uint16_t DCMI_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DCMI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h deleted file mode 100644 index 3c0c38969..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h +++ /dev/null @@ -1,609 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the DMA firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA_H -#define __STM32F4xx_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA Init structure definition - */ - -typedef struct -{ - uint32_t DMA_Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMA_channel */ - - uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */ - - uint32_t DMA_Memory0BaseAddr; /*!< Specifies the memory 0 base address for DMAy Streamx. - This memory is the default memory used when double buffer mode is - not enabled. */ - - uint32_t DMA_DIR; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_data_transfer_direction */ - - uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Stream. - The data unit is equal to the configuration set in DMA_PeripheralDataSize - or DMA_MemoryDataSize members depending in the transfer direction. */ - - uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_peripheral_incremented_mode */ - - uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_memory_incremented_mode */ - - uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_peripheral_data_size */ - - uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_memory_data_size */ - - uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_circular_normal_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_priority_level */ - - uint32_t DMA_FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream. - This parameter can be a value of @ref DMA_fifo_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected Stream */ - - uint32_t DMA_FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_fifo_threshold_level */ - - uint32_t DMA_MemoryBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t DMA_PeripheralBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptable - transaction. This parameter can be a value of @ref DMA_peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants - * @{ - */ - -#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \ - ((PERIPH) == DMA1_Stream1) || \ - ((PERIPH) == DMA1_Stream2) || \ - ((PERIPH) == DMA1_Stream3) || \ - ((PERIPH) == DMA1_Stream4) || \ - ((PERIPH) == DMA1_Stream5) || \ - ((PERIPH) == DMA1_Stream6) || \ - ((PERIPH) == DMA1_Stream7) || \ - ((PERIPH) == DMA2_Stream0) || \ - ((PERIPH) == DMA2_Stream1) || \ - ((PERIPH) == DMA2_Stream2) || \ - ((PERIPH) == DMA2_Stream3) || \ - ((PERIPH) == DMA2_Stream4) || \ - ((PERIPH) == DMA2_Stream5) || \ - ((PERIPH) == DMA2_Stream6) || \ - ((PERIPH) == DMA2_Stream7)) - -#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \ - ((CONTROLLER) == DMA2)) - -/** @defgroup DMA_channel - * @{ - */ -#define DMA_Channel_0 ((uint32_t)0x00000000) -#define DMA_Channel_1 ((uint32_t)0x02000000) -#define DMA_Channel_2 ((uint32_t)0x04000000) -#define DMA_Channel_3 ((uint32_t)0x06000000) -#define DMA_Channel_4 ((uint32_t)0x08000000) -#define DMA_Channel_5 ((uint32_t)0x0A000000) -#define DMA_Channel_6 ((uint32_t)0x0C000000) -#define DMA_Channel_7 ((uint32_t)0x0E000000) - -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \ - ((CHANNEL) == DMA_Channel_1) || \ - ((CHANNEL) == DMA_Channel_2) || \ - ((CHANNEL) == DMA_Channel_3) || \ - ((CHANNEL) == DMA_Channel_4) || \ - ((CHANNEL) == DMA_Channel_5) || \ - ((CHANNEL) == DMA_Channel_6) || \ - ((CHANNEL) == DMA_Channel_7)) -/** - * @} - */ - - -/** @defgroup DMA_data_transfer_direction - * @{ - */ -#define DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000) -#define DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040) -#define DMA_DIR_MemoryToMemory ((uint32_t)0x00000080) - -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \ - ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || \ - ((DIRECTION) == DMA_DIR_MemoryToMemory)) -/** - * @} - */ - - -/** @defgroup DMA_data_buffer_size - * @{ - */ -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_incremented_mode - * @{ - */ -#define DMA_PeripheralInc_Enable ((uint32_t)0x00000200) -#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \ - ((STATE) == DMA_PeripheralInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_memory_incremented_mode - * @{ - */ -#define DMA_MemoryInc_Enable ((uint32_t)0x00000400) -#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \ - ((STATE) == DMA_MemoryInc_Disable)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_data_size - * @{ - */ -#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) -#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800) -#define DMA_PeripheralDataSize_Word ((uint32_t)0x00001000) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \ - ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \ - ((SIZE) == DMA_PeripheralDataSize_Word)) -/** - * @} - */ - - -/** @defgroup DMA_memory_data_size - * @{ - */ -#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) -#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000) -#define DMA_MemoryDataSize_Word ((uint32_t)0x00004000) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \ - ((SIZE) == DMA_MemoryDataSize_HalfWord) || \ - ((SIZE) == DMA_MemoryDataSize_Word )) -/** - * @} - */ - - -/** @defgroup DMA_circular_normal_mode - * @{ - */ -#define DMA_Mode_Normal ((uint32_t)0x00000000) -#define DMA_Mode_Circular ((uint32_t)0x00000100) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \ - ((MODE) == DMA_Mode_Circular)) -/** - * @} - */ - - -/** @defgroup DMA_priority_level - * @{ - */ -#define DMA_Priority_Low ((uint32_t)0x00000000) -#define DMA_Priority_Medium ((uint32_t)0x00010000) -#define DMA_Priority_High ((uint32_t)0x00020000) -#define DMA_Priority_VeryHigh ((uint32_t)0x00030000) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || \ - ((PRIORITY) == DMA_Priority_Medium) || \ - ((PRIORITY) == DMA_Priority_High) || \ - ((PRIORITY) == DMA_Priority_VeryHigh)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_direct_mode - * @{ - */ -#define DMA_FIFOMode_Disable ((uint32_t)0x00000000) -#define DMA_FIFOMode_Enable ((uint32_t)0x00000004) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \ - ((STATE) == DMA_FIFOMode_Enable)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_threshold_level - * @{ - */ -#define DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000) -#define DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001) -#define DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002) -#define DMA_FIFOThreshold_Full ((uint32_t)0x00000003) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \ - ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == DMA_FIFOThreshold_Full)) -/** - * @} - */ - - -/** @defgroup DMA_memory_burst - * @{ - */ -#define DMA_MemoryBurst_Single ((uint32_t)0x00000000) -#define DMA_MemoryBurst_INC4 ((uint32_t)0x00800000) -#define DMA_MemoryBurst_INC8 ((uint32_t)0x01000000) -#define DMA_MemoryBurst_INC16 ((uint32_t)0x01800000) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \ - ((BURST) == DMA_MemoryBurst_INC4) || \ - ((BURST) == DMA_MemoryBurst_INC8) || \ - ((BURST) == DMA_MemoryBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_burst - * @{ - */ -#define DMA_PeripheralBurst_Single ((uint32_t)0x00000000) -#define DMA_PeripheralBurst_INC4 ((uint32_t)0x00200000) -#define DMA_PeripheralBurst_INC8 ((uint32_t)0x00400000) -#define DMA_PeripheralBurst_INC16 ((uint32_t)0x00600000) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \ - ((BURST) == DMA_PeripheralBurst_INC4) || \ - ((BURST) == DMA_PeripheralBurst_INC8) || \ - ((BURST) == DMA_PeripheralBurst_INC16)) -/** - * @} - */ - - -/** @defgroup DMA_fifo_status_level - * @{ - */ -#define DMA_FIFOStatus_Less1QuarterFull ((uint32_t)0x00000000 << 3) -#define DMA_FIFOStatus_1QuarterFull ((uint32_t)0x00000001 << 3) -#define DMA_FIFOStatus_HalfFull ((uint32_t)0x00000002 << 3) -#define DMA_FIFOStatus_3QuartersFull ((uint32_t)0x00000003 << 3) -#define DMA_FIFOStatus_Empty ((uint32_t)0x00000004 << 3) -#define DMA_FIFOStatus_Full ((uint32_t)0x00000005 << 3) - -#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == DMA_FIFOStatus_HalfFull) || \ - ((STATUS) == DMA_FIFOStatus_1QuarterFull) || \ - ((STATUS) == DMA_FIFOStatus_3QuartersFull) || \ - ((STATUS) == DMA_FIFOStatus_Full) || \ - ((STATUS) == DMA_FIFOStatus_Empty)) -/** - * @} - */ - -/** @defgroup DMA_flags_definition - * @{ - */ -#define DMA_FLAG_FEIF0 ((uint32_t)0x10800001) -#define DMA_FLAG_DMEIF0 ((uint32_t)0x10800004) -#define DMA_FLAG_TEIF0 ((uint32_t)0x10000008) -#define DMA_FLAG_HTIF0 ((uint32_t)0x10000010) -#define DMA_FLAG_TCIF0 ((uint32_t)0x10000020) -#define DMA_FLAG_FEIF1 ((uint32_t)0x10000040) -#define DMA_FLAG_DMEIF1 ((uint32_t)0x10000100) -#define DMA_FLAG_TEIF1 ((uint32_t)0x10000200) -#define DMA_FLAG_HTIF1 ((uint32_t)0x10000400) -#define DMA_FLAG_TCIF1 ((uint32_t)0x10000800) -#define DMA_FLAG_FEIF2 ((uint32_t)0x10010000) -#define DMA_FLAG_DMEIF2 ((uint32_t)0x10040000) -#define DMA_FLAG_TEIF2 ((uint32_t)0x10080000) -#define DMA_FLAG_HTIF2 ((uint32_t)0x10100000) -#define DMA_FLAG_TCIF2 ((uint32_t)0x10200000) -#define DMA_FLAG_FEIF3 ((uint32_t)0x10400000) -#define DMA_FLAG_DMEIF3 ((uint32_t)0x11000000) -#define DMA_FLAG_TEIF3 ((uint32_t)0x12000000) -#define DMA_FLAG_HTIF3 ((uint32_t)0x14000000) -#define DMA_FLAG_TCIF3 ((uint32_t)0x18000000) -#define DMA_FLAG_FEIF4 ((uint32_t)0x20000001) -#define DMA_FLAG_DMEIF4 ((uint32_t)0x20000004) -#define DMA_FLAG_TEIF4 ((uint32_t)0x20000008) -#define DMA_FLAG_HTIF4 ((uint32_t)0x20000010) -#define DMA_FLAG_TCIF4 ((uint32_t)0x20000020) -#define DMA_FLAG_FEIF5 ((uint32_t)0x20000040) -#define DMA_FLAG_DMEIF5 ((uint32_t)0x20000100) -#define DMA_FLAG_TEIF5 ((uint32_t)0x20000200) -#define DMA_FLAG_HTIF5 ((uint32_t)0x20000400) -#define DMA_FLAG_TCIF5 ((uint32_t)0x20000800) -#define DMA_FLAG_FEIF6 ((uint32_t)0x20010000) -#define DMA_FLAG_DMEIF6 ((uint32_t)0x20040000) -#define DMA_FLAG_TEIF6 ((uint32_t)0x20080000) -#define DMA_FLAG_HTIF6 ((uint32_t)0x20100000) -#define DMA_FLAG_TCIF6 ((uint32_t)0x20200000) -#define DMA_FLAG_FEIF7 ((uint32_t)0x20400000) -#define DMA_FLAG_DMEIF7 ((uint32_t)0x21000000) -#define DMA_FLAG_TEIF7 ((uint32_t)0x22000000) -#define DMA_FLAG_HTIF7 ((uint32_t)0x24000000) -#define DMA_FLAG_TCIF7 ((uint32_t)0x28000000) - -#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \ - (((FLAG) & 0xC002F082) == 0x00) && ((FLAG) != 0x00)) - -#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0) || ((FLAG) == DMA_FLAG_HTIF0) || \ - ((FLAG) == DMA_FLAG_TEIF0) || ((FLAG) == DMA_FLAG_DMEIF0) || \ - ((FLAG) == DMA_FLAG_FEIF0) || ((FLAG) == DMA_FLAG_TCIF1) || \ - ((FLAG) == DMA_FLAG_HTIF1) || ((FLAG) == DMA_FLAG_TEIF1) || \ - ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1) || \ - ((FLAG) == DMA_FLAG_TCIF2) || ((FLAG) == DMA_FLAG_HTIF2) || \ - ((FLAG) == DMA_FLAG_TEIF2) || ((FLAG) == DMA_FLAG_DMEIF2) || \ - ((FLAG) == DMA_FLAG_FEIF2) || ((FLAG) == DMA_FLAG_TCIF3) || \ - ((FLAG) == DMA_FLAG_HTIF3) || ((FLAG) == DMA_FLAG_TEIF3) || \ - ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3) || \ - ((FLAG) == DMA_FLAG_TCIF4) || ((FLAG) == DMA_FLAG_HTIF4) || \ - ((FLAG) == DMA_FLAG_TEIF4) || ((FLAG) == DMA_FLAG_DMEIF4) || \ - ((FLAG) == DMA_FLAG_FEIF4) || ((FLAG) == DMA_FLAG_TCIF5) || \ - ((FLAG) == DMA_FLAG_HTIF5) || ((FLAG) == DMA_FLAG_TEIF5) || \ - ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5) || \ - ((FLAG) == DMA_FLAG_TCIF6) || ((FLAG) == DMA_FLAG_HTIF6) || \ - ((FLAG) == DMA_FLAG_TEIF6) || ((FLAG) == DMA_FLAG_DMEIF6) || \ - ((FLAG) == DMA_FLAG_FEIF6) || ((FLAG) == DMA_FLAG_TCIF7) || \ - ((FLAG) == DMA_FLAG_HTIF7) || ((FLAG) == DMA_FLAG_TEIF7) || \ - ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_interrupt_enable_definitions - * @{ - */ -#define DMA_IT_TC ((uint32_t)0x00000010) -#define DMA_IT_HT ((uint32_t)0x00000008) -#define DMA_IT_TE ((uint32_t)0x00000004) -#define DMA_IT_DME ((uint32_t)0x00000002) -#define DMA_IT_FE ((uint32_t)0x00000080) - -#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - - -/** @defgroup DMA_interrupts_definitions - * @{ - */ -#define DMA_IT_FEIF0 ((uint32_t)0x90000001) -#define DMA_IT_DMEIF0 ((uint32_t)0x10001004) -#define DMA_IT_TEIF0 ((uint32_t)0x10002008) -#define DMA_IT_HTIF0 ((uint32_t)0x10004010) -#define DMA_IT_TCIF0 ((uint32_t)0x10008020) -#define DMA_IT_FEIF1 ((uint32_t)0x90000040) -#define DMA_IT_DMEIF1 ((uint32_t)0x10001100) -#define DMA_IT_TEIF1 ((uint32_t)0x10002200) -#define DMA_IT_HTIF1 ((uint32_t)0x10004400) -#define DMA_IT_TCIF1 ((uint32_t)0x10008800) -#define DMA_IT_FEIF2 ((uint32_t)0x90010000) -#define DMA_IT_DMEIF2 ((uint32_t)0x10041000) -#define DMA_IT_TEIF2 ((uint32_t)0x10082000) -#define DMA_IT_HTIF2 ((uint32_t)0x10104000) -#define DMA_IT_TCIF2 ((uint32_t)0x10208000) -#define DMA_IT_FEIF3 ((uint32_t)0x90400000) -#define DMA_IT_DMEIF3 ((uint32_t)0x11001000) -#define DMA_IT_TEIF3 ((uint32_t)0x12002000) -#define DMA_IT_HTIF3 ((uint32_t)0x14004000) -#define DMA_IT_TCIF3 ((uint32_t)0x18008000) -#define DMA_IT_FEIF4 ((uint32_t)0xA0000001) -#define DMA_IT_DMEIF4 ((uint32_t)0x20001004) -#define DMA_IT_TEIF4 ((uint32_t)0x20002008) -#define DMA_IT_HTIF4 ((uint32_t)0x20004010) -#define DMA_IT_TCIF4 ((uint32_t)0x20008020) -#define DMA_IT_FEIF5 ((uint32_t)0xA0000040) -#define DMA_IT_DMEIF5 ((uint32_t)0x20001100) -#define DMA_IT_TEIF5 ((uint32_t)0x20002200) -#define DMA_IT_HTIF5 ((uint32_t)0x20004400) -#define DMA_IT_TCIF5 ((uint32_t)0x20008800) -#define DMA_IT_FEIF6 ((uint32_t)0xA0010000) -#define DMA_IT_DMEIF6 ((uint32_t)0x20041000) -#define DMA_IT_TEIF6 ((uint32_t)0x20082000) -#define DMA_IT_HTIF6 ((uint32_t)0x20104000) -#define DMA_IT_TCIF6 ((uint32_t)0x20208000) -#define DMA_IT_FEIF7 ((uint32_t)0xA0400000) -#define DMA_IT_DMEIF7 ((uint32_t)0x21001000) -#define DMA_IT_TEIF7 ((uint32_t)0x22002000) -#define DMA_IT_HTIF7 ((uint32_t)0x24004000) -#define DMA_IT_TCIF7 ((uint32_t)0x28008000) - -#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \ - (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \ - (((IT) & 0x40820082) == 0x00)) - -#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0) || \ - ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \ - ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1) || \ - ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1) || \ - ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1) || \ - ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2) || \ - ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \ - ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3) || \ - ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3) || \ - ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3) || \ - ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4) || \ - ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \ - ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5) || \ - ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5) || \ - ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5) || \ - ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6) || \ - ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \ - ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7) || \ - ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7) || \ - ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7)) -/** - * @} - */ - - -/** @defgroup DMA_peripheral_increment_offset - * @{ - */ -#define DMA_PINCOS_Psize ((uint32_t)0x00000000) -#define DMA_PINCOS_WordAligned ((uint32_t)0x00008000) - -#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \ - ((SIZE) == DMA_PINCOS_WordAligned)) -/** - * @} - */ - - -/** @defgroup DMA_flow_controller_definitions - * @{ - */ -#define DMA_FlowCtrl_Memory ((uint32_t)0x00000000) -#define DMA_FlowCtrl_Peripheral ((uint32_t)0x00000020) - -#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \ - ((CTRL) == DMA_FlowCtrl_Peripheral)) -/** - * @} - */ - - -/** @defgroup DMA_memory_targets_definitions - * @{ - */ -#define DMA_Memory_0 ((uint32_t)0x00000000) -#define DMA_Memory_1 ((uint32_t)0x00080000) - -#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the DMA configuration to the default reset state *****/ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Initialization and Configuration functions *********************************/ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct); -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - -/* Optional Configuration functions *******************************************/ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos); -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl); - -/* Data Counter functions *****************************************************/ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Double Buffer mode functions ***********************************************/ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory); -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget); -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - -/* Interrupts and flags management functions **********************************/ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_DMA_H */ - -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h deleted file mode 100644 index b661311a9..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h +++ /dev/null @@ -1,475 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma2d.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the DMA2D firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_DMA2D_H -#define __STM32F4xx_DMA2D_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief DMA2D Init structure definition - */ - -typedef struct -{ - uint32_t DMA2D_Mode; /*!< configures the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_MODE */ - - uint32_t DMA2D_CMode; /*!< configures the color format of the output image. - This parameter can be one value of @ref DMA2D_CMODE */ - - uint32_t DMA2D_OutputBlue; /*!< configures the blue value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0xFF if RGB888 color mode is slected - - from 0x00 to 0x1F if RGB565 color mode is slected - - from 0x00 to 0x1F if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is selected - - from 0x00 to 0xFF if RGB888 color mode is selected - - from 0x00 to 0x2F if RGB565 color mode is selected - - from 0x00 to 0x1F if ARGB1555 color mode is selected - - from 0x00 to 0x0F if ARGB4444 color mode is selected */ - - uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is slected - - from 0x00 to 0xFF if RGB888 color mode is slected - - from 0x00 to 0x1F if RGB565 color mode is slected - - from 0x00 to 0x1F if ARGB1555 color mode is slected - - from 0x00 to 0x0F if ARGB4444 color mode is slected */ - - uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color. - This parameter must range: - - from 0x00 to 0xFF if ARGB8888 color mode is selected - - from 0x00 to 0x01 if ARGB1555 color mode is selected - - from 0x00 to 0x0F if ARGB4444 color mode is selected */ - - uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter - must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_OutputOffset; /*!< Specifies the Offset value. This parameter must be range from - 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered. - This parameter must range from 0x0000 to 0xFFFF */ - - uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transferred. - This parameter must range from 0x0000 to 0x3FFF */ -} DMA2D_InitTypeDef; - - - -typedef struct -{ - uint32_t DMA2D_FGMA; /*!< configures the DMA2D foreground memory address. - This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_FGO; /*!< configures the DMA2D foreground offset. - This parameter must be range from 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_FGCM; /*!< configures the DMA2D foreground color mode . - This parameter can be one value of @ref DMA2D_FGCM */ - - uint32_t DMA2D_FG_CLUT_CM; /*!< configures the DMA2D foreground CLUT color mode. - This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ - - uint32_t DMA2D_FG_CLUT_SIZE; /*!< configures the DMA2D foreground CLUT size. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGPFC_ALPHA_MODE; /*!< configures the DMA2D foreground alpha mode. - This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ - - uint32_t DMA2D_FGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D foreground alpha value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_BLUE; /*!< Specifies the DMA2D foreground blue value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_GREEN; /*!< Specifies the DMA2D foreground green value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGC_RED; /*!< Specifies the DMA2D foreground red value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_FGCMAR; /*!< Configures the DMA2D foreground CLUT memory address. - This parameter must range from 0x00000000 to 0xFFFFFFFF. */ -} DMA2D_FG_InitTypeDef; - - -typedef struct -{ - uint32_t DMA2D_BGMA; /*!< configures the DMA2D background memory address. - This parameter must be range from 0x00000000 to 0xFFFFFFFF. */ - - uint32_t DMA2D_BGO; /*!< configures the DMA2D background offset. - This parameter must be range from 0x0000 to 0x3FFF. */ - - uint32_t DMA2D_BGCM; /*!< configures the DMA2D background color mode . - This parameter can be one value of @ref DMA2D_FGCM */ - - uint32_t DMA2D_BG_CLUT_CM; /*!< configures the DMA2D background CLUT color mode. - This parameter can be one value of @ref DMA2D_FG_CLUT_CM */ - - uint32_t DMA2D_BG_CLUT_SIZE; /*!< configures the DMA2D background CLUT size. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGPFC_ALPHA_MODE; /*!< configures the DMA2D background alpha mode. - This parameter can be one value of @ref DMA2D_FGPFC_ALPHA_MODE */ - - uint32_t DMA2D_BGPFC_ALPHA_VALUE; /*!< Specifies the DMA2D background alpha value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_BLUE; /*!< Specifies the DMA2D background blue value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_GREEN; /*!< Specifies the DMA2D background green value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGC_RED; /*!< Specifies the DMA2D background red value - must be range from 0x00 to 0xFF. */ - - uint32_t DMA2D_BGCMAR; /*!< Configures the DMA2D background CLUT memory address. - This parameter must range from 0x00000000 to 0xFFFFFFFF. */ -} DMA2D_BG_InitTypeDef; - - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA2D_Exported_Constants - * @{ - */ - -/** @defgroup DMA2D_MODE - * @{ - */ - - -#define DMA2D_M2M ((uint32_t)0x00000000) -#define DMA2D_M2M_PFC ((uint32_t)0x00010000) -#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) -#define DMA2D_R2M ((uint32_t)0x00030000) - -#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ - ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) - - -/** - * @} - */ - -/** @defgroup DMA2D_CMODE - * @{ - */ -#define DMA2D_ARGB8888 ((uint32_t)0x00000000) -#define DMA2D_RGB888 ((uint32_t)0x00000001) -#define DMA2D_RGB565 ((uint32_t)0x00000002) -#define DMA2D_ARGB1555 ((uint32_t)0x00000003) -#define DMA2D_ARGB4444 ((uint32_t)0x00000004) - -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \ - ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \ - ((MODE_ARGB) == DMA2D_ARGB4444)) - - -/** - * @} - */ - -/** @defgroup DMA2D_OUTPUT_COLOR - * @{ - */ -#define DMA2D_Output_Color ((uint32_t)0x000000FF) - -#define IS_DMA2D_OGREEN(OGREEN) ((OGREEN) <= DMA2D_Output_Color) -#define IS_DMA2D_ORED(ORED) ((ORED) <= DMA2D_Output_Color) -#define IS_DMA2D_OBLUE(OBLUE) ((OBLUE) <= DMA2D_Output_Color) -#define IS_DMA2D_OALPHA(OALPHA) ((OALPHA) <= DMA2D_Output_Color) - -/** - * @} - */ - -/** @defgroup DMA2D_OUTPUT_OFFSET - * @{ - */ -#define DMA2D_OUTPUT_OFFSET ((uint32_t)0x00003FFF) - -#define IS_DMA2D_OUTPUT_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OUTPUT_OFFSET) - - -/** - * @} - */ - -/** @defgroup DMA2D_SIZE - * @{ - */ - -#define DMA2D_pixel ((uint32_t)0x00003FFF) -#define DMA2D_Line ((uint32_t)0x0000FFFF) - -#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_Line) -#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_pixel) - - -/** - * @} - */ - -/** @defgroup DMA2D_OFFSET - * @{ - */ -#define OFFSET ((uint32_t)0x00003FFF) - -#define IS_DMA2D_FGO(FGO) ((FGO) <= OFFSET) - -#define IS_DMA2D_BGO(BGO) ((BGO) <= OFFSET) - -/** - * @} - */ - - -/** @defgroup DMA2D_FGCM - * @{ - */ - -#define CM_ARGB8888 ((uint32_t)0x00000000) -#define CM_RGB888 ((uint32_t)0x00000001) -#define CM_RGB565 ((uint32_t)0x00000002) -#define CM_ARGB1555 ((uint32_t)0x00000003) -#define CM_ARGB4444 ((uint32_t)0x00000004) -#define CM_L8 ((uint32_t)0x00000005) -#define CM_AL44 ((uint32_t)0x00000006) -#define CM_AL88 ((uint32_t)0x00000007) -#define CM_L4 ((uint32_t)0x00000008) -#define CM_A8 ((uint32_t)0x00000009) -#define CM_A4 ((uint32_t)0x0000000A) - -#define IS_DMA2D_FGCM(FGCM) (((FGCM) == CM_ARGB8888) || ((FGCM) == CM_RGB888) || \ - ((FGCM) == CM_RGB565) || ((FGCM) == CM_ARGB1555) || \ - ((FGCM) == CM_ARGB4444) || ((FGCM) == CM_L8) || \ - ((FGCM) == CM_AL44) || ((FGCM) == CM_AL88) || \ - ((FGCM) == CM_L4) || ((FGCM) == CM_A8) || \ - ((FGCM) == CM_A4)) - -#define IS_DMA2D_BGCM(BGCM) (((BGCM) == CM_ARGB8888) || ((BGCM) == CM_RGB888) || \ - ((BGCM) == CM_RGB565) || ((BGCM) == CM_ARGB1555) || \ - ((BGCM) == CM_ARGB4444) || ((BGCM) == CM_L8) || \ - ((BGCM) == CM_AL44) || ((BGCM) == CM_AL88) || \ - ((BGCM) == CM_L4) || ((BGCM) == CM_A8) || \ - ((BGCM) == CM_A4)) - -/** - * @} - */ - -/** @defgroup DMA2D_FG_CLUT_CM - * @{ - */ - -#define CLUT_CM_ARGB8888 ((uint32_t)0x00000000) -#define CLUT_CM_RGB888 ((uint32_t)0x00000001) - -#define IS_DMA2D_FG_CLUT_CM(FG_CLUT_CM) (((FG_CLUT_CM) == CLUT_CM_ARGB8888) || ((FG_CLUT_CM) == CLUT_CM_RGB888)) - -#define IS_DMA2D_BG_CLUT_CM(BG_CLUT_CM) (((BG_CLUT_CM) == CLUT_CM_ARGB8888) || ((BG_CLUT_CM) == CLUT_CM_RGB888)) - -/** - * @} - */ - -/** @defgroup DMA2D_FG_COLOR_VALUE - * @{ - */ - -#define COLOR_VALUE ((uint32_t)0x000000FF) - -#define IS_DMA2D_FG_CLUT_SIZE(FG_CLUT_SIZE) ((FG_CLUT_SIZE) <= COLOR_VALUE) - -#define IS_DMA2D_FG_ALPHA_VALUE(FG_ALPHA_VALUE) ((FG_ALPHA_VALUE) <= COLOR_VALUE) -#define IS_DMA2D_FGC_BLUE(FGC_BLUE) ((FGC_BLUE) <= COLOR_VALUE) -#define IS_DMA2D_FGC_GREEN(FGC_GREEN) ((FGC_GREEN) <= COLOR_VALUE) -#define IS_DMA2D_FGC_RED(FGC_RED) ((FGC_RED) <= COLOR_VALUE) - -#define IS_DMA2D_BG_CLUT_SIZE(BG_CLUT_SIZE) ((BG_CLUT_SIZE) <= COLOR_VALUE) - -#define IS_DMA2D_BG_ALPHA_VALUE(BG_ALPHA_VALUE) ((BG_ALPHA_VALUE) <= COLOR_VALUE) -#define IS_DMA2D_BGC_BLUE(BGC_BLUE) ((BGC_BLUE) <= COLOR_VALUE) -#define IS_DMA2D_BGC_GREEN(BGC_GREEN) ((BGC_GREEN) <= COLOR_VALUE) -#define IS_DMA2D_BGC_RED(BGC_RED) ((BGC_RED) <= COLOR_VALUE) - -/** - * @} - */ - -/** DMA2D_FGPFC_ALPHA_MODE - * @{ - */ - -#define NO_MODIF_ALPHA_VALUE ((uint32_t)0x00000000) -#define REPLACE_ALPHA_VALUE ((uint32_t)0x00000001) -#define COMBINE_ALPHA_VALUE ((uint32_t)0x00000002) - -#define IS_DMA2D_FG_ALPHA_MODE(FG_ALPHA_MODE) (((FG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ - ((FG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ - ((FG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) - -#define IS_DMA2D_BG_ALPHA_MODE(BG_ALPHA_MODE) (((BG_ALPHA_MODE) == NO_MODIF_ALPHA_VALUE) || \ - ((BG_ALPHA_MODE) == REPLACE_ALPHA_VALUE) || \ - ((BG_ALPHA_MODE) == COMBINE_ALPHA_VALUE)) - -/** - * @} - */ - -/** @defgroup DMA2D_Interrupts - * @{ - */ - -#define DMA2D_IT_CE DMA2D_CR_CEIE -#define DMA2D_IT_CTC DMA2D_CR_CTCIE -#define DMA2D_IT_CAE DMA2D_CR_CAEIE -#define DMA2D_IT_TW DMA2D_CR_TWIE -#define DMA2D_IT_TC DMA2D_CR_TCIE -#define DMA2D_IT_TE DMA2D_CR_TEIE - -#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ - ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ - ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) - -/** - * @} - */ - -/** @defgroup DMA2D_Flag - * @{ - */ - -#define DMA2D_FLAG_CE DMA2D_ISR_CEIF -#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF -#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF -#define DMA2D_FLAG_TW DMA2D_ISR_TWIF -#define DMA2D_FLAG_TC DMA2D_ISR_TCIF -#define DMA2D_FLAG_TE DMA2D_ISR_TEIF - - -#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ - ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ - ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) - - -/** - * @} - */ - -/** @defgroup DMA2D_DeadTime - * @{ - */ - -#define DEADTIME ((uint32_t)0x000000FF) - -#define IS_DMA2D_DEAD_TIME(DEAD_TIME) ((DEAD_TIME) <= DEADTIME) - - -#define LINE_WATERMARK DMA2D_LWR_LW - -#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ - -/* Function used to set the DMA2D configuration to the default reset state *****/ -void DMA2D_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct); -void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct); -void DMA2D_StartTransfer(void); -void DMA2D_AbortTransfer(void); -void DMA2D_Suspend(FunctionalState NewState); -void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); -void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct); -void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); -void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct); -void DMA2D_FGStart(FunctionalState NewState); -void DMA2D_BGStart(FunctionalState NewState); -void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState); -void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig); - -/* Interrupts and flags management functions **********************************/ -void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState); -FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG); -void DMA2D_ClearFlag(uint32_t DMA2D_FLAG); -ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT); -void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_DMA2D_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h deleted file mode 100644 index e89061608..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the EXTI firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_EXTI_H -#define __STM32F4xx_EXTI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief EXTI mode enumeration - */ - -typedef enum -{ - EXTI_Mode_Interrupt = 0x00, - EXTI_Mode_Event = 0x04 -}EXTIMode_TypeDef; - -#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) - -/** - * @brief EXTI Trigger enumeration - */ - -typedef enum -{ - EXTI_Trigger_Rising = 0x08, - EXTI_Trigger_Falling = 0x0C, - EXTI_Trigger_Rising_Falling = 0x10 -}EXTITrigger_TypeDef; - -#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ - ((TRIGGER) == EXTI_Trigger_Falling) || \ - ((TRIGGER) == EXTI_Trigger_Rising_Falling)) -/** - * @brief EXTI Init Structure definition - */ - -typedef struct -{ - uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. - This parameter can be any combination value of @ref EXTI_Lines */ - - EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTIMode_TypeDef */ - - EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTITrigger_TypeDef */ - - FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ -}EXTI_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Constants - * @{ - */ - -/** @defgroup EXTI_Lines - * @{ - */ - -#define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ -#define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ -#define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ -#define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ -#define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ -#define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ -#define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ -#define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ -#define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ -#define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ -#define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ -#define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ -#define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ -#define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ -#define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ -#define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ -#define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ -#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ - - -#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00)) - -#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ - ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ - ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ - ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ - ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ - ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ - ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ - ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ - ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ - ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ - ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\ - ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the EXTI configuration to the default reset state *****/ -void EXTI_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); - -/* Interrupts and flags management functions **********************************/ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); -void EXTI_ClearFlag(uint32_t EXTI_Line); -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); -void EXTI_ClearITPendingBit(uint32_t EXTI_Line); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_EXTI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h deleted file mode 100644 index bae424d35..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h +++ /dev/null @@ -1,497 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_H -#define __STM32F4xx_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** - * @brief FLASH Status - */ -typedef enum -{ - FLASH_BUSY = 1, - FLASH_ERROR_RD, - FLASH_ERROR_PGS, - FLASH_ERROR_PGP, - FLASH_ERROR_PGA, - FLASH_ERROR_WRP, - FLASH_ERROR_PROGRAM, - FLASH_ERROR_OPERATION, - FLASH_COMPLETE -}FLASH_Status; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants - * @{ - */ - -/** @defgroup Flash_Latency - * @{ - */ -#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */ -#define FLASH_Latency_1 ((uint8_t)0x0001) /*!< FLASH One Latency cycle */ -#define FLASH_Latency_2 ((uint8_t)0x0002) /*!< FLASH Two Latency cycles */ -#define FLASH_Latency_3 ((uint8_t)0x0003) /*!< FLASH Three Latency cycles */ -#define FLASH_Latency_4 ((uint8_t)0x0004) /*!< FLASH Four Latency cycles */ -#define FLASH_Latency_5 ((uint8_t)0x0005) /*!< FLASH Five Latency cycles */ -#define FLASH_Latency_6 ((uint8_t)0x0006) /*!< FLASH Six Latency cycles */ -#define FLASH_Latency_7 ((uint8_t)0x0007) /*!< FLASH Seven Latency cycles */ -#define FLASH_Latency_8 ((uint8_t)0x0008) /*!< FLASH Eight Latency cycles */ -#define FLASH_Latency_9 ((uint8_t)0x0009) /*!< FLASH Nine Latency cycles */ -#define FLASH_Latency_10 ((uint8_t)0x000A) /*!< FLASH Ten Latency cycles */ -#define FLASH_Latency_11 ((uint8_t)0x000B) /*!< FLASH Eleven Latency cycles */ -#define FLASH_Latency_12 ((uint8_t)0x000C) /*!< FLASH Twelve Latency cycles */ -#define FLASH_Latency_13 ((uint8_t)0x000D) /*!< FLASH Thirteen Latency cycles */ -#define FLASH_Latency_14 ((uint8_t)0x000E) /*!< FLASH Fourteen Latency cycles */ -#define FLASH_Latency_15 ((uint8_t)0x000F) /*!< FLASH Fifteen Latency cycles */ - - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \ - ((LATENCY) == FLASH_Latency_1) || \ - ((LATENCY) == FLASH_Latency_2) || \ - ((LATENCY) == FLASH_Latency_3) || \ - ((LATENCY) == FLASH_Latency_4) || \ - ((LATENCY) == FLASH_Latency_5) || \ - ((LATENCY) == FLASH_Latency_6) || \ - ((LATENCY) == FLASH_Latency_7) || \ - ((LATENCY) == FLASH_Latency_8) || \ - ((LATENCY) == FLASH_Latency_9) || \ - ((LATENCY) == FLASH_Latency_10) || \ - ((LATENCY) == FLASH_Latency_11) || \ - ((LATENCY) == FLASH_Latency_12) || \ - ((LATENCY) == FLASH_Latency_13) || \ - ((LATENCY) == FLASH_Latency_14) || \ - ((LATENCY) == FLASH_Latency_15)) -/** - * @} - */ - -/** @defgroup FLASH_Voltage_Range - * @{ - */ -#define VoltageRange_1 ((uint8_t)0x00) /*!< Device operating range: 1.8V to 2.1V */ -#define VoltageRange_2 ((uint8_t)0x01) /*!= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -#if defined (STM32F40_41xxx) || defined(STM32F412xG) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F40_41xxx || STM32F412xG */ - -#if defined (STM32F401xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F401xx */ - -#if defined (STM32F411xE) || defined (STM32F446xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F411xE || STM32F446xx */ - -#if defined (STM32F410xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F))) -#endif /* STM32F410xx */ - -#if defined(STM32F413_423xx) -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0817FFFF)) ||\ - (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7BDF))) -#endif /* STM32F413_423xx */ -/** - * @} - */ - -/** @defgroup Option_Bytes_Write_Protection - * @{ - */ -#define OB_WRP_Sector_0 ((uint32_t)0x00000001) /*!< Write protection of Sector0 */ -#define OB_WRP_Sector_1 ((uint32_t)0x00000002) /*!< Write protection of Sector1 */ -#define OB_WRP_Sector_2 ((uint32_t)0x00000004) /*!< Write protection of Sector2 */ -#define OB_WRP_Sector_3 ((uint32_t)0x00000008) /*!< Write protection of Sector3 */ -#define OB_WRP_Sector_4 ((uint32_t)0x00000010) /*!< Write protection of Sector4 */ -#define OB_WRP_Sector_5 ((uint32_t)0x00000020) /*!< Write protection of Sector5 */ -#define OB_WRP_Sector_6 ((uint32_t)0x00000040) /*!< Write protection of Sector6 */ -#define OB_WRP_Sector_7 ((uint32_t)0x00000080) /*!< Write protection of Sector7 */ -#define OB_WRP_Sector_8 ((uint32_t)0x00000100) /*!< Write protection of Sector8 */ -#define OB_WRP_Sector_9 ((uint32_t)0x00000200) /*!< Write protection of Sector9 */ -#define OB_WRP_Sector_10 ((uint32_t)0x00000400) /*!< Write protection of Sector10 */ -#define OB_WRP_Sector_11 ((uint32_t)0x00000800) /*!< Write protection of Sector11 */ -#define OB_WRP_Sector_12 ((uint32_t)0x00000001) /*!< Write protection of Sector12 */ -#define OB_WRP_Sector_13 ((uint32_t)0x00000002) /*!< Write protection of Sector13 */ -#define OB_WRP_Sector_14 ((uint32_t)0x00000004) /*!< Write protection of Sector14 */ -#define OB_WRP_Sector_15 ((uint32_t)0x00000008) /*!< Write protection of Sector15 */ -#define OB_WRP_Sector_16 ((uint32_t)0x00000010) /*!< Write protection of Sector16 */ -#define OB_WRP_Sector_17 ((uint32_t)0x00000020) /*!< Write protection of Sector17 */ -#define OB_WRP_Sector_18 ((uint32_t)0x00000040) /*!< Write protection of Sector18 */ -#define OB_WRP_Sector_19 ((uint32_t)0x00000080) /*!< Write protection of Sector19 */ -#define OB_WRP_Sector_20 ((uint32_t)0x00000100) /*!< Write protection of Sector20 */ -#define OB_WRP_Sector_21 ((uint32_t)0x00000200) /*!< Write protection of Sector21 */ -#define OB_WRP_Sector_22 ((uint32_t)0x00000400) /*!< Write protection of Sector22 */ -#define OB_WRP_Sector_23 ((uint32_t)0x00000800) /*!< Write protection of Sector23 */ -#define OB_WRP_Sector_All ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup Selection_Protection_Mode - * @{ - */ -#define OB_PcROP_Disable ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */ -#define OB_PcROP_Enable ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i */ -#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PcROP_Disable) || ((PCROP) == OB_PcROP_Enable)) -/** - * @} - */ - -/** @defgroup Option_Bytes_PC_ReadWrite_Protection - * @{ - */ -#define OB_PCROP_Sector_0 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector0 */ -#define OB_PCROP_Sector_1 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector1 */ -#define OB_PCROP_Sector_2 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector2 */ -#define OB_PCROP_Sector_3 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector3 */ -#define OB_PCROP_Sector_4 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector4 */ -#define OB_PCROP_Sector_5 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector5 */ -#define OB_PCROP_Sector_6 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector6 */ -#define OB_PCROP_Sector_7 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector7 */ -#define OB_PCROP_Sector_8 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector8 */ -#define OB_PCROP_Sector_9 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector9 */ -#define OB_PCROP_Sector_10 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector10 */ -#define OB_PCROP_Sector_11 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector11 */ -#define OB_PCROP_Sector_12 ((uint32_t)0x00000001) /*!< PC Read/Write protection of Sector12 */ -#define OB_PCROP_Sector_13 ((uint32_t)0x00000002) /*!< PC Read/Write protection of Sector13 */ -#define OB_PCROP_Sector_14 ((uint32_t)0x00000004) /*!< PC Read/Write protection of Sector14 */ -#define OB_PCROP_Sector_15 ((uint32_t)0x00000008) /*!< PC Read/Write protection of Sector15 */ -#define OB_PCROP_Sector_16 ((uint32_t)0x00000010) /*!< PC Read/Write protection of Sector16 */ -#define OB_PCROP_Sector_17 ((uint32_t)0x00000020) /*!< PC Read/Write protection of Sector17 */ -#define OB_PCROP_Sector_18 ((uint32_t)0x00000040) /*!< PC Read/Write protection of Sector18 */ -#define OB_PCROP_Sector_19 ((uint32_t)0x00000080) /*!< PC Read/Write protection of Sector19 */ -#define OB_PCROP_Sector_20 ((uint32_t)0x00000100) /*!< PC Read/Write protection of Sector20 */ -#define OB_PCROP_Sector_21 ((uint32_t)0x00000200) /*!< PC Read/Write protection of Sector21 */ -#define OB_PCROP_Sector_22 ((uint32_t)0x00000400) /*!< PC Read/Write protection of Sector22 */ -#define OB_PCROP_Sector_23 ((uint32_t)0x00000800) /*!< PC Read/Write protection of Sector23 */ -#define OB_PCROP_Sector_All ((uint32_t)0x00000FFF) /*!< PC Read/Write protection of all Sectors */ - -#define IS_OB_PCROP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_Read_Protection - * @{ - */ -#define OB_RDP_Level_0 ((uint8_t)0xAA) -#define OB_RDP_Level_1 ((uint8_t)0x55) -/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 - it's no more possible to go back to level 1 or 0 */ -#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\ - ((LEVEL) == OB_RDP_Level_1))/*||\ - ((LEVEL) == OB_RDP_Level_2))*/ -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) -/** - * @} - */ - -/** @defgroup FLASH_Option_Bytes_nRST_STOP - * @{ - */ -#define OB_STOP_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */ -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST)) -/** - * @} - */ - - -/** @defgroup FLASH_Option_Bytes_nRST_STDBY - * @{ - */ -#define OB_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */ -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST)) -/** - * @} - */ - -/** @defgroup FLASH_BOR_Reset_Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint8_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint8_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint8_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) -/** - * @} - */ - -/** @defgroup FLASH_Dual_Boot - * @{ - */ -#define OB_Dual_BootEnabled ((uint8_t)0x10) /*!< Dual Bank Boot Enable */ -#define OB_Dual_BootDisabled ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */ -#define IS_OB_BOOT(BOOT) (((BOOT) == OB_Dual_BootEnabled) || ((BOOT) == OB_Dual_BootDisabled)) -/** - * @} - */ - -/** @defgroup FLASH_Interrupts - * @{ - */ -#define FLASH_IT_EOP ((uint32_t)0x01000000) /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */ -#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000)) -/** - * @} - */ - -/** @defgroup FLASH_Flags - * @{ - */ -#define FLASH_FLAG_EOP ((uint32_t)0x00000001) /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR ((uint32_t)0x00000002) /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR ((uint32_t)0x00000010) /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR ((uint32_t)0x00000020) /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR ((uint32_t)0x00000040) /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_PGSERR ((uint32_t)0x00000080) /*!< FLASH Programming Sequence error flag */ -#define FLASH_FLAG_RDERR ((uint32_t)0x00000100) /*!< Read Protection error flag (PCROP) */ -#define FLASH_FLAG_BSY ((uint32_t)0x00010000) /*!< FLASH Busy flag */ -#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFE0C) == 0x00000000) && ((FLAG) != 0x00000000)) -#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \ - ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \ - ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \ - ((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_RDERR)) -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)0x00000100) -#define FLASH_PSIZE_WORD ((uint32_t)0x00000200) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)0x00000300) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF) -/** - * @} - */ - -/** @defgroup FLASH_Keys - * @{ - */ -#define RDP_KEY ((uint16_t)0x00A5) -#define FLASH_KEY1 ((uint32_t)0x45670123) -#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F) -/** - * @} - */ - -/** - * @brief ACR register byte 0 (Bits[7:0]) base address - */ -#define ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) -/** - * @brief OPTCR register byte 0 (Bits[7:0]) base address - */ -#define OPTCR_BYTE0_ADDRESS ((uint32_t)0x40023C14) -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) -/** - * @brief OPTCR register byte 2 (Bits[23:16]) base address - */ -#define OPTCR_BYTE2_ADDRESS ((uint32_t)0x40023C16) -/** - * @brief OPTCR register byte 3 (Bits[31:24]) base address - */ -#define OPTCR_BYTE3_ADDRESS ((uint32_t)0x40023C17) - -/** - * @brief OPTCR1 register byte 0 (Bits[7:0]) base address - */ -#define OPTCR1_BYTE2_ADDRESS ((uint32_t)0x40023C1A) - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* FLASH Interface configuration functions ************************************/ -void FLASH_SetLatency(uint32_t FLASH_Latency); -void FLASH_PrefetchBufferCmd(FunctionalState NewState); -void FLASH_InstructionCacheCmd(FunctionalState NewState); -void FLASH_DataCacheCmd(FunctionalState NewState); -void FLASH_InstructionCacheReset(void); -void FLASH_DataCacheReset(void); - -/* FLASH Memory Programming functions *****************************************/ -void FLASH_Unlock(void); -void FLASH_Lock(void); -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange); -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data); -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data); - -/* Option Bytes Programming functions *****************************************/ -void FLASH_OB_Unlock(void); -void FLASH_OB_Lock(void); -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState); -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP); -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState); -void FLASH_OB_RDPConfig(uint8_t OB_RDP); -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -void FLASH_OB_BORConfig(uint8_t OB_BOR); -void FLASH_OB_BootConfig(uint8_t OB_BOOT); -FLASH_Status FLASH_OB_Launch(void); -uint8_t FLASH_OB_GetUser(void); -uint16_t FLASH_OB_GetWRP(void); -uint16_t FLASH_OB_GetWRP1(void); -uint16_t FLASH_OB_GetPCROP(void); -uint16_t FLASH_OB_GetPCROP1(void); -FlagStatus FLASH_OB_GetRDP(void); -uint8_t FLASH_OB_GetBOR(void); - -/* Interrupts and flags management functions **********************************/ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); -void FLASH_ClearFlag(uint32_t FLASH_FLAG); -FLASH_Status FLASH_GetStatus(void); -FLASH_Status FLASH_WaitForLastOperation(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h deleted file mode 100644 index 562b5b180..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash_ramfunc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief Header file of FLASH RAMFUNC driver. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FLASH_RAMFUNC_H -#define __STM32F4xx_FLASH_RAMFUNC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FLASH RAMFUNC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC void - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc void - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC void __attribute__((section(".RamFunc"))) - -#endif -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState); -__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState); - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_FLASH_RAMFUNC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h deleted file mode 100644 index c66aab4ab..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h +++ /dev/null @@ -1,1143 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fmc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the FMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FMC_H -#define __STM32F4xx_FMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 1 and 15. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 1 and 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 15. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 15 in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ - - uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the databus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ - - uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FMC_Memory_Type */ - - uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ - - uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ - - uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ - - uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FMC_Wrap_Mode */ - - uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ - - uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ - - uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ - - uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ - - uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ - - uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ - - uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ - - - FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ - - FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ -}FMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 255.*/ - - uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0 and 255 */ - - uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0 and 255 */ - - uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - databus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0 and 255 */ -}FMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ - - uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ - - uint32_t FMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ - - uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ - - uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 255. */ - - uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0 and 255 */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ -}FMC_NANDInitTypeDef; - -/** - * @brief FMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 255. */ - - uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0 and 255 */ - - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */ - - FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */ -}FMC_PCCARDInitTypeDef; - -/** - * @brief Timing parameters for FMC SDRAM Banks - */ - -typedef struct -{ - uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and - an active or Refresh command in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to - issuing the Activate command in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock - cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command - and the delay between two consecutive Refresh commands in number of - memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command - in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command - in number of memory clock cycles. - This parameter can be a value between 1 and 16. */ - -}FMC_SDRAMTimingInitTypeDef; - -/** - * @brief Command parameters for FMC SDRAM Banks - */ - - -typedef struct -{ - uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device. - This parameter can be a value of @ref FMC_Command_Mode. */ - - uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to. - This parameter can be a value of @ref FMC_Command_Target. */ - - uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued - in auto refresh mode. - This parameter can be a value between 1 and 16. */ - - uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ - -}FMC_SDRAMCommandTypeDef; - -/** - * @brief FMC SDRAM Init structure definition - */ - -typedef struct -{ - uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used. - This parameter can be a value of @ref FMC_SDRAM_Bank */ - - uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_ColumnBits_Number. */ - - uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address.. - This parameter can be a value of @ref FMC_RowBits_Number. */ - - uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width. - This parameter can be a value of @ref FMC_SDMemory_Data_Width. */ - - uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address. - This parameter can be of @ref FMC_InternalBank_Number. */ - - uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. - This parameter can be a value of @ref FMC_CAS_Latency. */ - - uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode. - This parameter can be a value of @ref FMC_Write_Protection. */ - - uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable - the clock before changing frequency. - This parameter can be a value of @ref FMC_SDClock_Period. */ - - uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands - during the CAS latency and stores data in the Read FIFO. - This parameter can be a value of @ref FMC_Read_Burst. */ - - uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. - This parameter can be a value of @ref FMC_ReadPipe_Delay. */ - - FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/ - -}FMC_SDRAMInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FMC_Exported_Constants - * @{ - */ - -/** @defgroup FMC_NORSRAM_Bank - * @{ - */ -#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) - -#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \ - ((BANK) == FMC_Bank1_NORSRAM2) || \ - ((BANK) == FMC_Bank1_NORSRAM3) || \ - ((BANK) == FMC_Bank1_NORSRAM4)) -/** - * @} - */ - -/** @defgroup FMC_NAND_Bank - * @{ - */ -#define FMC_Bank2_NAND ((uint32_t)0x00000010) -#define FMC_Bank3_NAND ((uint32_t)0x00000100) - -#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND)) -/** - * @} - */ - -/** @defgroup FMC_PCCARD_Bank - * @{ - */ -#define FMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Bank - * @{ - */ -#define FMC_Bank1_SDRAM ((uint32_t)0x00000000) -#define FMC_Bank2_SDRAM ((uint32_t)0x00000001) - -#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM)) - -/** - * @} - */ - - -/** @defgroup FMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002) - -#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \ - ((MUX) == FMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Memory_Type - * @{ - */ - -#define FMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FMC_MemoryType_NOR ((uint32_t)0x00000008) - -#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \ - ((MEMORY) == FMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Data_Width - * @{ - */ - -#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \ - ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \ - ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b)) -/** - * @} - */ - -/** @defgroup FMC_Burst_Access_Mode - * @{ - */ - -#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100) - -#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \ - ((STATE) == FMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_AsynchronousWait - * @{ - */ -#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000) - -#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \ - ((STATE) == FMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal_Polarity - * @{ - */ -#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200) - -#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FMC_Wrap_Mode - * @{ - */ -#define FMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FMC_WrapMode_Enable ((uint32_t)0x00000400) - -#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \ - ((MODE) == FMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Timing - * @{ - */ -#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FMC_Write_Operation - * @{ - */ -#define FMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FMC_WriteOperation_Enable ((uint32_t)0x00001000) - -#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \ - ((OPERATION) == FMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal - * @{ - */ -#define FMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FMC_WaitSignal_Enable ((uint32_t)0x00002000) - -#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \ - ((SIGNAL) == FMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Extended_Mode - * @{ - */ -#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \ - ((MODE) == FMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Write_Burst - * @{ - */ - -#define FMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FMC_WriteBurst_Enable ((uint32_t)0x00080000) - -#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \ - ((BURST) == FMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FMC_Continous_Clock - * @{ - */ - -#define FMC_CClock_SyncOnly ((uint32_t)0x00000000) -#define FMC_CClock_SyncAsync ((uint32_t)0x00100000) - -#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \ - ((CCLOCK) == FMC_CClock_SyncAsync)) -/** - * @} - */ - -/** @defgroup FMC_Address_Setup_Time - * @{ - */ -#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Address_Hold_Time - * @{ - */ -#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Setup_Time - * @{ - */ -#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255)) -/** - * @} - */ - -/** @defgroup FMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15) -/** - * @} - */ - -/** @defgroup FMC_CLK_Division - * @{ - */ -#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15)) -/** - * @} - */ - -/** @defgroup FMC_Data_Latency - * @{ - */ -#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15) -/** - * @} - */ - -/** @defgroup FMC_Access_Mode - * @{ - */ -#define FMC_AccessMode_A ((uint32_t)0x00000000) -#define FMC_AccessMode_B ((uint32_t)0x10000000) -#define FMC_AccessMode_C ((uint32_t)0x20000000) -#define FMC_AccessMode_D ((uint32_t)0x30000000) - -#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \ - ((MODE) == FMC_AccessMode_B) || \ - ((MODE) == FMC_AccessMode_C) || \ - ((MODE) == FMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FMC_Wait_feature - * @{ - */ -#define FMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FMC_Waitfeature_Enable ((uint32_t)0x00000002) - -#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \ - ((FEATURE) == FMC_Waitfeature_Enable)) -/** - * @} - */ - -/** @defgroup FMC_NAND_Data_Width - * @{ - */ -#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010) - -#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \ - ((WIDTH) == FMC_NAND_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FMC_ECC - * @{ - */ -#define FMC_ECC_Disable ((uint32_t)0x00000000) -#define FMC_ECC_Enable ((uint32_t)0x00000040) - -#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \ - ((STATE) == FMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FMC_ECC_Page_Size - * @{ - */ -#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) - -#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FMC_TCLR_Setup_Time - * @{ - */ -#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_TAR_Setup_Time - * @{ - */ -#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Setup_Time - * @{ - */ -#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Wait_Setup_Time - * @{ - */ -#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_Hold_Setup_Time - * @{ - */ -#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** @defgroup FMC_HiZ_Setup_Time - * @{ - */ -#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255) -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FMC_ColumnBits_Number - * @{ - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \ - ((COLUMN) == FMC_ColumnBits_Number_9b) || \ - ((COLUMN) == FMC_ColumnBits_Number_10b) || \ - ((COLUMN) == FMC_ColumnBits_Number_11b)) - -/** - * @} - */ - -/** @defgroup FMC_RowBits_Number - * @{ - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \ - ((ROW) == FMC_RowBits_Number_12b) || \ - ((ROW) == FMC_RowBits_Number_13b)) - -/** - * @} - */ - -/** @defgroup FMC_SDMemory_Data_Width - * @{ - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \ - ((WIDTH) == FMC_SDMemory_Width_16b) || \ - ((WIDTH) == FMC_SDMemory_Width_32b)) - -/** - * @} - */ - -/** @defgroup FMC_InternalBank_Number - * @{ - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \ - ((NUMBER) == FMC_InternalBank_Number_4)) - -/** - * @} - */ - - -/** @defgroup FMC_CAS_Latency - * @{ - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \ - ((LATENCY) == FMC_CAS_Latency_2) || \ - ((LATENCY) == FMC_CAS_Latency_3)) - -/** - * @} - */ - -/** @defgroup FMC_Write_Protection - * @{ - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) - -#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \ - ((WRITE) == FMC_Write_Protection_Enable)) - -/** - * @} - */ - - -/** @defgroup FMC_SDClock_Period - * @{ - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) - -#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \ - ((PERIOD) == FMC_SDClock_Period_2) || \ - ((PERIOD) == FMC_SDClock_Period_3)) - -/** - * @} - */ - -/** @defgroup FMC_Read_Burst - * @{ - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) - -#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \ - ((RBURST) == FMC_Read_Burst_Enable)) - -/** - * @} - */ - -/** @defgroup FMC_ReadPipe_Delay - * @{ - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) - -#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \ - ((DELAY) == FMC_ReadPipe_Delay_1) || \ - ((DELAY) == FMC_ReadPipe_Delay_2)) - -/** - * @} - */ - -/** @defgroup FMC_LoadToActive_Delay - * @{ - */ -#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_ExitSelfRefresh_Delay - * @{ - */ -#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_SelfRefresh_Time - * @{ - */ -#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RowCycle_Delay - * @{ - */ -#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_Write_Recovery_Time - * @{ - */ -#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RP_Delay - * @{ - */ -#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) -/** - * @} - */ - -/** @defgroup FMC_RCD_Delay - * @{ - */ -#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16)) - -/** - * @} - */ - -/** @defgroup FMC_Command_Mode - * @{ - */ -#define FMC_Command_Mode_normal ((uint32_t)0x00000000) -#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001) -#define FMC_Command_Mode_PALL ((uint32_t)0x00000002) -#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003) -#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004) -#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005) -#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006) - -#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \ - ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \ - ((COMMAND) == FMC_Command_Mode_PALL) || \ - ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \ - ((COMMAND) == FMC_Command_Mode_LoadMode) || \ - ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \ - ((COMMAND) == FMC_Command_Mode_PowerDown)) - -/** - * @} - */ - -/** @defgroup FMC_Command_Target - * @{ - */ -#define FMC_Command_Target_bank2 ((uint32_t)0x00000008) -#define FMC_Command_Target_bank1 ((uint32_t)0x00000010) -#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018) - -#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \ - ((TARGET) == FMC_Command_Target_bank2) || \ - ((TARGET) == FMC_Command_Target_bank1_2)) - -/** - * @} - */ - -/** @defgroup FMC_AutoRefresh_Number - * @{ - */ -#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16)) - -/** - * @} - */ - -/** @defgroup FMC_ModeRegister_Definition - * @{ - */ -#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191) - -/** - * @} - */ - - -/** @defgroup FMC_Mode_Status - * @{ - */ -#define FMC_NormalMode_Status ((uint32_t)0x00000000) -#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0 -#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1 - -#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \ - ((STATUS) == FMC_SelfRefreshMode_Status) || \ - ((STATUS) == FMC_PowerDownMode_Status)) - - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_Interrupt_sources - * @{ - */ -#define FMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FMC_IT_Level ((uint32_t)0x00000010) -#define FMC_IT_FallingEdge ((uint32_t)0x00000020) -#define FMC_IT_Refresh ((uint32_t)0x00004000) - -#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \ - ((IT) == FMC_IT_Level) || \ - ((IT) == FMC_IT_FallingEdge) || \ - ((IT) == FMC_IT_Refresh)) - -#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND) || \ - ((BANK) == FMC_Bank4_PCCARD) || \ - ((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM)) -/** - * @} - */ - -/** @defgroup FMC_Flags - * @{ - */ -#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FMC_FLAG_Level ((uint32_t)0x00000002) -#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define FMC_FLAG_Refresh FMC_SDSR_RE -#define FMC_FLAG_Busy FMC_SDSR_BUSY - -#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \ - ((FLAG) == FMC_FLAG_Level) || \ - ((FLAG) == FMC_FLAG_FallingEdge) || \ - ((FLAG) == FMC_FLAG_FEMPT) || \ - ((FLAG) == FMC_FLAG_Refresh) || \ - ((FLAG) == FMC_SDSR_BUSY)) - -#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \ - ((BANK) == FMC_Bank3_NAND) || \ - ((BANK) == FMC_Bank4_PCCARD) || \ - ((BANK) == FMC_Bank1_SDRAM) || \ - ((BANK) == FMC_Bank2_SDRAM) || \ - ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM))) - -#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) - - -/** - * @} - */ - -/** @defgroup FMC_Refresh_count - * @{ - */ -#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FMC_NORSRAMDeInit(uint32_t FMC_Bank); -void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); -void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct); -void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FMC_NANDDeInit(uint32_t FMC_Bank); -void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); -void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct); -void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState); -void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState); -uint32_t FMC_GetECC(uint32_t FMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FMC_PCCARDDeInit(void); -void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); -void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct); -void FMC_PCCARDCmd(FunctionalState NewState); - -/* SDRAM Controller functions ************************************************/ -void FMC_SDRAMDeInit(uint32_t FMC_Bank); -void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); -void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct); -void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct); -uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank); -void FMC_SetRefreshCount(uint32_t FMC_Count); -void FMC_SetAutoRefresh_Number(uint32_t FMC_Number); -void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState); -FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG); -void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG); -ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT); -void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h deleted file mode 100644 index bf9aefad6..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the FSMC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_FSMC_H -#define __STM32F4xx_FSMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup FSMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief Timing parameters For NOR/SRAM Banks - */ -typedef struct -{ - uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between 0 and 0xF. - @note This parameter is not used with synchronous NOR Flash memories.*/ - - uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between 0 and 0xFF. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ - - uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between 0 and 0xF. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles. - This parameter can be a value between 1 and 0xF. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ - - uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between 0 and 0xF in NOR Flash memories - with synchronous burst mode enable */ - - uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ -}FSMC_NORSRAMTimingInitTypeDef; - -/** - * @brief FSMC NOR/SRAM Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ - - uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ - - uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory bank. - This parameter can be a value of @ref FSMC_Memory_Type */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_Data_Width */ - - uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ - - uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ - - uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ - - uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash - memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode */ - - uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ - - uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ - - uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ - - uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ - - uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/ - - FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/ -}FSMC_NORSRAMInitTypeDef; - -/** - * @brief Timing parameters For FSMC NAND and PCCARD Banks - */ -typedef struct -{ - uint32_t FSMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between 0 and 0xFF.*/ - - uint32_t FSMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between 0x00 and 0xFF */ - - uint32_t FSMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - data bus is kept in HiZ after the start of a NAND Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between 0x00 and 0xFF */ -}FSMC_NAND_PCCARDTimingInitTypeDef; - -/** - * @brief FSMC NAND Init structure definition - */ -typedef struct -{ - uint32_t FSMC_Bank; /*!< Specifies the NAND memory bank that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ - - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_Data_Width */ - - uint32_t FSMC_ECC; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ - - uint32_t FSMC_ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ -}FSMC_NANDInitTypeDef; - -/** - * @brief FSMC PCCARD Init structure definition - */ - -typedef struct -{ - uint32_t FSMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank. - This parameter can be any value of @ref FSMC_Wait_feature */ - - uint32_t FSMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between 0 and 0xFF. */ - - uint32_t FSMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between 0x0 and 0xFF */ - - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */ - - FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */ -}FSMC_PCCARDInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FSMC_Exported_Constants - * @{ - */ - -/** @defgroup FSMC_NORSRAM_Bank - * @{ - */ -#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) -#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002) -#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004) -#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006) -/** - * @} - */ - -/** @defgroup FSMC_NAND_Bank - * @{ - */ -#define FSMC_Bank2_NAND ((uint32_t)0x00000010) -#define FSMC_Bank3_NAND ((uint32_t)0x00000100) -/** - * @} - */ - -/** @defgroup FSMC_PCCARD_Bank - * @{ - */ -#define FSMC_Bank4_PCCARD ((uint32_t)0x00001000) -/** - * @} - */ - -#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \ - ((BANK) == FSMC_Bank1_NORSRAM2) || \ - ((BANK) == FSMC_Bank1_NORSRAM3) || \ - ((BANK) == FSMC_Bank1_NORSRAM4)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND)) - -#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \ - ((BANK) == FSMC_Bank3_NAND) || \ - ((BANK) == FSMC_Bank4_PCCARD)) - -/** @defgroup FSMC_NOR_SRAM_Controller - * @{ - */ - -/** @defgroup FSMC_Data_Address_Bus_Multiplexing - * @{ - */ - -#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) -#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) -#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \ - ((MUX) == FSMC_DataAddressMux_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Memory_Type - * @{ - */ - -#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) -#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) -#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) -#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \ - ((MEMORY) == FSMC_MemoryType_PSRAM)|| \ - ((MEMORY) == FSMC_MemoryType_NOR)) -/** - * @} - */ - -/** @defgroup FSMC_Data_Width - * @{ - */ - -#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) -#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) -#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \ - ((WIDTH) == FSMC_MemoryDataWidth_16b)) -/** - * @} - */ - -/** @defgroup FSMC_Burst_Access_Mode - * @{ - */ - -#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) -#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) -#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \ - ((STATE) == FSMC_BurstAccessMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_AsynchronousWait - * @{ - */ -#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) -#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) -#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \ - ((STATE) == FSMC_AsynchronousWait_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal_Polarity - * @{ - */ -#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) -#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) -#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \ - ((POLARITY) == FSMC_WaitSignalPolarity_High)) -/** - * @} - */ - -/** @defgroup FSMC_Wrap_Mode - * @{ - */ -#define FSMC_WrapMode_Disable ((uint32_t)0x00000000) -#define FSMC_WrapMode_Enable ((uint32_t)0x00000400) -#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \ - ((MODE) == FSMC_WrapMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Timing - * @{ - */ -#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) -#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \ - ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Operation - * @{ - */ -#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) -#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) -#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \ - ((OPERATION) == FSMC_WriteOperation_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Signal - * @{ - */ -#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) -#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) -#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \ - ((SIGNAL) == FSMC_WaitSignal_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Extended_Mode - * @{ - */ -#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) -#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) - -#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \ - ((MODE) == FSMC_ExtendedMode_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Write_Burst - * @{ - */ - -#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) -#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) -#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \ - ((BURST) == FSMC_WriteBurst_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_Address_Setup_Time - * @{ - */ -#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Address_Hold_Time - * @{ - */ -#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Setup_Time - * @{ - */ -#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF)) -/** - * @} - */ - -/** @defgroup FSMC_Bus_Turn_around_Duration - * @{ - */ -#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_CLK_Division - * @{ - */ -#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Data_Latency - * @{ - */ -#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF) -/** - * @} - */ - -/** @defgroup FSMC_Access_Mode - * @{ - */ -#define FSMC_AccessMode_A ((uint32_t)0x00000000) -#define FSMC_AccessMode_B ((uint32_t)0x10000000) -#define FSMC_AccessMode_C ((uint32_t)0x20000000) -#define FSMC_AccessMode_D ((uint32_t)0x30000000) -#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \ - ((MODE) == FSMC_AccessMode_B) || \ - ((MODE) == FSMC_AccessMode_C) || \ - ((MODE) == FSMC_AccessMode_D)) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FSMC_NAND_PCCARD_Controller - * @{ - */ - -/** @defgroup FSMC_Wait_feature - * @{ - */ -#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) -#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \ - ((FEATURE) == FSMC_Waitfeature_Enable)) -/** - * @} - */ - - -/** @defgroup FSMC_ECC - * @{ - */ -#define FSMC_ECC_Disable ((uint32_t)0x00000000) -#define FSMC_ECC_Enable ((uint32_t)0x00000040) -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \ - ((STATE) == FSMC_ECC_Enable)) -/** - * @} - */ - -/** @defgroup FSMC_ECC_Page_Size - * @{ - */ -#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) -#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) -#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) -#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) -#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) -#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_512Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \ - ((SIZE) == FSMC_ECCPageSize_8192Bytes)) -/** - * @} - */ - -/** @defgroup FSMC_TCLR_Setup_Time - * @{ - */ -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_TAR_Setup_Time - * @{ - */ -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Setup_Time - * @{ - */ -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Wait_Setup_Time - * @{ - */ -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Hold_Setup_Time - * @{ - */ -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_HiZ_Setup_Time - * @{ - */ -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF) -/** - * @} - */ - -/** @defgroup FSMC_Interrupt_sources - * @{ - */ -#define FSMC_IT_RisingEdge ((uint32_t)0x00000008) -#define FSMC_IT_Level ((uint32_t)0x00000010) -#define FSMC_IT_FallingEdge ((uint32_t)0x00000020) -#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \ - ((IT) == FSMC_IT_Level) || \ - ((IT) == FSMC_IT_FallingEdge)) -/** - * @} - */ - -/** @defgroup FSMC_Flags - * @{ - */ -#define FSMC_FLAG_RisingEdge ((uint32_t)0x00000001) -#define FSMC_FLAG_Level ((uint32_t)0x00000002) -#define FSMC_FLAG_FallingEdge ((uint32_t)0x00000004) -#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) -#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \ - ((FLAG) == FSMC_FLAG_Level) || \ - ((FLAG) == FSMC_FLAG_FallingEdge) || \ - ((FLAG) == FSMC_FLAG_FEMPT)) - -#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* NOR/SRAM Controller functions **********************************************/ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); - -/* NAND Controller functions **************************************************/ -void FSMC_NANDDeInit(uint32_t FSMC_Bank); -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); -uint32_t FSMC_GetECC(uint32_t FSMC_Bank); - -/* PCCARD Controller functions ************************************************/ -void FSMC_PCCARDDeInit(void); -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct); -void FSMC_PCCARDCmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState); -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT); -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_FSMC_H */ -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h deleted file mode 100644 index 4c7195540..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h +++ /dev/null @@ -1,592 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the GPIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_GPIO_H -#define __STM32F4xx_GPIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ - ((PERIPH) == GPIOB) || \ - ((PERIPH) == GPIOC) || \ - ((PERIPH) == GPIOD) || \ - ((PERIPH) == GPIOE) || \ - ((PERIPH) == GPIOF) || \ - ((PERIPH) == GPIOG) || \ - ((PERIPH) == GPIOH) || \ - ((PERIPH) == GPIOI) || \ - ((PERIPH) == GPIOJ) || \ - ((PERIPH) == GPIOK)) - -/** - * @brief GPIO Configuration Mode enumeration - */ -typedef enum -{ - GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ - GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ - GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ - GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */ -}GPIOMode_TypeDef; -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \ - ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN)) - -/** - * @brief GPIO Output type enumeration - */ -typedef enum -{ - GPIO_OType_PP = 0x00, - GPIO_OType_OD = 0x01 -}GPIOOType_TypeDef; -#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD)) - - -/** - * @brief GPIO Output Maximum frequency enumeration - */ -typedef enum -{ - GPIO_Low_Speed = 0x00, /*!< Low speed */ - GPIO_Medium_Speed = 0x01, /*!< Medium speed */ - GPIO_Fast_Speed = 0x02, /*!< Fast speed */ - GPIO_High_Speed = 0x03 /*!< High speed */ -}GPIOSpeed_TypeDef; - -/* Add legacy definition */ -#define GPIO_Speed_2MHz GPIO_Low_Speed -#define GPIO_Speed_25MHz GPIO_Medium_Speed -#define GPIO_Speed_50MHz GPIO_Fast_Speed -#define GPIO_Speed_100MHz GPIO_High_Speed - -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || \ - ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed)) - -/** - * @brief GPIO Configuration PullUp PullDown enumeration - */ -typedef enum -{ - GPIO_PuPd_NOPULL = 0x00, - GPIO_PuPd_UP = 0x01, - GPIO_PuPd_DOWN = 0x02 -}GPIOPuPd_TypeDef; -#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \ - ((PUPD) == GPIO_PuPd_DOWN)) - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - Bit_RESET = 0, - Bit_SET -}BitAction; -#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET)) - - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIOMode_TypeDef */ - - GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIOSpeed_TypeDef */ - - GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIOOType_TypeDef */ - - GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIOPuPd_TypeDef */ -}GPIO_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants - * @{ - */ - -/** @defgroup GPIO_pins_define - * @{ - */ -#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ -#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ -#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ -#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ -#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ -#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ -#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ -#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ -#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ -#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ -#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ -#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ -#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ -#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ -#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ -#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ -#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) -#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ - ((PIN) == GPIO_Pin_1) || \ - ((PIN) == GPIO_Pin_2) || \ - ((PIN) == GPIO_Pin_3) || \ - ((PIN) == GPIO_Pin_4) || \ - ((PIN) == GPIO_Pin_5) || \ - ((PIN) == GPIO_Pin_6) || \ - ((PIN) == GPIO_Pin_7) || \ - ((PIN) == GPIO_Pin_8) || \ - ((PIN) == GPIO_Pin_9) || \ - ((PIN) == GPIO_Pin_10) || \ - ((PIN) == GPIO_Pin_11) || \ - ((PIN) == GPIO_Pin_12) || \ - ((PIN) == GPIO_Pin_13) || \ - ((PIN) == GPIO_Pin_14) || \ - ((PIN) == GPIO_Pin_15)) -/** - * @} - */ - - -/** @defgroup GPIO_Pin_sources - * @{ - */ -#define GPIO_PinSource0 ((uint8_t)0x00) -#define GPIO_PinSource1 ((uint8_t)0x01) -#define GPIO_PinSource2 ((uint8_t)0x02) -#define GPIO_PinSource3 ((uint8_t)0x03) -#define GPIO_PinSource4 ((uint8_t)0x04) -#define GPIO_PinSource5 ((uint8_t)0x05) -#define GPIO_PinSource6 ((uint8_t)0x06) -#define GPIO_PinSource7 ((uint8_t)0x07) -#define GPIO_PinSource8 ((uint8_t)0x08) -#define GPIO_PinSource9 ((uint8_t)0x09) -#define GPIO_PinSource10 ((uint8_t)0x0A) -#define GPIO_PinSource11 ((uint8_t)0x0B) -#define GPIO_PinSource12 ((uint8_t)0x0C) -#define GPIO_PinSource13 ((uint8_t)0x0D) -#define GPIO_PinSource14 ((uint8_t)0x0E) -#define GPIO_PinSource15 ((uint8_t)0x0F) - -#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ - ((PINSOURCE) == GPIO_PinSource1) || \ - ((PINSOURCE) == GPIO_PinSource2) || \ - ((PINSOURCE) == GPIO_PinSource3) || \ - ((PINSOURCE) == GPIO_PinSource4) || \ - ((PINSOURCE) == GPIO_PinSource5) || \ - ((PINSOURCE) == GPIO_PinSource6) || \ - ((PINSOURCE) == GPIO_PinSource7) || \ - ((PINSOURCE) == GPIO_PinSource8) || \ - ((PINSOURCE) == GPIO_PinSource9) || \ - ((PINSOURCE) == GPIO_PinSource10) || \ - ((PINSOURCE) == GPIO_PinSource11) || \ - ((PINSOURCE) == GPIO_PinSource12) || \ - ((PINSOURCE) == GPIO_PinSource13) || \ - ((PINSOURCE) == GPIO_PinSource14) || \ - ((PINSOURCE) == GPIO_PinSource15)) -/** - * @} - */ - -/** @defgroup GPIO_Alternat_function_selection_define - * @{ - */ -/** - * @brief AF 0 selection - */ -#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */ -#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -#if defined(STM32F446xx) -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#endif /* STM32F446xx */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#if defined(STM32F410xx) || defined(STM32F413_423xx) -#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */ -#endif /* STM32F410xx || STM32F413_423xx */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */ -#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */ -#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */ -#if defined(STM32F446xx) -#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */ -#endif /* STM32F446xx */ -#if defined(STM32F413_423xx) -#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */ -#endif /* STM32F413_423xx */ -/** - * @brief AF 4 selection - */ -#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#if defined(STM32F446xx) -#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */ -#endif /* STM32F446xx */ -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */ -#endif /* STM32F410xx || STM32F446xx */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */ -#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */ -#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */ -#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */ -#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */ -#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */ -#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */ -#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */ -#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */ -#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F412xG || STM32F413_423xx */ -#if defined(STM32F413_423xx) -#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */ -#endif /* STM32F413_423xx */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */ -#if defined(STM32F413_423xx) -#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */ -#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */ -#endif /* STM32F413_423xx */ - -/** - * @brief AF 7 selection Legacy - */ -#define GPIO_AF_I2S3ext GPIO_AF7_SPI3 - -/** - * @brief AF 8 selection - */ -#define GPIO_AF_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */ -#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */ -#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */ -#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */ -#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */ -#endif /* STM32F412xG || STM32F413_423xx */ -#if defined(STM32F446xx) -#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */ -#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */ -#endif /* STM32F446xx */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */ -#define GPIO_AF_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */ -#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ -#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ -#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */ -#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */ -#if defined(STM32F446xx) -#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */ -#endif /* STM32F446xx */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */ -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */ -#if defined(STM32F446xx) -#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */ -#endif /* STM32F446xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */ -#define GPIO_AF10_DFSDM1 ((uint8_t)0xA) /* DFSDM Alternate Function mapping */ -#endif /* STM32F412xG || STM32F413_423xx */ -#if defined(STM32F413_423xx) -#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */ -#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */ -#endif /* STM32F413_423xx */ -/** - * @brief AF 11 selection - */ -#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */ -#if defined(STM32F413_423xx) -#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */ -#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */ -#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */ -#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */ -#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */ -#endif /* STM32F413_423xx */ - -/** - * @brief AF 12 selection - */ -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */ -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ -#if defined(STM32F469_479xx) -#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */ -#endif /* STM32F469_479xx */ -/** - * @brief AF 14 selection - */ -#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ -#if defined(STM32F413_423xx) -#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */ -#endif /* STM32F413_423xx */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#if defined(STM32F40_41xxx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC)) -#endif /* STM32F40_41xxx */ - -#if defined(STM32F401xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4)) -#endif /* STM32F401xx */ - -#if defined(STM32F411xE) -#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14)) -#endif /* STM32F411xE */ - -#if defined(STM32F410xx) -#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15)) -#endif /* STM32F410xx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \ - ((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \ - ((AF) == GPIO_AF_TIM1) || ((AF) == GPIO_AF_TIM2) || \ - ((AF) == GPIO_AF_TIM3) || ((AF) == GPIO_AF_TIM4) || \ - ((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_TIM8) || \ - ((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \ - ((AF) == GPIO_AF_I2C3) || ((AF) == GPIO_AF_SPI1) || \ - ((AF) == GPIO_AF_SPI2) || ((AF) == GPIO_AF_TIM13) || \ - ((AF) == GPIO_AF_SPI3) || ((AF) == GPIO_AF_TIM14) || \ - ((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \ - ((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_UART4) || \ - ((AF) == GPIO_AF_UART5) || ((AF) == GPIO_AF_USART6) || \ - ((AF) == GPIO_AF_CAN1) || ((AF) == GPIO_AF_CAN2) || \ - ((AF) == GPIO_AF_OTG_FS) || ((AF) == GPIO_AF_OTG_HS) || \ - ((AF) == GPIO_AF_ETH) || ((AF) == GPIO_AF_OTG_HS_FS) || \ - ((AF) == GPIO_AF_SDIO) || ((AF) == GPIO_AF_DCMI) || \ - ((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4) || \ - ((AF) == GPIO_AF_SPI5) || ((AF) == GPIO_AF_SPI6) || \ - ((AF) == GPIO_AF_UART7) || ((AF) == GPIO_AF_UART8) || \ - ((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \ - ((AF) == GPIO_AF_LTDC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined(STM32F412xG) -#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14)) -#endif /* STM32F412xG */ - -#if defined(STM32F413_423xx) -#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 13)) -#endif /* STM32F413_423xx */ - -#if defined(STM32F446xx) -#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14)) -#endif /* STM32F446xx */ - -#if defined(STM32F469_479xx) -#define IS_GPIO_AF(AF) ((AF) < 16) -#endif /* STM32F469_479xx */ - -/** - * @} - */ - -/** @defgroup GPIO_Legacy - * @{ - */ - -#define GPIO_Mode_AIN GPIO_Mode_AN - -#define GPIO_AF_OTG1_FS GPIO_AF_OTG_FS -#define GPIO_AF_OTG2_HS GPIO_AF_OTG_HS -#define GPIO_AF_OTG2_FS GPIO_AF_OTG_HS_FS - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the GPIO configuration to the default reset state ****/ -void GPIO_DeInit(GPIO_TypeDef* GPIOx); - -/* Initialization and Configuration functions *********************************/ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Read and Write functions **********************************************/ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); - -/* GPIO Alternate functions configuration function ****************************/ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_GPIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h deleted file mode 100644 index 28b2d6ba6..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h +++ /dev/null @@ -1,257 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the HASH - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HASH_H -#define __STM32F4xx_HASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HASH Init structure definition - */ -typedef struct -{ - uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter - can be a value of @ref HASH_Algo_Selection */ - uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value - of @ref HASH_processor_Algorithm_Mode */ - uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or - bit string. This parameter can be a value of - @ref HASH_Data_Type */ - uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter - can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */ -}HASH_InitTypeDef; - -/** - * @brief HASH message digest result structure definition - */ -typedef struct -{ - uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256, - 7x 32bit wors for SHA-224, - 5x 32bit words for SHA-1 or - 4x 32bit words for MD5 */ -} HASH_MsgDigest; - -/** - * @brief HASH context swapping structure definition - */ -typedef struct -{ - uint32_t HASH_IMR; - uint32_t HASH_STR; - uint32_t HASH_CR; - uint32_t HASH_CSR[54]; -}HASH_Context; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection - * @{ - */ -#define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */ -#define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ -#define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ -#define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ - -#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \ - ((ALGOSELECTION) == HASH_AlgoSelection_MD5)) -/** - * @} - */ - -/** @defgroup HASH_processor_Algorithm_Mode - * @{ - */ -#define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */ -#define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ - -#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \ - ((ALGOMODE) == HASH_AlgoMode_HMAC)) -/** - * @} - */ - -/** @defgroup HASH_Data_Type - * @{ - */ -#define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */ -#define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ -#define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ -#define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ - -#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \ - ((DATATYPE) == HASH_DataType_16b)|| \ - ((DATATYPE) == HASH_DataType_8b) || \ - ((DATATYPE) == HASH_DataType_1b)) -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode - * @{ - */ -#define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */ -#define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */ - -#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \ - ((KEYTYPE) == HASH_HMACKeyType_LongKey)) -/** - * @} - */ - -/** @defgroup Number_of_valid_bits_in_last_word_of_the_message - * @{ - */ -#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F) - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition - * @{ - */ -#define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */ -#define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */ - -#define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI)) - -/** - * @} - */ - -/** @defgroup HASH_flags_definition - * @{ - */ -#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */ -#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */ -#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */ - -#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS) || \ - ((FLAG) == HASH_FLAG_DMAS) || \ - ((FLAG) == HASH_FLAG_BUSY) || \ - ((FLAG) == HASH_FLAG_DINNE)) - -#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \ - ((FLAG) == HASH_FLAG_DCIS)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the HASH configuration to the default reset state ****/ -void HASH_DeInit(void); - -/* HASH Configuration function ************************************************/ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct); -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct); -void HASH_Reset(void); - -/* HASH Message Digest generation functions ***********************************/ -void HASH_DataIn(uint32_t Data); -uint8_t HASH_GetInFIFOWordsNbr(void); -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber); -void HASH_StartDigest(void); -void HASH_AutoStartDigest(FunctionalState NewState); -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest); - -/* HASH Context swapping functions ********************************************/ -void HASH_SaveContext(HASH_Context* HASH_ContextSave); -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore); - -/* HASH DMA interface function ************************************************/ -void HASH_DMACmd(FunctionalState NewState); - -/* HASH Interrupts and flags management functions *****************************/ -void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState); -FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG); -void HASH_ClearFlag(uint32_t HASH_FLAG); -ITStatus HASH_GetITStatus(uint32_t HASH_IT); -void HASH_ClearITPendingBit(uint32_t HASH_IT); - -/* High Level SHA1 functions **************************************************/ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]); -ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[20]); - -/* High Level MD5 functions ***************************************************/ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]); -ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen, - uint8_t *Input, uint32_t Ilen, - uint8_t Output[16]); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_HASH_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h deleted file mode 100644 index ade420d7f..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h +++ /dev/null @@ -1,709 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_i2c.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the I2C firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_I2C_H -#define __STM32F4xx_I2C_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief I2C Init structure definition - */ - -typedef struct -{ - uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz */ - - uint16_t I2C_Mode; /*!< Specifies the I2C mode. - This parameter can be a value of @ref I2C_mode */ - - uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ - - uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement. - This parameter can be a value of @ref I2C_acknowledgement */ - - uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. - This parameter can be a value of @ref I2C_acknowledged_address */ -}I2C_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - - -/** @defgroup I2C_Exported_Constants - * @{ - */ -#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ - ((PERIPH) == I2C2) || \ - ((PERIPH) == I2C3)) -/** @defgroup I2C_Digital_Filter - * @{ - */ - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) -/** - * @} - */ - - -/** @defgroup I2C_mode - * @{ - */ - -#define I2C_Mode_I2C ((uint16_t)0x0000) -#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) -#define I2C_Mode_SMBusHost ((uint16_t)0x000A) -#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ - ((MODE) == I2C_Mode_SMBusDevice) || \ - ((MODE) == I2C_Mode_SMBusHost)) -/** - * @} - */ - -/** @defgroup I2C_duty_cycle_in_fast_mode - * @{ - */ - -#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */ -#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */ -#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \ - ((CYCLE) == I2C_DutyCycle_2)) -/** - * @} - */ - -/** @defgroup I2C_acknowledgement - * @{ - */ - -#define I2C_Ack_Enable ((uint16_t)0x0400) -#define I2C_Ack_Disable ((uint16_t)0x0000) -#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \ - ((STATE) == I2C_Ack_Disable)) -/** - * @} - */ - -/** @defgroup I2C_transfer_direction - * @{ - */ - -#define I2C_Direction_Transmitter ((uint8_t)0x00) -#define I2C_Direction_Receiver ((uint8_t)0x01) -#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ - ((DIRECTION) == I2C_Direction_Receiver)) -/** - * @} - */ - -/** @defgroup I2C_acknowledged_address - * @{ - */ - -#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) -#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) -#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ - ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) -/** - * @} - */ - -/** @defgroup I2C_registers - * @{ - */ - -#define I2C_Register_CR1 ((uint8_t)0x00) -#define I2C_Register_CR2 ((uint8_t)0x04) -#define I2C_Register_OAR1 ((uint8_t)0x08) -#define I2C_Register_OAR2 ((uint8_t)0x0C) -#define I2C_Register_DR ((uint8_t)0x10) -#define I2C_Register_SR1 ((uint8_t)0x14) -#define I2C_Register_SR2 ((uint8_t)0x18) -#define I2C_Register_CCR ((uint8_t)0x1C) -#define I2C_Register_TRISE ((uint8_t)0x20) -#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ - ((REGISTER) == I2C_Register_CR2) || \ - ((REGISTER) == I2C_Register_OAR1) || \ - ((REGISTER) == I2C_Register_OAR2) || \ - ((REGISTER) == I2C_Register_DR) || \ - ((REGISTER) == I2C_Register_SR1) || \ - ((REGISTER) == I2C_Register_SR2) || \ - ((REGISTER) == I2C_Register_CCR) || \ - ((REGISTER) == I2C_Register_TRISE)) -/** - * @} - */ - -/** @defgroup I2C_NACK_position - * @{ - */ - -#define I2C_NACKPosition_Next ((uint16_t)0x0800) -#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \ - ((POSITION) == I2C_NACKPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_SMBus_alert_pin_level - * @{ - */ - -#define I2C_SMBusAlert_Low ((uint16_t)0x2000) -#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) -#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \ - ((ALERT) == I2C_SMBusAlert_High)) -/** - * @} - */ - -/** @defgroup I2C_PEC_position - * @{ - */ - -#define I2C_PECPosition_Next ((uint16_t)0x0800) -#define I2C_PECPosition_Current ((uint16_t)0xF7FF) -#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \ - ((POSITION) == I2C_PECPosition_Current)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_BUF ((uint16_t)0x0400) -#define I2C_IT_EVT ((uint16_t)0x0200) -#define I2C_IT_ERR ((uint16_t)0x0100) -#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00)) -/** - * @} - */ - -/** @defgroup I2C_interrupts_definition - * @{ - */ - -#define I2C_IT_SMBALERT ((uint32_t)0x01008000) -#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) -#define I2C_IT_PECERR ((uint32_t)0x01001000) -#define I2C_IT_OVR ((uint32_t)0x01000800) -#define I2C_IT_AF ((uint32_t)0x01000400) -#define I2C_IT_ARLO ((uint32_t)0x01000200) -#define I2C_IT_BERR ((uint32_t)0x01000100) -#define I2C_IT_TXE ((uint32_t)0x06000080) -#define I2C_IT_RXNE ((uint32_t)0x06000040) -#define I2C_IT_STOPF ((uint32_t)0x02000010) -#define I2C_IT_ADD10 ((uint32_t)0x02000008) -#define I2C_IT_BTF ((uint32_t)0x02000004) -#define I2C_IT_ADDR ((uint32_t)0x02000002) -#define I2C_IT_SB ((uint32_t)0x02000001) - -#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00)) - -#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \ - ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \ - ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \ - ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \ - ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \ - ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \ - ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB)) -/** - * @} - */ - -/** @defgroup I2C_flags_definition - * @{ - */ - -/** - * @brief SR2 register flags - */ - -#define I2C_FLAG_DUALF ((uint32_t)0x00800000) -#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) -#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) -#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) -#define I2C_FLAG_TRA ((uint32_t)0x00040000) -#define I2C_FLAG_BUSY ((uint32_t)0x00020000) -#define I2C_FLAG_MSL ((uint32_t)0x00010000) - -/** - * @brief SR1 register flags - */ - -#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) -#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) -#define I2C_FLAG_PECERR ((uint32_t)0x10001000) -#define I2C_FLAG_OVR ((uint32_t)0x10000800) -#define I2C_FLAG_AF ((uint32_t)0x10000400) -#define I2C_FLAG_ARLO ((uint32_t)0x10000200) -#define I2C_FLAG_BERR ((uint32_t)0x10000100) -#define I2C_FLAG_TXE ((uint32_t)0x10000080) -#define I2C_FLAG_RXNE ((uint32_t)0x10000040) -#define I2C_FLAG_STOPF ((uint32_t)0x10000010) -#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) -#define I2C_FLAG_BTF ((uint32_t)0x10000004) -#define I2C_FLAG_ADDR ((uint32_t)0x10000002) -#define I2C_FLAG_SB ((uint32_t)0x10000001) - -#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \ - ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \ - ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \ - ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \ - ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \ - ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \ - ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \ - ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \ - ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \ - ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \ - ((FLAG) == I2C_FLAG_SB)) -/** - * @} - */ - -/** @defgroup I2C_Events - * @{ - */ - -/** - =============================================================================== - I2C Master Events (Events grouped in order of communication) - =============================================================================== - */ - -/** - * @brief Communication start - * - * After sending the START condition (I2C_GenerateSTART() function) the master - * has to wait for this event. It means that the Start condition has been correctly - * released on the I2C bus (the bus is free, no other devices is communicating). - * - */ -/* --EV5 */ -#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ - -/** - * @brief Address Acknowledge - * - * After checking on EV5 (start condition correctly released on the bus), the - * master sends the address of the slave(s) with which it will communicate - * (I2C_Send7bitAddress() function, it also determines the direction of the communication: - * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges - * his address. If an acknowledge is sent on the bus, one of the following events will - * be set: - * - * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - * event is set. - * - * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - * is set - * - * 3) In case of 10-Bit addressing mode, the master (just after generating the START - * and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() - * function). Then master should wait on EV9. It means that the 10-bit addressing - * header has been correctly sent on the bus. Then master should send the second part of - * the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master - * should wait for event EV6. - * - */ - -/* --EV6 */ -#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ -#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ -/* --EV9 */ -#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ - -/** - * @brief Communication events - * - * If a communication is established (START condition generated and slave address - * acknowledged) then the master has to check on one of the following events for - * communication procedures: - * - * 1) Master Receiver mode: The master has to wait on the event EV7 then to read - * the data received from the slave (I2C_ReceiveData() function). - * - * 2) Master Transmitter mode: The master has to send data (I2C_SendData() - * function) then to wait on event EV8 or EV8_2. - * These two events are similar: - * - EV8 means that the data has been written in the data register and is - * being shifted out. - * - EV8_2 means that the data has been physically shifted out and output - * on the bus. - * In most cases, using EV8 is sufficient for the application. - * Using EV8_2 leads to a slower communication but ensure more reliable test. - * EV8_2 is also more suitable than EV8 for testing on the last data transmission - * (before Stop condition generation). - * - * @note In case the user software does not guarantee that this event EV7 is - * managed before the current byte end of transfer, then user may check on EV7 - * and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Master RECEIVER mode -----------------------------*/ -/* --EV7 */ -#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ - -/* Master TRANSMITTER mode --------------------------*/ -/* --EV8 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ -/* --EV8_2 */ -#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ - - -/** - =============================================================================== - I2C Slave Events (Events grouped in order of communication) - =============================================================================== - */ - - -/** - * @brief Communication start events - * - * Wait on one of these events at the start of the communication. It means that - * the I2C peripheral detected a Start condition on the bus (generated by master - * device) followed by the peripheral address. The peripheral generates an ACK - * condition on the bus (if the acknowledge feature is enabled through function - * I2C_AcknowledgeConfig()) and the events listed above are set : - * - * 1) In normal case (only one address managed by the slave), when the address - * sent by the master matches the own address of the peripheral (configured by - * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set - * (where XXX could be TRANSMITTER or RECEIVER). - * - * 2) In case the address sent by the master matches the second address of the - * peripheral (configured by the function I2C_OwnAddress2Config() and enabled - * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED - * (where XXX could be TRANSMITTER or RECEIVER) are set. - * - * 3) In case the address sent by the master is General Call (address 0x00) and - * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) - * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. - * - */ - -/* --EV1 (all the events below are variants of EV1) */ -/* 1) Case of One Single Address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ - -/* 2) Case of Dual address managed by the slave */ -#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ -#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ - -/* 3) Case of General Call enabled for the slave */ -#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ - -/** - * @brief Communication events - * - * Wait on one of these events when EV1 has already been checked and: - * - * - Slave RECEIVER mode: - * - EV2: When the application is expecting a data byte to be received. - * - EV4: When the application is expecting the end of the communication: master - * sends a stop condition and data transmission is stopped. - * - * - Slave Transmitter mode: - * - EV3: When a byte has been transmitted by the slave and the application is expecting - * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and - * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be - * used when the user software doesn't guarantee the EV3 is managed before the - * current byte end of transfer. - * - EV3_2: When the master sends a NACK in order to tell slave that data transmission - * shall end (before sending the STOP condition). In this case slave has to stop sending - * data bytes and expect a Stop condition on the bus. - * - * @note In case the user software does not guarantee that the event EV2 is - * managed before the current byte end of transfer, then user may check on EV2 - * and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)). - * In this case the communication may be slower. - * - */ - -/* Slave RECEIVER mode --------------------------*/ -/* --EV2 */ -#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ -/* --EV4 */ -#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ - -/* Slave TRANSMITTER mode -----------------------*/ -/* --EV3 */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ -#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ -/* --EV3_2 */ -#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ - -/* - =============================================================================== - End of Events Description - =============================================================================== - */ - -#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \ - ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \ - ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \ - ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \ - ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \ - ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \ - ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE)) -/** - * @} - */ - -/** @defgroup I2C_own_address1 - * @{ - */ - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF) -/** - * @} - */ - -/** @defgroup I2C_clock_speed - * @{ - */ - -#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the I2C configuration to the default reset state *****/ -void I2C_DeInit(I2C_TypeDef* I2Cx); - -/* Initialization and Configuration functions *********************************/ -void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter); -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); - -/* PEC management functions ***************************************************/ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); - -/* DMA transfers management functions *****************************************/ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); - -/* Interrupts, events and flags management functions **************************/ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); - -/* - =============================================================================== - I2C State Monitoring Functions - =============================================================================== - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - 1. Basic state monitoring (Using I2C_CheckEvent() function) - ----------------------------------------------------------- - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - - When to use - - This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - - It is also suitable for users who need to define their own events. - - - Limitations - - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - Note - For error management, it is advised to use the following functions: - - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - - I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - 2. Advanced state monitoring (Using the function I2C_GetLastEvent()) - -------------------------------------------------------------------- - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - - When to use - - This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - - The returned value could be compared to events already defined in - this file or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - - At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - - Limitations - - User may need to define his own events. - - Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - 3. Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - ----------------------------------------------------------------------- - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - - When to use - - This function could be used for specific applications or in debug - phase. - - It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - - Limitations: - - When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - - Function may need to be called twice or more in order to monitor - one single event. - */ - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); - - -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_I2C_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h deleted file mode 100644 index b8c75fead..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the IWDG - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_IWDG_H -#define __STM32F4xx_IWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup IWDG_Exported_Constants - * @{ - */ - -/** @defgroup IWDG_WriteAccess - * @{ - */ -#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) -#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) -#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ - ((ACCESS) == IWDG_WriteAccess_Disable)) -/** - * @} - */ - -/** @defgroup IWDG_prescaler - * @{ - */ -#define IWDG_Prescaler_4 ((uint8_t)0x00) -#define IWDG_Prescaler_8 ((uint8_t)0x01) -#define IWDG_Prescaler_16 ((uint8_t)0x02) -#define IWDG_Prescaler_32 ((uint8_t)0x03) -#define IWDG_Prescaler_64 ((uint8_t)0x04) -#define IWDG_Prescaler_128 ((uint8_t)0x05) -#define IWDG_Prescaler_256 ((uint8_t)0x06) -#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ - ((PRESCALER) == IWDG_Prescaler_8) || \ - ((PRESCALER) == IWDG_Prescaler_16) || \ - ((PRESCALER) == IWDG_Prescaler_32) || \ - ((PRESCALER) == IWDG_Prescaler_64) || \ - ((PRESCALER) == IWDG_Prescaler_128)|| \ - ((PRESCALER) == IWDG_Prescaler_256)) -/** - * @} - */ - -/** @defgroup IWDG_Flag - * @{ - */ -#define IWDG_FLAG_PVU ((uint16_t)0x0001) -#define IWDG_FLAG_RVU ((uint16_t)0x0002) -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) -#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Prescaler and Counter configuration functions ******************************/ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); -void IWDG_SetReload(uint16_t Reload); -void IWDG_ReloadCounter(void); - -/* IWDG activation function ***************************************************/ -void IWDG_Enable(void); - -/* Flag management function ***************************************************/ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_IWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h deleted file mode 100644 index 260cd3f0f..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h +++ /dev/null @@ -1,503 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ltdc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the LTDC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LTDC_H -#define __STM32F4xx_LTDC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup LTDC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief LTDC Init structure definition - */ - -typedef struct -{ - uint32_t LTDC_HSPolarity; /*!< configures the horizontal synchronization polarity. - This parameter can be one value of @ref LTDC_HSPolarity */ - - uint32_t LTDC_VSPolarity; /*!< configures the vertical synchronization polarity. - This parameter can be one value of @ref LTDC_VSPolarity */ - - uint32_t LTDC_DEPolarity; /*!< configures the data enable polarity. This parameter can - be one of value of @ref LTDC_DEPolarity */ - - uint32_t LTDC_PCPolarity; /*!< configures the pixel clock polarity. This parameter can - be one of value of @ref LTDC_PCPolarity */ - - uint32_t LTDC_HorizontalSync; /*!< configures the number of Horizontal synchronization - width. This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization - height. This parameter must range from 0x000 to 0x7FF. */ - - uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must range from LTDC_HorizontalSync to 0xFFF. */ - - uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch height. - This parameter must range from LTDC_VerticalSync to 0x7FF. */ - - uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter - must range from LTDC_AccumulatedHBP to 0xFFF. */ - - uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active height. This parameter - must range from LTDC_AccumulatedVBP to 0x7FF. */ - - uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter - must range from LTDC_AccumulatedActiveW to 0xFFF. */ - - uint32_t LTDC_TotalHeigh; /*!< configures the total height. This parameter - must range from LTDC_AccumulatedActiveH to 0x7FF. */ - - uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BackgroundGreenValue; /*!< configures the background green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BackgroundBlueValue; /*!< configures the background blue value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_InitTypeDef; - -/** - * @brief LTDC Layer structure definition - */ - -typedef struct -{ - uint32_t LTDC_HorizontalStart; /*!< Configures the Window Horizontal Start Position. - This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_HorizontalStop; /*!< Configures the Window Horizontal Stop Position. - This parameter must range from 0x0000 to 0xFFFF. */ - - uint32_t LTDC_VerticalStart; /*!< Configures the Window vertical Start Position. - This parameter must range from 0x000 to 0xFFF. */ - - uint32_t LTDC_VerticalStop; /*!< Configures the Window vaertical Stop Position. - This parameter must range from 0x0000 to 0xFFFF. */ - - uint32_t LTDC_PixelFormat; /*!< Specifies the pixel format. This parameter can be - one of value of @ref LTDC_Pixelformat */ - - uint32_t LTDC_ConstantAlpha; /*!< Specifies the constant alpha used for blending. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorBlue; /*!< Configures the default blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorGreen; /*!< Configures the default green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorRed; /*!< Configures the default red value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_DefaultColorAlpha; /*!< Configures the default alpha value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BlendingFactor_1; /*!< Select the blending factor 1. This parameter - can be one of value of @ref LTDC_BlendingFactor1 */ - - uint32_t LTDC_BlendingFactor_2; /*!< Select the blending factor 2. This parameter - can be one of value of @ref LTDC_BlendingFactor2 */ - - uint32_t LTDC_CFBStartAdress; /*!< Configures the color frame buffer address */ - - uint32_t LTDC_CFBLineLength; /*!< Configures the color frame buffer line length. - This parameter must range from 0x0000 to 0x1FFF. */ - - uint32_t LTDC_CFBPitch; /*!< Configures the color frame buffer pitch in bytes. - This parameter must range from 0x0000 to 0x1FFF. */ - - uint32_t LTDC_CFBLineNumber; /*!< Specifies the number of line in frame buffer. - This parameter must range from 0x000 to 0x7FF. */ -} LTDC_Layer_InitTypeDef; - -/** - * @brief LTDC Position structure definition - */ -typedef struct -{ - uint32_t LTDC_POSX; /*!< Current X Position */ - uint32_t LTDC_POSY; /*!< Current Y Position */ -} LTDC_PosTypeDef; - -/** - * @brief LTDC RGB structure definition - */ -typedef struct -{ - uint32_t LTDC_BlueWidth; /*!< Blue width */ - uint32_t LTDC_GreenWidth; /*!< Green width */ - uint32_t LTDC_RedWidth; /*!< Red width */ -} LTDC_RGBTypeDef; - -/** - * @brief LTDC Color Keying structure definition - */ -typedef struct -{ - uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_ColorKeyGreen; /*!< Configures the color key green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_ColorKeyRed; /*!< Configures the color key red value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_ColorKeying_InitTypeDef; - -/** - * @brief LTDC CLUT structure definition - */ -typedef struct -{ - uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_BlueValue; /*!< Configures the blue value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_GreenValue; /*!< Configures the green value. - This parameter must range from 0x00 to 0xFF. */ - - uint32_t LTDC_RedValue; /*!< Configures the red value. - This parameter must range from 0x00 to 0xFF. */ -} LTDC_CLUT_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LTDC_Exported_Constants - * @{ - */ - -/** @defgroup LTDC_SYNC - * @{ - */ - -#define LTDC_HorizontalSYNC ((uint32_t)0x00000FFF) -#define LTDC_VerticalSYNC ((uint32_t)0x000007FF) - -#define IS_LTDC_HSYNC(HSYNC) ((HSYNC) <= LTDC_HorizontalSYNC) -#define IS_LTDC_VSYNC(VSYNC) ((VSYNC) <= LTDC_VerticalSYNC) -#define IS_LTDC_AHBP(AHBP) ((AHBP) <= LTDC_HorizontalSYNC) -#define IS_LTDC_AVBP(AVBP) ((AVBP) <= LTDC_VerticalSYNC) -#define IS_LTDC_AAW(AAW) ((AAW) <= LTDC_HorizontalSYNC) -#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC) -#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC) -#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC) -/** - * @} - */ - -/** @defgroup LTDC_HSPolarity - * @{ - */ -#define LTDC_HSPolarity_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */ -#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ - -#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \ - ((HSPOL) == LTDC_HSPolarity_AH)) -/** - * @} - */ - -/** @defgroup LTDC_VSPolarity - * @{ - */ -#define LTDC_VSPolarity_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */ -#define LTDC_VSPolarity_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ - -#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \ - ((VSPOL) == LTDC_VSPolarity_AH)) -/** - * @} - */ - -/** @defgroup LTDC_DEPolarity - * @{ - */ -#define LTDC_DEPolarity_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */ -#define LTDC_DEPolarity_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ - -#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \ - ((DEPOL) == LTDC_DEPolarity_AH)) -/** - * @} - */ - -/** @defgroup LTDC_PCPolarity - * @{ - */ -#define LTDC_PCPolarity_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */ -#define LTDC_PCPolarity_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ - -#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \ - ((PCPOL) == LTDC_PCPolarity_IIPC)) -/** - * @} - */ - -/** @defgroup LTDC_Reload - * @{ - */ -#define LTDC_IMReload LTDC_SRCR_IMR /*!< Immediately Reload. */ -#define LTDC_VBReload LTDC_SRCR_VBR /*!< Vertical Blanking Reload. */ - -#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \ - ((RELOAD) == LTDC_VBReload)) -/** - * @} - */ - -/** @defgroup LTDC_Back_Color - * @{ - */ -#define LTDC_Back_Color ((uint32_t)0x000000FF) - -#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color) -#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color) -#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color) -/** - * @} - */ - -/** @defgroup LTDC_Position - * @{ - */ -#define LTDC_POS_CY LTDC_CPSR_CYPOS -#define LTDC_POS_CX LTDC_CPSR_CXPOS - -#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY)) -/** - * @} - */ - -/** @defgroup LTDC_LIPosition - * @{ - */ -#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF) -/** - * @} - */ - -/** @defgroup LTDC_CurrentStatus - * @{ - */ -#define LTDC_CD_VDES LTDC_CDSR_VDES -#define LTDC_CD_HDES LTDC_CDSR_HDES -#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS -#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS - -#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \ - ((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC)) -/** - * @} - */ - -/** @defgroup LTDC_Interrupts - * @{ - */ -#define LTDC_IT_LI LTDC_IER_LIE -#define LTDC_IT_FU LTDC_IER_FUIE -#define LTDC_IT_TERR LTDC_IER_TERRIE -#define LTDC_IT_RR LTDC_IER_RRIE - -#define IS_LTDC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF0) == 0x00) && ((IT) != 0x00)) - -/** - * @} - */ - -/** @defgroup LTDC_Flag - * @{ - */ -#define LTDC_FLAG_LI LTDC_ISR_LIF -#define LTDC_FLAG_FU LTDC_ISR_FUIF -#define LTDC_FLAG_TERR LTDC_ISR_TERRIF -#define LTDC_FLAG_RR LTDC_ISR_RRIF - -#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \ - ((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR)) -/** - * @} - */ - -/** @defgroup LTDC_Pixelformat - * @{ - */ -#define LTDC_Pixelformat_ARGB8888 ((uint32_t)0x00000000) -#define LTDC_Pixelformat_RGB888 ((uint32_t)0x00000001) -#define LTDC_Pixelformat_RGB565 ((uint32_t)0x00000002) -#define LTDC_Pixelformat_ARGB1555 ((uint32_t)0x00000003) -#define LTDC_Pixelformat_ARGB4444 ((uint32_t)0x00000004) -#define LTDC_Pixelformat_L8 ((uint32_t)0x00000005) -#define LTDC_Pixelformat_AL44 ((uint32_t)0x00000006) -#define LTDC_Pixelformat_AL88 ((uint32_t)0x00000007) - -#define IS_LTDC_Pixelformat(Pixelformat) (((Pixelformat) == LTDC_Pixelformat_ARGB8888) || ((Pixelformat) == LTDC_Pixelformat_RGB888) || \ - ((Pixelformat) == LTDC_Pixelformat_RGB565) || ((Pixelformat) == LTDC_Pixelformat_ARGB1555) || \ - ((Pixelformat) == LTDC_Pixelformat_ARGB4444) || ((Pixelformat) == LTDC_Pixelformat_L8) || \ - ((Pixelformat) == LTDC_Pixelformat_AL44) || ((Pixelformat) == LTDC_Pixelformat_AL88)) - -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor1 - * @{ - */ -#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400) -#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600) - -#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA)) -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor2 - * @{ - */ -#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005) -#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007) - -#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA)) -/** - * @} - */ - -/** @defgroup LTDC_LAYER_Config - * @{ - */ -#define LTDC_STOPPosition ((uint32_t)0x0000FFFF) -#define LTDC_STARTPosition ((uint32_t)0x00000FFF) - -#define LTDC_DefaultColorConfig ((uint32_t)0x000000FF) -#define LTDC_ColorFrameBuffer ((uint32_t)0x00001FFF) -#define LTDC_LineNumber ((uint32_t)0x000007FF) - -#define IS_LTDC_HCONFIGST(HCONFIGST) ((HCONFIGST) <= LTDC_STARTPosition) -#define IS_LTDC_HCONFIGSP(HCONFIGSP) ((HCONFIGSP) <= LTDC_STOPPosition) -#define IS_LTDC_VCONFIGST(VCONFIGST) ((VCONFIGST) <= LTDC_STARTPosition) -#define IS_LTDC_VCONFIGSP(VCONFIGSP) ((VCONFIGSP) <= LTDC_STOPPosition) - -#define IS_LTDC_DEFAULTCOLOR(DEFAULTCOLOR) ((DEFAULTCOLOR) <= LTDC_DefaultColorConfig) - -#define IS_LTDC_CFBP(CFBP) ((CFBP) <= LTDC_ColorFrameBuffer) -#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer) - -#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber) -/** - * @} - */ - -/** @defgroup LTDC_colorkeying_Config - * @{ - */ -#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF) - -#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig) -/** - * @} - */ - -/** @defgroup LTDC_CLUT_Config - * @{ - */ - -#define LTDC_CLUTWR ((uint32_t)0x000000FF) - -#define IS_LTDC_CLUTWR(CLUTWR) ((CLUTWR) <= LTDC_CLUTWR) - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions ------------------------------------------------------- */ -/* Function used to set the LTDC configuration to the default reset state *****/ -void LTDC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct); -void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct); -void LTDC_Cmd(FunctionalState NewState); -void LTDC_DitherCmd(FunctionalState NewState); -LTDC_RGBTypeDef LTDC_GetRGBWidth(void); -void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct); -void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig); -void LTDC_ReloadConfig(uint32_t LTDC_Reload); -void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct); -void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct); -void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); -LTDC_PosTypeDef LTDC_GetPosStatus(void); -void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct); -FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD); -void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState); -void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct); -void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState); -void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); -void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct); -void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY); -void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha); -void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address); -void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height); -void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat); - -/* Interrupts and flags management functions **********************************/ -void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState); -FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG); -void LTDC_ClearFlag(uint32_t LTDC_FLAG); -ITStatus LTDC_GetITStatus(uint32_t LTDC_IT); -void LTDC_ClearITPendingBit(uint32_t LTDC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_LTDC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h deleted file mode 100644 index 8e46f7089..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the PWR firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_PWR_H -#define __STM32F4xx_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level - * @{ - */ -#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 - -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ - ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ - ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ - ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) -/** - * @} - */ - - -/** @defgroup PWR_Regulator_state_in_STOP_mode - * @{ - */ -#define PWR_MainRegulator_ON ((uint32_t)0x00000000) -#define PWR_LowPowerRegulator_ON PWR_CR_LPDS - -/* --- PWR_Legacy ---*/ -#define PWR_Regulator_ON PWR_MainRegulator_ON -#define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON - -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_ON)) - -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_UnderDrive_mode - * @{ - */ -#define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS -#define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS)) - -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \ - ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON)) - -/** - * @} - */ -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** @defgroup PWR_Wake_Up_Pin - * @{ - */ -#define PWR_WakeUp_Pin1 ((uint32_t)0x00) -#define PWR_WakeUp_Pin2 ((uint32_t)0x01) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define PWR_WakeUp_Pin3 ((uint32_t)0x02) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F446xx) -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \ - ((PIN) == PWR_WakeUp_Pin2)) -#else /* STM32F410xx || STM32F412xG */ -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \ - ((PIN) == PWR_WakeUp_Pin3)) -#endif /* STM32F446xx */ -/** - * @} - */ -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/** @defgroup PWR_STOP_mode_entry - * @{ - */ -#define PWR_STOPEntry_WFI ((uint8_t)0x01) -#define PWR_STOPEntry_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale - * @{ - */ -#define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000) -#define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000) -#define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \ - ((VOLTAGE) == PWR_Regulator_Voltage_Scale3)) -/** - * @} - */ - -/** @defgroup PWR_Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_BRR PWR_CSR_BRR -#define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY -#define PWR_FLAG_ODRDY PWR_CSR_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY - -/* --- FLAG Legacy ---*/ -#define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY - -#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ - ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \ - ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY)) - - -#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ - ((FLAG) == PWR_FLAG_UDRDY)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the PWR configuration to the default reset state ******/ -void PWR_DeInit(void); - -/* Backup Domain Access function **********************************************/ -void PWR_BackupAccessCmd(FunctionalState NewState); - -/* PVD configuration functions ************************************************/ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); -void PWR_PVDCmd(FunctionalState NewState); - -/* WakeUp pins configuration functions ****************************************/ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -void PWR_WakeUpPinCmd(FunctionalState NewState); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx) -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState); -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ -/* Main and Backup Regulators configuration functions *************************/ -void PWR_BackupRegulatorCmd(FunctionalState NewState); -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage); -void PWR_OverDriveCmd(FunctionalState NewState); -void PWR_OverDriveSWCmd(FunctionalState NewState); -void PWR_UnderDriveCmd(FunctionalState NewState); - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) -void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState); -void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState); -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */ - -#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) -void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState); -void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState); -#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */ - -/* FLASH Power Down configuration functions ***********************************/ -void PWR_FlashPowerDownCmd(FunctionalState NewState); - -/* Low Power modes configuration functions ************************************/ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); -void PWR_EnterSTANDBYMode(void); - -/* Flags management functions *************************************************/ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); -void PWR_ClearFlag(uint32_t PWR_FLAG); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_PWR_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h deleted file mode 100644 index c3d4cad3c..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h +++ /dev/null @@ -1,1066 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the RCC firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RCC_H -#define __STM32F4xx_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency expressed in Hz */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency expressed in Hz */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency expressed in Hz */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency expressed in Hz */ -}RCC_ClocksTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Constants - * @{ - */ - -/** @defgroup RCC_HSE_configuration - * @{ - */ -#define RCC_HSE_OFF ((uint8_t)0x00) -#define RCC_HSE_ON ((uint8_t)0x01) -#define RCC_HSE_Bypass ((uint8_t)0x05) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Dual_Mode_Selection - * @{ - */ -#define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00) -#define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01) -#define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || \ - ((MODE) == RCC_LSE_HIGHDRIVE_MODE)) -/** - * @} - */ - -/** @defgroup RCC_PLLSAIDivR_Factor - * @{ - */ -#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000) -#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000) -#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000) -#define RCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000) -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div4) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div8) ||\ - ((VALUE) == RCC_PLLSAIDivR_Div16)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source - * @{ - */ -#define RCC_PLLSource_HSI ((uint32_t)0x00000000) -#define RCC_PLLSource_HSE ((uint32_t)0x00400000) -#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \ - ((SOURCE) == RCC_PLLSource_HSE)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63) -#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15)) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) -#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#if defined(STM32F446xx) -#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63) -#elif defined(STM32F412xG) || defined(STM32F413_423xx) -#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#else -#endif /* STM32F446xx */ -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#if defined(STM32F446xx) || defined(STM32F469_479xx) -#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8)) -#endif /* STM32F446xx || STM32F469_479xx */ -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#if defined(STM32F413_423xx) -#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) -#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) -#endif /* STM32F413_423xx */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source - * @{ - */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002) -#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLRCLK)) -/* Add legacy definition */ -#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK -#endif /* STM32F446xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) -#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) -#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) -#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) -#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ - ((SOURCE) == RCC_SYSCLKSource_HSE) || \ - ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source - * @{ - */ -#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) -#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) -#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) -#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) -#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) -#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) -#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) -#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) -#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ - ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ - ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ - ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ - ((HCLK) == RCC_SYSCLK_Div512)) -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source - * @{ - */ -#define RCC_HCLK_Div1 ((uint32_t)0x00000000) -#define RCC_HCLK_Div2 ((uint32_t)0x00001000) -#define RCC_HCLK_Div4 ((uint32_t)0x00001400) -#define RCC_HCLK_Div8 ((uint32_t)0x00001800) -#define RCC_HCLK_Div16 ((uint32_t)0x00001C00) -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ - ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ - ((PCLK) == RCC_HCLK_Div16)) -/** - * @} - */ - -/** @defgroup RCC_Interrupt_Source - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01) -#define RCC_IT_LSERDY ((uint8_t)0x02) -#define RCC_IT_HSIRDY ((uint8_t)0x04) -#define RCC_IT_HSERDY ((uint8_t)0x08) -#define RCC_IT_PLLRDY ((uint8_t)0x10) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40) -#define RCC_IT_CSS ((uint8_t)0x80) - -#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ - ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY)) -#define IS_RCC_CLEAR_IT(IT)((IT) != 0x00) - -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration - * @{ - */ -#define RCC_LSE_OFF ((uint8_t)0x00) -#define RCC_LSE_ON ((uint8_t)0x01) -#define RCC_LSE_Bypass ((uint8_t)0x04) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_Bypass)) -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source - * @{ - */ -#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) -#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) -#define RCC_RTCCLKSource_HSE_Div2 ((uint32_t)0x00020300) -#define RCC_RTCCLKSource_HSE_Div3 ((uint32_t)0x00030300) -#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)0x00040300) -#define RCC_RTCCLKSource_HSE_Div5 ((uint32_t)0x00050300) -#define RCC_RTCCLKSource_HSE_Div6 ((uint32_t)0x00060300) -#define RCC_RTCCLKSource_HSE_Div7 ((uint32_t)0x00070300) -#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)0x00080300) -#define RCC_RTCCLKSource_HSE_Div9 ((uint32_t)0x00090300) -#define RCC_RTCCLKSource_HSE_Div10 ((uint32_t)0x000A0300) -#define RCC_RTCCLKSource_HSE_Div11 ((uint32_t)0x000B0300) -#define RCC_RTCCLKSource_HSE_Div12 ((uint32_t)0x000C0300) -#define RCC_RTCCLKSource_HSE_Div13 ((uint32_t)0x000D0300) -#define RCC_RTCCLKSource_HSE_Div14 ((uint32_t)0x000E0300) -#define RCC_RTCCLKSource_HSE_Div15 ((uint32_t)0x000F0300) -#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)0x00100300) -#define RCC_RTCCLKSource_HSE_Div17 ((uint32_t)0x00110300) -#define RCC_RTCCLKSource_HSE_Div18 ((uint32_t)0x00120300) -#define RCC_RTCCLKSource_HSE_Div19 ((uint32_t)0x00130300) -#define RCC_RTCCLKSource_HSE_Div20 ((uint32_t)0x00140300) -#define RCC_RTCCLKSource_HSE_Div21 ((uint32_t)0x00150300) -#define RCC_RTCCLKSource_HSE_Div22 ((uint32_t)0x00160300) -#define RCC_RTCCLKSource_HSE_Div23 ((uint32_t)0x00170300) -#define RCC_RTCCLKSource_HSE_Div24 ((uint32_t)0x00180300) -#define RCC_RTCCLKSource_HSE_Div25 ((uint32_t)0x00190300) -#define RCC_RTCCLKSource_HSE_Div26 ((uint32_t)0x001A0300) -#define RCC_RTCCLKSource_HSE_Div27 ((uint32_t)0x001B0300) -#define RCC_RTCCLKSource_HSE_Div28 ((uint32_t)0x001C0300) -#define RCC_RTCCLKSource_HSE_Div29 ((uint32_t)0x001D0300) -#define RCC_RTCCLKSource_HSE_Div30 ((uint32_t)0x001E0300) -#define RCC_RTCCLKSource_HSE_Div31 ((uint32_t)0x001F0300) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ - ((SOURCE) == RCC_RTCCLKSource_LSI) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \ - ((SOURCE) == RCC_RTCCLKSource_HSE_Div31)) -/** - * @} - */ - -#if defined(STM32F410xx) || defined(STM32F413_423xx) -/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000) -#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0) -#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1) -#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1) - -#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) -/* Legacy Defines */ -#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE - -#if defined(STM32F410xx) -/** - * @} - */ - -/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source - * @{ - */ -#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000) -#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0) -#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1) -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \ - ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC)) -/** - * @} - */ -#endif /* STM32F413_423xx */ -#endif /* STM32F410xx || STM32F413_423xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00) -#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0) -#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1) -#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \ - ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE)) -/** - * @} - */ - -/** @defgroup RCC_I2S_APBBus - * @{ - */ -#define RCC_I2SBus_APB1 ((uint8_t)0x00) -#define RCC_I2SBus_APB2 ((uint8_t)0x01) -#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2)) -/** - * @} - */ -#if defined(STM32F446xx) -/** @defgroup RCC_SAI_Clock_Source - * @{ - */ -#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00) -#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0) -#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1) -#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1) - -#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \ - ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE)) -/** - * @} - */ - -/** @defgroup RCC_SAI_Instance - * @{ - */ -#define RCC_SAIInstance_SAI1 ((uint8_t)0x00) -#define RCC_SAIInstance_SAI2 ((uint8_t)0x01) -#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2)) -/** - * @} - */ -#endif /* STM32F446xx */ -#if defined(STM32F413_423xx) - -/** @defgroup RCC_SAI_BlockA_Clock_Source - * @{ - */ -#define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000) -#define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0) -#define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1) -#define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1) - -#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \ - ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockB_Clock_Source - * @{ - */ -#define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000) -#define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0) -#define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1) -#define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1) - -#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \ - ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE)) -/** - * @} - */ -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) -/** @defgroup RCC_I2S_Clock_Source - * @{ - */ -#define RCC_I2S2CLKSource_PLLI2S ((uint8_t)0x00) -#define RCC_I2S2CLKSource_Ext ((uint8_t)0x01) - -#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockA_Clock_Source - * @{ - */ -#define RCC_SAIACLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIACLKSource_PLLI2S ((uint32_t)0x00100000) -#define RCC_SAIACLKSource_Ext ((uint32_t)0x00200000) - -#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIACLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIACLKSource_Ext)) -/** - * @} - */ - -/** @defgroup RCC_SAI_BlockB_Clock_Source - * @{ - */ -#define RCC_SAIBCLKSource_PLLSAI ((uint32_t)0x00000000) -#define RCC_SAIBCLKSource_PLLI2S ((uint32_t)0x00400000) -#define RCC_SAIBCLKSource_Ext ((uint32_t)0x00800000) - -#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S) ||\ - ((SOURCE) == RCC_SAIBCLKSource_PLLSAI) ||\ - ((SOURCE) == RCC_SAIBCLKSource_Ext)) -/** - * @} - */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ - -/** @defgroup RCC_TIM_PRescaler_Selection - * @{ - */ -#define RCC_TIMPrescDesactivated ((uint8_t)0x00) -#define RCC_TIMPrescActivated ((uint8_t)0x01) - -#define IS_RCC_TIMCLK_PRESCALER(VALUE) (((VALUE) == RCC_TIMPrescDesactivated) || ((VALUE) == RCC_TIMPrescActivated)) -/** - * @} - */ - -#if defined(STM32F469_479xx) -/** @defgroup RCC_DSI_Clock_Source_Selection - * @{ - */ -#define RCC_DSICLKSource_PHY ((uint8_t)0x00) -#define RCC_DSICLKSource_PLLR ((uint8_t)0x01) -#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \ - ((CLKSOURCE) == RCC_DSICLKSource_PLLR)) -/** - * @} - */ -#endif /* STM32F469_479xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** @defgroup RCC_SDIO_Clock_Source_Selection - * @{ - */ -#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00) -#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01) -#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \ - ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK)) -/** - * @} - */ - - -/** @defgroup RCC_48MHZ_Clock_Source_Selection - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469_479xx) -#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00) -#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01) -#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \ - ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI)) -#endif /* STM32F446xx || STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00) -#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */ -#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \ - ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ)) -#endif /* STM32F412xG || STM32F413_423xx */ -/** - * @} - */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F446xx) -/** @defgroup RCC_SPDIFRX_Clock_Source_Selection - * @{ - */ -#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00) -#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01) -#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \ - ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP)) -/** - * @} - */ - -/** @defgroup RCC_CEC_Clock_Source_Selection - * @{ - */ -#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00) -#define RCC_CECCLKSource_LSE ((uint8_t)0x01) -#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \ - ((CLKSOURCE) == RCC_CECCLKSource_LSE)) -/** - * @} - */ - -/** @defgroup RCC_AHB1_ClockGating - * @{ - */ -#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001) -#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002) -#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004) -#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008) -#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010) -#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020) -#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040) - -#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ -#endif /* STM32F446xx */ - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** @defgroup RCC_FMPI2C1_Clock_Source - * @{ - */ -#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00) -#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0) -#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1) - -#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \ - ((SOURCE) == RCC_FMPI2C1CLKSource_HSI)) -/** - * @} - */ -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) -/** @defgroup RCC_DFSDM_Clock_Source - * @{ - */ -#define RCC_DFSDMCLKSource_APB ((uint8_t)0x00) -#define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01) -#define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS)) - -/* Legacy Defines */ -#define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB -#define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS -#define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE -/** - * @} - */ - -/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL) -#define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2)) - -/* Legacy Defines */ -#define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE -/** - * @} - */ - -#if defined(STM32F413_423xx) -/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source - * @{ - */ -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000) -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL) -#define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2)) -/** - * @} - */ -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx */ - -/** @defgroup RCC_AHB1_Peripherals - * @{ - */ -#define RCC_AHB1Periph_GPIOA ((uint32_t)0x00000001) -#define RCC_AHB1Periph_GPIOB ((uint32_t)0x00000002) -#define RCC_AHB1Periph_GPIOC ((uint32_t)0x00000004) -#define RCC_AHB1Periph_GPIOD ((uint32_t)0x00000008) -#define RCC_AHB1Periph_GPIOE ((uint32_t)0x00000010) -#define RCC_AHB1Periph_GPIOF ((uint32_t)0x00000020) -#define RCC_AHB1Periph_GPIOG ((uint32_t)0x00000040) -#define RCC_AHB1Periph_GPIOH ((uint32_t)0x00000080) -#define RCC_AHB1Periph_GPIOI ((uint32_t)0x00000100) -#define RCC_AHB1Periph_GPIOJ ((uint32_t)0x00000200) -#define RCC_AHB1Periph_GPIOK ((uint32_t)0x00000400) -#define RCC_AHB1Periph_CRC ((uint32_t)0x00001000) -#define RCC_AHB1Periph_FLITF ((uint32_t)0x00008000) -#define RCC_AHB1Periph_SRAM1 ((uint32_t)0x00010000) -#define RCC_AHB1Periph_SRAM2 ((uint32_t)0x00020000) -#define RCC_AHB1Periph_BKPSRAM ((uint32_t)0x00040000) -#define RCC_AHB1Periph_SRAM3 ((uint32_t)0x00080000) -#define RCC_AHB1Periph_CCMDATARAMEN ((uint32_t)0x00100000) -#define RCC_AHB1Periph_DMA1 ((uint32_t)0x00200000) -#define RCC_AHB1Periph_DMA2 ((uint32_t)0x00400000) -#define RCC_AHB1Periph_DMA2D ((uint32_t)0x00800000) -#define RCC_AHB1Periph_ETH_MAC ((uint32_t)0x02000000) -#define RCC_AHB1Periph_ETH_MAC_Tx ((uint32_t)0x04000000) -#define RCC_AHB1Periph_ETH_MAC_Rx ((uint32_t)0x08000000) -#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000) -#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000) -#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000) -#if defined(STM32F410xx) -#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000) -#endif /* STM32F410xx */ -#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripherals - * @{ - */ -#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001) -#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010) -#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020) -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040) -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ -#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080) -#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripherals - * @{ - */ -#if defined(STM32F40_41xxx) -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F40_41xxx */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) -#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined(STM32F446xx) || defined(STM32F469_479xx) -#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001) -#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001) -#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002) -#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00)) -#endif /* STM32F412xG || STM32F413_423xx */ - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripherals - * @{ - */ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) -#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) -#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) -#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) -#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) -#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) -#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) -#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) -#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) -#if defined(STM32F410xx) || defined(STM32F413_423xx) -#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200) -#endif /* STM32F410xx || STM32F413_423xx */ -#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) -#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) -#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) -#if defined(STM32F446xx) -#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000) -#endif /* STM32F446xx */ -#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) -#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) -#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) -#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) -#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) -#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) -#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000) -#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/ -#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) -#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) -#if defined(STM32F413_423xx) -#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000) -#endif /* STM32F413_423xx */ -#if defined(STM32F446xx) -#define RCC_APB1Periph_CEC ((uint32_t)0x08000000) -#endif /* STM32F446xx */ -#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) -#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) -#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000) -#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000) -#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripherals - * @{ - */ -#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000001) -#define RCC_APB2Periph_TIM8 ((uint32_t)0x00000002) -#define RCC_APB2Periph_USART1 ((uint32_t)0x00000010) -#define RCC_APB2Periph_USART6 ((uint32_t)0x00000020) -#define RCC_APB2Periph_ADC ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000100) -#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000200) -#define RCC_APB2Periph_ADC3 ((uint32_t)0x00000400) -#define RCC_APB2Periph_SDIO ((uint32_t)0x00000800) -#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) -#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000) -#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000) -#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000) -#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000) -#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000) -#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000) -#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000) -#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000) -#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000) -#if defined(STM32F446xx) || defined(STM32F469_479xx) -#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000) -#endif /* STM32F446xx || STM32F469_479xx */ -#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000) -#if defined(STM32F469_479xx) -#define RCC_APB2Periph_DSI ((uint32_t)0x08000000) -#endif /* STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) -#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000) -#endif /* STM32F412xG || STM32F413_423xx */ -#if defined(STM32F413_423xx) -#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000) -#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040) -#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080) -#endif /* STM32F413_423xx */ - -/* Legacy Defines */ -#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1 - -#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00)) -#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00)) - -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO1Source_HSI ((uint32_t)0x00000000) -#define RCC_MCO1Source_LSE ((uint32_t)0x00200000) -#define RCC_MCO1Source_HSE ((uint32_t)0x00400000) -#define RCC_MCO1Source_PLLCLK ((uint32_t)0x00600000) -#define RCC_MCO1Div_1 ((uint32_t)0x00000000) -#define RCC_MCO1Div_2 ((uint32_t)0x04000000) -#define RCC_MCO1Div_3 ((uint32_t)0x05000000) -#define RCC_MCO1Div_4 ((uint32_t)0x06000000) -#define RCC_MCO1Div_5 ((uint32_t)0x07000000) -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \ - ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK)) - -#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \ - ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \ - ((DIV) == RCC_MCO1Div_5)) -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source_Prescaler - * @{ - */ -#define RCC_MCO2Source_SYSCLK ((uint32_t)0x00000000) -#define RCC_MCO2Source_PLLI2SCLK ((uint32_t)0x40000000) -#define RCC_MCO2Source_HSE ((uint32_t)0x80000000) -#define RCC_MCO2Source_PLLCLK ((uint32_t)0xC0000000) -#define RCC_MCO2Div_1 ((uint32_t)0x00000000) -#define RCC_MCO2Div_2 ((uint32_t)0x20000000) -#define RCC_MCO2Div_3 ((uint32_t)0x28000000) -#define RCC_MCO2Div_4 ((uint32_t)0x30000000) -#define RCC_MCO2Div_5 ((uint32_t)0x38000000) -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK)) - -#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \ - ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \ - ((DIV) == RCC_MCO2Div_5)) -/** - * @} - */ - -/** @defgroup RCC_Flag - * @{ - */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21) -#define RCC_FLAG_HSERDY ((uint8_t)0x31) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3D) -#define RCC_FLAG_LSERDY ((uint8_t)0x41) -#define RCC_FLAG_LSIRDY ((uint8_t)0x61) -#define RCC_FLAG_BORRST ((uint8_t)0x79) -#define RCC_FLAG_PINRST ((uint8_t)0x7A) -#define RCC_FLAG_PORRST ((uint8_t)0x7B) -#define RCC_FLAG_SFTRST ((uint8_t)0x7C) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) - -#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ - ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ - ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \ - ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \ - ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \ - ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \ - ((FLAG) == RCC_FLAG_PLLI2SRDY)|| ((FLAG) == RCC_FLAG_PLLSAIRDY)) - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RCC clock configuration to the default reset state */ -void RCC_DeInit(void); - -/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ -void RCC_HSEConfig(uint8_t RCC_HSE); -ErrorStatus RCC_WaitForHSEStartUp(void); -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); -void RCC_HSICmd(FunctionalState NewState); -void RCC_LSEConfig(uint8_t RCC_LSE); -void RCC_LSICmd(FunctionalState NewState); - -void RCC_PLLCmd(FunctionalState NewState); - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR); -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -void RCC_PLLI2SCmd(FunctionalState NewState); - -#if defined(STM32F40_41xxx) || defined(STM32F401xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR); -#endif /* STM32F40_41xxx || STM32F401xx */ -#if defined(STM32F411xE) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM); -#endif /* STM32F411xE */ -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR); -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR); -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - -void RCC_PLLSAICmd(FunctionalState NewState); -#if defined(STM32F469_479xx) -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR); -#endif /* STM32F469_479xx */ -#if defined(STM32F446xx) -void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ); -#endif /* STM32F446xx */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -void RCC_ClockSecuritySystemCmd(FunctionalState NewState); -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div); -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div); - -/* System, AHB and APB busses clocks configuration functions ******************/ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); -uint8_t RCC_GetSYSCLKSource(void); -void RCC_HCLKConfig(uint32_t RCC_SYSCLK); -void RCC_PCLK1Config(uint32_t RCC_HCLK); -void RCC_PCLK2Config(uint32_t RCC_HCLK); -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); - -/* Peripheral clocks configuration functions **********************************/ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); -void RCC_RTCCLKCmd(FunctionalState NewState); -void RCC_BackupResetCmd(FunctionalState NewState); - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource); -#if defined(STM32F446xx) -void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource); -#endif /* STM32F446xx */ -#if defined(STM32F413_423xx) -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource); -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ); -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ); - -#if defined(STM32F413_423xx) -void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR); -void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR); -#endif /* STM32F413_423xx */ - -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR); -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler); - -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); - -/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */ -void RCC_LSEModeConfig(uint8_t RCC_Mode); - -/* Features available only for STM32F469_479xx devices */ -#if defined(STM32F469_479xx) -void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource); -#endif /* STM32F469_479xx */ - -/* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */ -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource); -void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource); -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -/* Features available only for STM32F446xx devices */ -#if defined(STM32F446xx) -void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState); -void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource); -void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource); -#endif /* STM32F446xx */ - -/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */ -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource); -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/* Features available only for STM32F410xx devices */ -#if defined(STM32F410xx) || defined(STM32F413_423xx) -void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource); -#if defined(STM32F410xx) -void RCC_MCO1Cmd(FunctionalState NewState); -void RCC_MCO2Cmd(FunctionalState NewState); -#endif /* STM32F410xx */ -#endif /* STM32F410xx || STM32F413_423xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) -void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource); -void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource); -#if defined(STM32F413_423xx) -void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource); -#endif /* STM32F413_423xx */ -/* Legacy Defines */ -#define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig -#endif /* STM32F412xG || STM32F413_423xx */ -/* Interrupts and flags management functions **********************************/ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); -void RCC_ClearFlag(void); -ITStatus RCC_GetITStatus(uint8_t RCC_IT); -void RCC_ClearITPendingBit(uint8_t RCC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_RCC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h deleted file mode 100644 index aa8e26dad..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the Random - * Number Generator(RNG) firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RNG_H -#define __STM32F4xx_RNG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RNG - * @{ - */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Constants - * @{ - */ - -/** @defgroup RNG_flags_definition - * @{ - */ -#define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */ - -#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \ - ((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \ - ((RNG_FLAG) == RNG_FLAG_SECS)) -/** - * @} - */ - -/** @defgroup RNG_interrupts_definition - * @{ - */ -#define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */ - -#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00)) -#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RNG configuration to the default reset state *****/ -void RNG_DeInit(void); - -/* Configuration function *****************************************************/ -void RNG_Cmd(FunctionalState NewState); - -/* Get 32 bit Random number function ******************************************/ -uint32_t RNG_GetRandomNumber(void); - -/* Interrupts and flags management functions **********************************/ -void RNG_ITConfig(FunctionalState NewState); -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); -void RNG_ClearFlag(uint8_t RNG_FLAG); -ITStatus RNG_GetITStatus(uint8_t RNG_IT); -void RNG_ClearITPendingBit(uint8_t RNG_IT); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RNG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h deleted file mode 100644 index ec6f6fd41..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h +++ /dev/null @@ -1,888 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the RTC firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_RTC_H -#define __STM32F4xx_RTC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be set to a value lower than 0x7F */ - - uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be set to a value lower than 0x7FFF */ -}RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. - This parameter must be set to a value in the 0-12 range - if the RTC_HourFormat_12 is selected or 0-23 range if - the RTC_HourFormat_24 is selected. */ - - uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be set to a value in the 0-59 range. */ - - uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ -}RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t RTC_Date; /*!< Specifies the RTC Date. - This parameter must be set to a value in the 1-31 range. */ - - uint8_t RTC_Year; /*!< Specifies the RTC Date Year. - This parameter must be set to a value in the 0-99 range. */ -}RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter - must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this - parameter can be a value of @ref RTC_WeekDay_Definitions */ -}RTC_AlarmTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants - * @{ - */ - - -/** @defgroup RTC_Hour_Formats - * @{ - */ -#define RTC_HourFormat_24 ((uint32_t)0x00000000) -#define RTC_HourFormat_12 ((uint32_t)0x00000040) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ - ((FORMAT) == RTC_HourFormat_24)) -/** - * @} - */ - -/** @defgroup RTC_Asynchronous_Predivider - * @{ - */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) - -/** - * @} - */ - - -/** @defgroup RTC_Synchronous_Predivider - * @{ - */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) - -/** - * @} - */ - -/** @defgroup RTC_Time_Definitions - * @{ - */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) - -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions - * @{ - */ -#define RTC_H12_AM ((uint8_t)0x00) -#define RTC_H12_PM ((uint8_t)0x40) -#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) - -/** - * @} - */ - -/** @defgroup RTC_Year_Date_Definitions - * @{ - */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) - -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions - * @{ - */ - -/* Coded in BCD format */ -#define RTC_Month_January ((uint8_t)0x01) -#define RTC_Month_February ((uint8_t)0x02) -#define RTC_Month_March ((uint8_t)0x03) -#define RTC_Month_April ((uint8_t)0x04) -#define RTC_Month_May ((uint8_t)0x05) -#define RTC_Month_June ((uint8_t)0x06) -#define RTC_Month_July ((uint8_t)0x07) -#define RTC_Month_August ((uint8_t)0x08) -#define RTC_Month_September ((uint8_t)0x09) -#define RTC_Month_October ((uint8_t)0x10) -#define RTC_Month_November ((uint8_t)0x11) -#define RTC_Month_December ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) - -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions - * @{ - */ - -#define RTC_Weekday_Monday ((uint8_t)0x01) -#define RTC_Weekday_Tuesday ((uint8_t)0x02) -#define RTC_Weekday_Wednesday ((uint8_t)0x03) -#define RTC_Weekday_Thursday ((uint8_t)0x04) -#define RTC_Weekday_Friday ((uint8_t)0x05) -#define RTC_Weekday_Saturday ((uint8_t)0x06) -#define RTC_Weekday_Sunday ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) -/** - * @} - */ - - -/** @defgroup RTC_Alarm_Definitions - * @{ - */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ - ((WEEKDAY) == RTC_Weekday_Tuesday) || \ - ((WEEKDAY) == RTC_Weekday_Wednesday) || \ - ((WEEKDAY) == RTC_Weekday_Thursday) || \ - ((WEEKDAY) == RTC_Weekday_Friday) || \ - ((WEEKDAY) == RTC_Weekday_Saturday) || \ - ((WEEKDAY) == RTC_Weekday_Sunday)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmDateWeekDay_Definitions - * @{ - */ -#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) -#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ - ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay)) - -/** - * @} - */ - - -/** @defgroup RTC_AlarmMask_Definitions - * @{ - */ -#define RTC_AlarmMask_None ((uint32_t)0x00000000) -#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) -#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) -#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) -#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) -#define RTC_AlarmMask_All ((uint32_t)0x80808080) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) - -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions - * @{ - */ -#define RTC_Alarm_A ((uint32_t)0x00000100) -#define RTC_Alarm_B ((uint32_t)0x00000200) -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) -#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET) - -/** - * @} - */ - - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions - * @{ - */ -#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ - ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ - ((MASK) == RTC_AlarmSubSecondMask_None)) -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Value - * @{ - */ - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Wakeup_Timer_Definitions - * @{ - */ -#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000) -#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001) -#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002) -#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003) -#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004) -#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006) -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \ - ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \ - ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) -/** - * @} - */ - -/** @defgroup RTC_Time_Stamp_Edges_definitions - * @{ - */ -#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) -#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) -#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ - ((EDGE) == RTC_TimeStampEdge_Falling)) -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions - * @{ - */ -#define RTC_Output_Disable ((uint32_t)0x00000000) -#define RTC_Output_AlarmA ((uint32_t)0x00200000) -#define RTC_Output_AlarmB ((uint32_t)0x00400000) -#define RTC_Output_WakeUp ((uint32_t)0x00600000) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ - ((OUTPUT) == RTC_Output_AlarmA) || \ - ((OUTPUT) == RTC_Output_AlarmB) || \ - ((OUTPUT) == RTC_Output_WakeUp)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions - * @{ - */ -#define RTC_OutputPolarity_High ((uint32_t)0x00000000) -#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ - ((POL) == RTC_OutputPolarity_Low)) -/** - * @} - */ - - -/** @defgroup RTC_Digital_Calibration_Definitions - * @{ - */ -#define RTC_CalibSign_Positive ((uint32_t)0x00000000) -#define RTC_CalibSign_Negative ((uint32_t)0x00000080) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \ - ((SIGN) == RTC_CalibSign_Negative)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) - -/** - * @} - */ - - /** @defgroup RTC_Calib_Output_selection_Definitions - * @{ - */ -#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) -#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ - ((OUTPUT) == RTC_CalibOutput_1Hz)) -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_period_Definitions - * @{ - */ -#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ - ((PERIOD) == RTC_SmoothCalibPeriod_8sec)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions - * @{ - */ -#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0]. - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0]. */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ - ((PLUS) == RTC_SmoothCalibPlusPulses_Reset)) - -/** - * @} - */ - -/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions - * @{ - */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) - -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions - * @{ - */ -#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) -#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \ - ((SAVE) == RTC_DayLightSaving_ADD1H)) - -#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) -#define RTC_StoreOperation_Set ((uint32_t)0x00040000) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ - ((OPERATION) == RTC_StoreOperation_Set)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Trigger_Definitions - * @{ - */ -#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) -#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001) -#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) -#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001) -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ - ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ - ((TRIGGER) == RTC_TamperTrigger_HighLevel)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Filter_Definitions - * @{ - */ -#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ - -#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 - consecutive samples at the active level. */ -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ - ((FILTER) == RTC_TamperFilter_2Sample) || \ - ((FILTER) == RTC_TamperFilter_4Sample) || \ - ((FILTER) == RTC_TamperFilter_8Sample)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ - ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256)) - -/** - * @} - */ - - /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions - * @{ - */ -#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ - ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK)) -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pins_Definitions - * @{ - */ -#define RTC_Tamper_1 RTC_TAFCR_TAMP1E -#define RTC_Tamper_2 RTC_TAFCR_TAMP2E -#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1) || ((TAMPER) == RTC_Tamper_2)) - -/** - * @} - */ - -/** @defgroup RTC_Tamper_Pin_Selection - * @{ - */ -#define RTC_TamperPin_Default ((uint32_t)0x00000000) -#define RTC_TamperPin_Pos1 ((uint32_t)0x00010000) -#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_Default) || \ - ((PIN) == RTC_TamperPin_Pos1)) -/* Legacy Defines */ -#define RTC_TamperPin_PC13 RTC_TamperPin_Default -#define RTC_TamperPin_PI8 RTC_TamperPin_Pos1 -/** - * @} - */ - -/** @defgroup RTC_TimeStamp_Pin_Selection - * @{ - */ -#define RTC_TimeStampPin_PC13 ((uint32_t)0x00000000) -#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000) -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \ - ((PIN) == RTC_TimeStampPin_PI8)) - -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT - * @{ - */ -#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) -#define RTC_OutputType_PushPull ((uint32_t)0x00040000) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ - ((TYPE) == RTC_OutputType_PushPull)) - -/** - * @} - */ - -/** @defgroup RTC_Add_1_Second_Parameter_Definitions - * @{ - */ -#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) -#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ - ((SEL) == RTC_ShiftAdd1S_Set)) -/** - * @} - */ - -/** @defgroup RTC_Substract_Fraction_Of_Second_Value - * @{ - */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) - -/** - * @} - */ - -/** @defgroup RTC_Backup_Registers_Definitions - * @{ - */ - -#define RTC_BKP_DR0 ((uint32_t)0x00000000) -#define RTC_BKP_DR1 ((uint32_t)0x00000001) -#define RTC_BKP_DR2 ((uint32_t)0x00000002) -#define RTC_BKP_DR3 ((uint32_t)0x00000003) -#define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define RTC_BKP_DR5 ((uint32_t)0x00000005) -#define RTC_BKP_DR6 ((uint32_t)0x00000006) -#define RTC_BKP_DR7 ((uint32_t)0x00000007) -#define RTC_BKP_DR8 ((uint32_t)0x00000008) -#define RTC_BKP_DR9 ((uint32_t)0x00000009) -#define RTC_BKP_DR10 ((uint32_t)0x0000000A) -#define RTC_BKP_DR11 ((uint32_t)0x0000000B) -#define RTC_BKP_DR12 ((uint32_t)0x0000000C) -#define RTC_BKP_DR13 ((uint32_t)0x0000000D) -#define RTC_BKP_DR14 ((uint32_t)0x0000000E) -#define RTC_BKP_DR15 ((uint32_t)0x0000000F) -#define RTC_BKP_DR16 ((uint32_t)0x00000010) -#define RTC_BKP_DR17 ((uint32_t)0x00000011) -#define RTC_BKP_DR18 ((uint32_t)0x00000012) -#define RTC_BKP_DR19 ((uint32_t)0x00000013) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions - * @{ - */ -#define RTC_Format_BIN ((uint32_t)0x000000000) -#define RTC_Format_BCD ((uint32_t)0x000000001) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) - -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions - * @{ - */ -#define RTC_FLAG_RECALPF ((uint32_t)0x00010000) -#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000) -#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000) -#define RTC_FLAG_TSOVF ((uint32_t)0x00001000) -#define RTC_FLAG_TSF ((uint32_t)0x00000800) -#define RTC_FLAG_WUTF ((uint32_t)0x00000400) -#define RTC_FLAG_ALRBF ((uint32_t)0x00000200) -#define RTC_FLAG_ALRAF ((uint32_t)0x00000100) -#define RTC_FLAG_INITF ((uint32_t)0x00000040) -#define RTC_FLAG_RSF ((uint32_t)0x00000020) -#define RTC_FLAG_INITS ((uint32_t)0x00000010) -#define RTC_FLAG_SHPF ((uint32_t)0x00000008) -#define RTC_FLAG_WUTWF ((uint32_t)0x00000004) -#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002) -#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001) -#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ - ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ - ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \ - ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \ - ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \ - ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \ - ((FLAG) == RTC_FLAG_TAMP2F) ||((FLAG) == RTC_FLAG_SHPF)) -#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET)) -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions - * @{ - */ -#define RTC_IT_TS ((uint32_t)0x00008000) -#define RTC_IT_WUT ((uint32_t)0x00004000) -#define RTC_IT_ALRB ((uint32_t)0x00002000) -#define RTC_IT_ALRA ((uint32_t)0x00001000) -#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 ((uint32_t)0x00020000) -#define RTC_IT_TAMP2 ((uint32_t)0x00040000) - -#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET)) -#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \ - ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \ - ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2)) -#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET)) - -/** - * @} - */ - -/** @defgroup RTC_Legacy - * @{ - */ -#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig -#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the RTC configuration to the default reset state *****/ -ErrorStatus RTC_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct); -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct); -void RTC_WriteProtectionCmd(FunctionalState NewState); -ErrorStatus RTC_EnterInitMode(void); -void RTC_ExitInitMode(void); -ErrorStatus RTC_WaitForSynchro(void); -ErrorStatus RTC_RefClockCmd(FunctionalState NewState); -void RTC_BypassShadowCmd(FunctionalState NewState); - -/* Time and Date configuration functions **************************************/ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct); -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct); -uint32_t RTC_GetSubSecond(void); -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct); -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct); - -/* Alarms (Alarm A and Alarm B) configuration functions **********************/ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct); -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState); -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask); -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); - -/* WakeUp Timer configuration functions ***************************************/ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); -uint32_t RTC_GetWakeUpCounter(void); -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); - -/* Daylight Saving configuration functions ************************************/ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); -uint32_t RTC_GetStoreOperation(void); - -/* Output pin Configuration function ******************************************/ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); - -/* Digital Calibration configuration functions *********************************/ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value); -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState); -void RTC_CalibOutputCmd(FunctionalState NewState); -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput); -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue); - -/* TimeStamp configuration functions ******************************************/ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct); -uint32_t RTC_GetTimeStampSubSecond(void); - -/* Tampers configuration functions ********************************************/ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); -void RTC_TamperPullUpCmd(FunctionalState NewState); - -/* Backup Data Registers configuration functions ******************************/ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data); -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR); - -/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - functions ******************************************************************/ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin); -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin); -void RTC_OutputTypeConfig(uint32_t RTC_OutputType); - -/* RTC_Shift_control_synchonisation_functions *********************************/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); - -/* Interrupts and flags management functions **********************************/ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState); -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); -void RTC_ClearFlag(uint32_t RTC_FLAG); -ITStatus RTC_GetITStatus(uint32_t RTC_IT); -void RTC_ClearITPendingBit(uint32_t RTC_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_RTC_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h deleted file mode 100644 index 5e7fbe371..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h +++ /dev/null @@ -1,649 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sai.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the SAI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SAI_H -#define __STM32F4xx_SAI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SAI - * @{ - */ -#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \ - defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \ - defined (STM32F413_423xx) -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SAI Block Init structure definition - */ - -typedef struct -{ - uint32_t SAI_AudioMode; /*!< Specifies the SAI Block Audio Mode. - This parameter can be a value of @ref SAI_Block_Mode */ - - uint32_t SAI_Protocol; /*!< Specifies the SAI Block Protocol. - This parameter can be a value of @ref SAI_Block_Protocol */ - - uint32_t SAI_DataSize; /*!< Specifies the SAI Block data size. - This parameter can be a value of @ref SAI_Block_Data_Size - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission - @note this value has no meaning when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. - This parameter can be a value of @ref SAI_Block_Clock_Strobing */ - - uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization - This parameter can be a value of @ref SAI_Block_Synchronization */ - - uint32_t SAI_SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common - for BlockA and BlockB - This parameter can be a value of @ref SAI_Block_SyncExt - @note: If both audio blocks of same SAI are used, this parameter has - to be set to the same value for each audio block */ - - uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven. - This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ - - uint32_t SAI_NoDivider; /*!< Specifies whether Master Clock will be divided or not. - This parameter can be a value of @ref SAI_Block_NoDivider */ - - uint32_t SAI_MasterDivider; /*!< Specifies SAI Block Master Clock Divider. - @note the Master Clock Frequency is calculated accordingly to the - following formula : MCLK_x = SAI_CK_x/(MCKDIV[3:0]*2)*/ - - uint32_t SAI_FIFOThreshold; /*!< Specifies SAI Block FIFO Threshold. - This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ -}SAI_InitTypeDef; - -/** - * @brief SAI Block Frame Init structure definition - */ - -typedef struct -{ - - uint32_t SAI_FrameLength; /*!< Specifies the Frame Length, the number of SCK clocks - for each audio frame. - This parameter must be a number between 8 and 256. - @note If master Clock MCLK_x pin is declared as an output, the frame length - should be Aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. - This Parameter specifies the length in number of bit clock (SCK + 1) - of the active level of FS signal in audio frame. - This parameter must be a number between 1 and 128. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSDefinition; /*!< Specifies the Frame Synchronization definition. - This parameter can be a value of @ref SAI_Block_FS_Definition - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSPolarity; /*!< Specifies the Frame Synchronization Polarity. - This parameter can be a value of @ref SAI_Block_FS_Polarity - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_FSOffset; /*!< Specifies the Frame Synchronization Offset. - This parameter can be a value of @ref SAI_Block_FS_Offset - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - -}SAI_FrameInitTypeDef; - -/** - * @brief SAI Block Slot Init Structure definition - */ - -typedef struct -{ - uint32_t SAI_FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. - This parameter must be a number between 0 and 24. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotSize; /*!< Specifies the Slot Size. - This parameter can be a value of @ref SAI_Block_Slot_Size - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotNumber; /*!< Specifies the number of slot in the audio frame. - This parameter must be a number between 1 and 16. - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ - - uint32_t SAI_SlotActive; /*!< Specifies the slots in audio frame that will be activated. - This parameter can be a value of @ ref SAI_Block_Slot_Active - @note this value is ignored when AC'97 or SPDIF protocols are selected.*/ -}SAI_SlotInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SAI_Exported_Constants - * @{ - */ - -#if defined(STM32F446xx) -#define IS_SAI_PERIPH(PERIPH) (((PERIPH) == SAI1) || ((PERIPH) == SAI2)) - -#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ - ((PERIPH) == SAI1_Block_B) || \ - ((PERIPH) == SAI2_Block_A) || \ - ((PERIPH) == SAI2_Block_B)) -#endif /* STM32F446xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) || defined(STM32F413_423xx) || defined (STM32F469_479xx) - -#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1) - -#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \ - ((PERIPH) == SAI1_Block_B)) -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F413_423xx || STM32F469_479xx */ - -/** @defgroup SAI_Block_Mode - * @{ - */ -#define SAI_Mode_MasterTx ((uint32_t)0x00000000) -#define SAI_Mode_MasterRx ((uint32_t)0x00000001) -#define SAI_Mode_SlaveTx ((uint32_t)0x00000002) -#define SAI_Mode_SlaveRx ((uint32_t)0x00000003) -#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_Mode_MasterTx) || \ - ((MODE) == SAI_Mode_MasterRx) || \ - ((MODE) == SAI_Mode_SlaveTx) || \ - ((MODE) == SAI_Mode_SlaveRx)) -/** - * @} - */ - -/** @defgroup SAI_Block_Protocol - * @{ - */ - -#define SAI_Free_Protocol ((uint32_t)0x00000000) -#define SAI_SPDIF_Protocol ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_Protocol ((uint32_t)SAI_xCR1_PRTCFG_1) -#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_Free_Protocol) || \ - ((PROTOCOL) == SAI_SPDIF_Protocol) || \ - ((PROTOCOL) == SAI_AC97_Protocol)) -/** - * @} - */ - -/** @defgroup SAI_Block_Data_Size - * @{ - */ - -#define SAI_DataSize_8b ((uint32_t)0x00000040) -#define SAI_DataSize_10b ((uint32_t)0x00000060) -#define SAI_DataSize_16b ((uint32_t)0x00000080) -#define SAI_DataSize_20b ((uint32_t)0x000000A0) -#define SAI_DataSize_24b ((uint32_t)0x000000C0) -#define SAI_DataSize_32b ((uint32_t)0x000000E0) -#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DataSize_8b) || \ - ((DATASIZE) == SAI_DataSize_10b) || \ - ((DATASIZE) == SAI_DataSize_16b) || \ - ((DATASIZE) == SAI_DataSize_20b) || \ - ((DATASIZE) == SAI_DataSize_24b) || \ - ((DATASIZE) == SAI_DataSize_32b)) -/** - * @} - */ - -/** @defgroup SAI_Block_MSB_LSB_transmission - * @{ - */ - -#define SAI_FirstBit_MSB ((uint32_t)0x00000000) -#define SAI_FirstBit_LSB ((uint32_t)SAI_xCR1_LSBFIRST) -#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FirstBit_MSB) || \ - ((BIT) == SAI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SAI_Block_Clock_Strobing - * @{ - */ - -#define SAI_ClockStrobing_FallingEdge ((uint32_t)0x00000000) -#define SAI_ClockStrobing_RisingEdge ((uint32_t)SAI_xCR1_CKSTR) -#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_ClockStrobing_FallingEdge) || \ - ((CLOCK) == SAI_ClockStrobing_RisingEdge)) -/** - * @} - */ - -/** @defgroup SAI_Block_Synchronization - * @{ - */ - -#define SAI_Asynchronous ((uint32_t)0x00000000) -#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0) -#define SAI_Synchronous_Ext ((uint32_t)SAI_xCR1_SYNCEN_1) -#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \ - ((SYNCHRO) == SAI_Asynchronous) || \ - ((SYNCHRO) == SAI_Synchronous_Ext)) -/** - * @} - */ - -/** @defgroup SAI_Block_SyncExt SAI External synchronisation - * @{ - */ -#define SAI_SyncExt_Disable ((uint32_t)0x00000000) -#define SAI_SyncExt_OutBlockA_Enable ((uint32_t)SAI_GCR_SYNCOUT_0) -#define SAI_SyncExt_OutBlockB_Enable ((uint32_t)SAI_GCR_SYNCOUT_1) -#define IS_SAI_BLOCK_SYNCEXT(SYNCHRO) (((SYNCHRO) == SAI_SyncExt_Disable) || \ - ((SYNCHRO) == SAI_SyncExt_OutBlockA_Enable)|| \ - ((SYNCHRO) == SAI_SyncExt_OutBlockB_Enable)) -/** - * @} - */ - -/** @defgroup SAI_Block_Output_Drive - * @{ - */ - -#define SAI_OutputDrive_Disabled ((uint32_t)0x00000000) -#define SAI_OutputDrive_Enabled ((uint32_t)SAI_xCR1_OUTDRIV) -#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OutputDrive_Disabled) || \ - ((DRIVE) == SAI_OutputDrive_Enabled)) -/** - * @} - */ - - - -/** @defgroup SAI_Block_NoDivider - * @{ - */ - -#define SAI_MasterDivider_Enabled ((uint32_t)0x00000000) -#define SAI_MasterDivider_Disabled ((uint32_t)SAI_xCR1_NODIV) -#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MasterDivider_Enabled) || \ - ((NODIVIDER) == SAI_MasterDivider_Disabled)) -/** - * @} - */ - - -/** @defgroup SAI_Block_Master_Divider - * @{ - */ -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15) - -/** - * @} - */ - -/** @defgroup SAI_Block_Frame_Length - * @{ - */ -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Active_FrameLength - * @{ - */ -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) - -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Definition - * @{ - */ - -#define SAI_FS_StartFrame ((uint32_t)0x00000000) -#define I2S_FS_ChannelIdentification ((uint32_t)SAI_xFRCR_FSDEF) -#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_StartFrame) || \ - ((DEFINITION) == I2S_FS_ChannelIdentification)) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Polarity - * @{ - */ - -#define SAI_FS_ActiveLow ((uint32_t)0x00000000) -#define SAI_FS_ActiveHigh ((uint32_t)SAI_xFRCR_FSPO) -#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ActiveLow) || \ - ((POLARITY) == SAI_FS_ActiveHigh)) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Offset - * @{ - */ - -#define SAI_FS_FirstBit ((uint32_t)0x00000000) -#define SAI_FS_BeforeFirstBit ((uint32_t)SAI_xFRCR_FSOFF) -#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FirstBit) || \ - ((OFFSET) == SAI_FS_BeforeFirstBit)) -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_FirstBit_Offset - * @{ - */ -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) - -/** - * @} - */ - - /** @defgroup SAI_Block_Slot_Size - * @{ - */ -#define SAI_SlotSize_DataSize ((uint32_t)0x00000000) -#define SAI_SlotSize_16b ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SlotSize_32b ((uint32_t)SAI_xSLOTR_SLOTSZ_1) -#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SlotSize_DataSize) || \ - ((SIZE) == SAI_SlotSize_16b) || \ - ((SIZE) == SAI_SlotSize_32b)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Number - * @{ - */ -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Active - * @{ - */ -#define SAI_Slot_NotActive ((uint32_t)0x00000000) -#define SAI_SlotActive_0 ((uint32_t)0x00010000) -#define SAI_SlotActive_1 ((uint32_t)0x00020000) -#define SAI_SlotActive_2 ((uint32_t)0x00040000) -#define SAI_SlotActive_3 ((uint32_t)0x00080000) -#define SAI_SlotActive_4 ((uint32_t)0x00100000) -#define SAI_SlotActive_5 ((uint32_t)0x00200000) -#define SAI_SlotActive_6 ((uint32_t)0x00400000) -#define SAI_SlotActive_7 ((uint32_t)0x00800000) -#define SAI_SlotActive_8 ((uint32_t)0x01000000) -#define SAI_SlotActive_9 ((uint32_t)0x02000000) -#define SAI_SlotActive_10 ((uint32_t)0x04000000) -#define SAI_SlotActive_11 ((uint32_t)0x08000000) -#define SAI_SlotActive_12 ((uint32_t)0x10000000) -#define SAI_SlotActive_13 ((uint32_t)0x20000000) -#define SAI_SlotActive_14 ((uint32_t)0x40000000) -#define SAI_SlotActive_15 ((uint32_t)0x80000000) -#define SAI_SlotActive_ALL ((uint32_t)0xFFFF0000) - -#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) != 0) - -/** - * @} - */ - -/** @defgroup SAI_Mono_Streo_Mode - * @{ - */ - -#define SAI_MonoMode ((uint32_t)SAI_xCR1_MONO) -#define SAI_StreoMode ((uint32_t)0x00000000) -#define IS_SAI_BLOCK_MONO_STREO_MODE(MODE) (((MODE) == SAI_MonoMode) ||\ - ((MODE) == SAI_StreoMode)) -/** - * @} - */ - -/** @defgroup SAI_TRIState_Management - * @{ - */ - -#define SAI_Output_NotReleased ((uint32_t)0x00000000) -#define SAI_Output_Released ((uint32_t)SAI_xCR2_TRIS) -#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_Output_NotReleased) ||\ - ((STATE) == SAI_Output_Released)) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Threshold - * @{ - */ - -#define SAI_Threshold_FIFOEmpty ((uint32_t)0x00000000) -#define SAI_FIFOThreshold_1QuarterFull ((uint32_t)0x00000001) -#define SAI_FIFOThreshold_HalfFull ((uint32_t)0x00000002) -#define SAI_FIFOThreshold_3QuartersFull ((uint32_t)0x00000003) -#define SAI_FIFOThreshold_Full ((uint32_t)0x00000004) -#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_Threshold_FIFOEmpty) || \ - ((THRESHOLD) == SAI_FIFOThreshold_1QuarterFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_HalfFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_3QuartersFull) || \ - ((THRESHOLD) == SAI_FIFOThreshold_Full)) -/** - * @} - */ - -/** @defgroup SAI_Block_Companding_Mode - * @{ - */ - -#define SAI_NoCompanding ((uint32_t)0x00000000) -#define SAI_ULaw_1CPL_Companding ((uint32_t)0x00008000) -#define SAI_ALaw_1CPL_Companding ((uint32_t)0x0000C000) -#define SAI_ULaw_2CPL_Companding ((uint32_t)0x0000A000) -#define SAI_ALaw_2CPL_Companding ((uint32_t)0x0000E000) -#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NoCompanding) || \ - ((MODE) == SAI_ULaw_1CPL_Companding) || \ - ((MODE) == SAI_ALaw_1CPL_Companding) || \ - ((MODE) == SAI_ULaw_2CPL_Companding) || \ - ((MODE) == SAI_ALaw_2CPL_Companding)) -/** - * @} - */ - -/** @defgroup SAI_Block_Mute_Value - * @{ - */ - -#define SAI_ZeroValue ((uint32_t)0x00000000) -#define SAI_LastSentValue ((uint32_t)SAI_xCR2_MUTEVAL) -#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZeroValue) || \ - ((VALUE) == SAI_LastSentValue)) -/** - * @} - */ - -/** @defgroup SAI_Block_Mute_Frame_Counter - * @{ - */ - -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) - -/** - * @} - */ - -/** @defgroup SAI_Block_Interrupts_Definition - * @{ - */ - -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) - -#define IS_SAI_BLOCK_CONFIG_IT(IT) (((IT) == SAI_IT_OVRUDR) || \ - ((IT) == SAI_IT_MUTEDET) || \ - ((IT) == SAI_IT_WCKCFG) || \ - ((IT) == SAI_IT_FREQ) || \ - ((IT) == SAI_IT_CNRDY) || \ - ((IT) == SAI_IT_AFSDET) || \ - ((IT) == SAI_IT_LFSDET)) -/** - * @} - */ - -/** @defgroup SAI_Block_Flags_Definition - * @{ - */ - -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) - -#define IS_SAI_BLOCK_GET_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ - ((FLAG) == SAI_FLAG_MUTEDET) || \ - ((FLAG) == SAI_FLAG_WCKCFG) || \ - ((FLAG) == SAI_FLAG_FREQ) || \ - ((FLAG) == SAI_FLAG_CNRDY) || \ - ((FLAG) == SAI_FLAG_AFSDET) || \ - ((FLAG) == SAI_FLAG_LFSDET)) - -#define IS_SAI_BLOCK_CLEAR_FLAG(FLAG) (((FLAG) == SAI_FLAG_OVRUDR) || \ - ((FLAG) == SAI_FLAG_MUTEDET) || \ - ((FLAG) == SAI_FLAG_WCKCFG) || \ - ((FLAG) == SAI_FLAG_FREQ) || \ - ((FLAG) == SAI_FLAG_CNRDY) || \ - ((FLAG) == SAI_FLAG_AFSDET) || \ - ((FLAG) == SAI_FLAG_LFSDET)) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Status_Level - * @{ - */ -#define SAI_FIFOStatus_Empty ((uint32_t)0x00000000) -#define SAI_FIFOStatus_Less1QuarterFull ((uint32_t)0x00010000) -#define SAI_FIFOStatus_1QuarterFull ((uint32_t)0x00020000) -#define SAI_FIFOStatus_HalfFull ((uint32_t)0x00030000) -#define SAI_FIFOStatus_3QuartersFull ((uint32_t)0x00040000) -#define SAI_FIFOStatus_Full ((uint32_t)0x00050000) - -#define IS_SAI_BLOCK_FIFO_STATUS(STATUS) (((STATUS) == SAI_FIFOStatus_Less1QuarterFull ) || \ - ((STATUS) == SAI_FIFOStatus_HalfFull) || \ - ((STATUS) == SAI_FIFOStatus_1QuarterFull) || \ - ((STATUS) == SAI_FIFOStatus_3QuartersFull) || \ - ((STATUS) == SAI_FIFOStatus_Full) || \ - ((STATUS) == SAI_FIFOStatus_Empty)) -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SAI configuration to the default reset state *****/ -void SAI_DeInit(SAI_TypeDef* SAIx); - -/* Initialization and Configuration functions *********************************/ -void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct); -void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct); -void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct); -void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct); -void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct); -void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct); - -void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); -void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode); -void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState); -void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode); -void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); -void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue); -void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter); -void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx) -void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */ -/* Data transfers functions ***************************************************/ -void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data); -uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x); - -/* DMA transfers management functions *****************************************/ -void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); -FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); -void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); -ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); -void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); -FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); -uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); - -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SAI_H */ - -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h deleted file mode 100644 index dc6c2e9ef..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the SDIO firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SDIO_H -#define __STM32F4xx_SDIO_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SDIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -typedef struct -{ - uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDIO_Clock_Edge */ - - uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDIO_Clock_Bypass */ - - uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDIO_Clock_Power_Save */ - - uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width. - This parameter can be a value of @ref SDIO_Bus_Wide */ - - uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ - - uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. - This parameter can be a value between 0x00 and 0xFF. */ - -} SDIO_InitTypeDef; - -typedef struct -{ - uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register */ - - uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */ - - uint32_t SDIO_Response; /*!< Specifies the SDIO response type. - This parameter can be a value of @ref SDIO_Response_Type */ - - uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait for interrupt request is enabled or disabled. - This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ - - uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_CPSM_State */ -} SDIO_CmdInitTypeDef; - -typedef struct -{ - uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDIO_Data_Block_Size */ - - uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDIO_Transfer_Direction */ - - uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDIO_Transfer_Type */ - - uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDIO_DPSM_State */ -} SDIO_DataInitTypeDef; - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SDIO_Exported_Constants - * @{ - */ - -/** @defgroup SDIO_Clock_Edge - * @{ - */ - -#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) -#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) -#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \ - ((EDGE) == SDIO_ClockEdge_Falling)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Bypass - * @{ - */ - -#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) -#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \ - ((BYPASS) == SDIO_ClockBypass_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Clock_Power_Save - * @{ - */ - -#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) -#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) -#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \ - ((SAVE) == SDIO_ClockPowerSave_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Bus_Wide - * @{ - */ - -#define SDIO_BusWide_1b ((uint32_t)0x00000000) -#define SDIO_BusWide_4b ((uint32_t)0x00000800) -#define SDIO_BusWide_8b ((uint32_t)0x00001000) -#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \ - ((WIDE) == SDIO_BusWide_8b)) - -/** - * @} - */ - -/** @defgroup SDIO_Hardware_Flow_Control - * @{ - */ - -#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) -#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) -#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \ - ((CONTROL) == SDIO_HardwareFlowControl_Enable)) -/** - * @} - */ - -/** @defgroup SDIO_Power_State - * @{ - */ - -#define SDIO_PowerState_OFF ((uint32_t)0x00000000) -#define SDIO_PowerState_ON ((uint32_t)0x00000003) -#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON)) -/** - * @} - */ - - -/** @defgroup SDIO_Interrupt_sources - * @{ - */ - -#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) -#define SDIO_IT_CMDREND ((uint32_t)0x00000040) -#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) -#define SDIO_IT_DATAEND ((uint32_t)0x00000100) -#define SDIO_IT_STBITERR ((uint32_t)0x00000200) -#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) -#define SDIO_IT_CMDACT ((uint32_t)0x00000800) -#define SDIO_IT_TXACT ((uint32_t)0x00001000) -#define SDIO_IT_RXACT ((uint32_t)0x00002000) -#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) -#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) -#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) -#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00)) -/** - * @} - */ - -/** @defgroup SDIO_Command_Index - * @{ - */ - -#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40) -/** - * @} - */ - -/** @defgroup SDIO_Response_Type - * @{ - */ - -#define SDIO_Response_No ((uint32_t)0x00000000) -#define SDIO_Response_Short ((uint32_t)0x00000040) -#define SDIO_Response_Long ((uint32_t)0x000000C0) -#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \ - ((RESPONSE) == SDIO_Response_Short) || \ - ((RESPONSE) == SDIO_Response_Long)) -/** - * @} - */ - -/** @defgroup SDIO_Wait_Interrupt_State - * @{ - */ - -#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */ -#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */ -#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */ -#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \ - ((WAIT) == SDIO_Wait_Pend)) -/** - * @} - */ - -/** @defgroup SDIO_CPSM_State - * @{ - */ - -#define SDIO_CPSM_Disable ((uint32_t)0x00000000) -#define SDIO_CPSM_Enable ((uint32_t)0x00000400) -#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Response_Registers - * @{ - */ - -#define SDIO_RESP1 ((uint32_t)0x00000000) -#define SDIO_RESP2 ((uint32_t)0x00000004) -#define SDIO_RESP3 ((uint32_t)0x00000008) -#define SDIO_RESP4 ((uint32_t)0x0000000C) -#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \ - ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4)) -/** - * @} - */ - -/** @defgroup SDIO_Data_Length - * @{ - */ - -#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF) -/** - * @} - */ - -/** @defgroup SDIO_Data_Block_Size - * @{ - */ - -#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) -#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) -#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) -#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) -#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) -#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) -#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) -#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) -#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) -#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) -#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) -#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) -#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) -#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) -#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) -#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \ - ((SIZE) == SDIO_DataBlockSize_2b) || \ - ((SIZE) == SDIO_DataBlockSize_4b) || \ - ((SIZE) == SDIO_DataBlockSize_8b) || \ - ((SIZE) == SDIO_DataBlockSize_16b) || \ - ((SIZE) == SDIO_DataBlockSize_32b) || \ - ((SIZE) == SDIO_DataBlockSize_64b) || \ - ((SIZE) == SDIO_DataBlockSize_128b) || \ - ((SIZE) == SDIO_DataBlockSize_256b) || \ - ((SIZE) == SDIO_DataBlockSize_512b) || \ - ((SIZE) == SDIO_DataBlockSize_1024b) || \ - ((SIZE) == SDIO_DataBlockSize_2048b) || \ - ((SIZE) == SDIO_DataBlockSize_4096b) || \ - ((SIZE) == SDIO_DataBlockSize_8192b) || \ - ((SIZE) == SDIO_DataBlockSize_16384b)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Direction - * @{ - */ - -#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) -#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) -#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \ - ((DIR) == SDIO_TransferDir_ToSDIO)) -/** - * @} - */ - -/** @defgroup SDIO_Transfer_Type - * @{ - */ - -#define SDIO_TransferMode_Block ((uint32_t)0x00000000) -#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) -#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \ - ((MODE) == SDIO_TransferMode_Block)) -/** - * @} - */ - -/** @defgroup SDIO_DPSM_State - * @{ - */ - -#define SDIO_DPSM_Disable ((uint32_t)0x00000000) -#define SDIO_DPSM_Enable ((uint32_t)0x00000001) -#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable)) -/** - * @} - */ - -/** @defgroup SDIO_Flags - * @{ - */ - -#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) -#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) -#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) -#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) -#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) -#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) -#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) -#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) -#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) -#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) -#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) -#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) -#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) -#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) -#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) -#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) -#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) -#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) -#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) -#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) -#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) -#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) -#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) -#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) -#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_DCRCFAIL) || \ - ((FLAG) == SDIO_FLAG_CTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_DTIMEOUT) || \ - ((FLAG) == SDIO_FLAG_TXUNDERR) || \ - ((FLAG) == SDIO_FLAG_RXOVERR) || \ - ((FLAG) == SDIO_FLAG_CMDREND) || \ - ((FLAG) == SDIO_FLAG_CMDSENT) || \ - ((FLAG) == SDIO_FLAG_DATAEND) || \ - ((FLAG) == SDIO_FLAG_STBITERR) || \ - ((FLAG) == SDIO_FLAG_DBCKEND) || \ - ((FLAG) == SDIO_FLAG_CMDACT) || \ - ((FLAG) == SDIO_FLAG_TXACT) || \ - ((FLAG) == SDIO_FLAG_RXACT) || \ - ((FLAG) == SDIO_FLAG_TXFIFOHE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOHF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOF) || \ - ((FLAG) == SDIO_FLAG_RXFIFOF) || \ - ((FLAG) == SDIO_FLAG_TXFIFOE) || \ - ((FLAG) == SDIO_FLAG_RXFIFOE) || \ - ((FLAG) == SDIO_FLAG_TXDAVL) || \ - ((FLAG) == SDIO_FLAG_RXDAVL) || \ - ((FLAG) == SDIO_FLAG_SDIOIT) || \ - ((FLAG) == SDIO_FLAG_CEATAEND)) - -#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00)) - -#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \ - ((IT) == SDIO_IT_DCRCFAIL) || \ - ((IT) == SDIO_IT_CTIMEOUT) || \ - ((IT) == SDIO_IT_DTIMEOUT) || \ - ((IT) == SDIO_IT_TXUNDERR) || \ - ((IT) == SDIO_IT_RXOVERR) || \ - ((IT) == SDIO_IT_CMDREND) || \ - ((IT) == SDIO_IT_CMDSENT) || \ - ((IT) == SDIO_IT_DATAEND) || \ - ((IT) == SDIO_IT_STBITERR) || \ - ((IT) == SDIO_IT_DBCKEND) || \ - ((IT) == SDIO_IT_CMDACT) || \ - ((IT) == SDIO_IT_TXACT) || \ - ((IT) == SDIO_IT_RXACT) || \ - ((IT) == SDIO_IT_TXFIFOHE) || \ - ((IT) == SDIO_IT_RXFIFOHF) || \ - ((IT) == SDIO_IT_TXFIFOF) || \ - ((IT) == SDIO_IT_RXFIFOF) || \ - ((IT) == SDIO_IT_TXFIFOE) || \ - ((IT) == SDIO_IT_RXFIFOE) || \ - ((IT) == SDIO_IT_TXDAVL) || \ - ((IT) == SDIO_IT_RXDAVL) || \ - ((IT) == SDIO_IT_SDIOIT) || \ - ((IT) == SDIO_IT_CEATAEND)) - -#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00)) - -/** - * @} - */ - -/** @defgroup SDIO_Read_Wait_Mode - * @{ - */ - -#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) -#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) -#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \ - ((MODE) == SDIO_ReadWaitMode_DATA2)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Function used to set the SDIO configuration to the default reset state ****/ -void SDIO_DeInit(void); - -/* Initialization and Configuration functions *********************************/ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); -void SDIO_ClockCmd(FunctionalState NewState); -void SDIO_SetPowerState(uint32_t SDIO_PowerState); -uint32_t SDIO_GetPowerState(void); - -/* Command path state machine (CPSM) management functions *********************/ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); -uint8_t SDIO_GetCommandResponse(void); -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); - -/* Data path state machine (DPSM) management functions ************************/ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); -uint32_t SDIO_GetDataCounter(void); -uint32_t SDIO_ReadData(void); -void SDIO_WriteData(uint32_t Data); -uint32_t SDIO_GetFIFOCount(void); - -/* SDIO IO Cards mode management functions ************************************/ -void SDIO_StartSDIOReadWait(FunctionalState NewState); -void SDIO_StopSDIOReadWait(FunctionalState NewState); -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); -void SDIO_SetSDIOOperation(FunctionalState NewState); -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); - -/* CE-ATA mode management functions *******************************************/ -void SDIO_CommandCompletionCmd(FunctionalState NewState); -void SDIO_CEATAITCmd(FunctionalState NewState); -void SDIO_SendCEATACmd(FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void SDIO_DMACmd(FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); -void SDIO_ClearFlag(uint32_t SDIO_FLAG); -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); -void SDIO_ClearITPendingBit(uint32_t SDIO_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_SDIO_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h deleted file mode 100644 index a1436f658..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h +++ /dev/null @@ -1,549 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the SPI - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SPI_H -#define __STM32F4xx_SPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief SPI Init structure definition - */ - -typedef struct -{ - uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_data_direction */ - - uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_mode */ - - uint16_t SPI_DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_data_size */ - - uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ -}SPI_InitTypeDef; - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - - uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ -}I2S_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants - * @{ - */ - -#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6)) - -#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \ - ((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == SPI4) || \ - ((PERIPH) == SPI5) || \ - ((PERIPH) == SPI6) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3)) - -#define IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || \ - ((PERIPH) == SPI3) || \ - ((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - -#define IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || \ - ((PERIPH) == I2S3ext)) - - -/** @defgroup SPI_data_direction - * @{ - */ - -#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) -#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) -#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) -#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ - ((MODE) == SPI_Direction_2Lines_RxOnly) || \ - ((MODE) == SPI_Direction_1Line_Rx) || \ - ((MODE) == SPI_Direction_1Line_Tx)) -/** - * @} - */ - -/** @defgroup SPI_mode - * @{ - */ - -#define SPI_Mode_Master ((uint16_t)0x0104) -#define SPI_Mode_Slave ((uint16_t)0x0000) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ - ((MODE) == SPI_Mode_Slave)) -/** - * @} - */ - -/** @defgroup SPI_data_size - * @{ - */ - -#define SPI_DataSize_16b ((uint16_t)0x0800) -#define SPI_DataSize_8b ((uint16_t)0x0000) -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ - ((DATASIZE) == SPI_DataSize_8b)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity - * @{ - */ - -#define SPI_CPOL_Low ((uint16_t)0x0000) -#define SPI_CPOL_High ((uint16_t)0x0002) -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ - ((CPOL) == SPI_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase - * @{ - */ - -#define SPI_CPHA_1Edge ((uint16_t)0x0000) -#define SPI_CPHA_2Edge ((uint16_t)0x0001) -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ - ((CPHA) == SPI_CPHA_2Edge)) -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management - * @{ - */ - -#define SPI_NSS_Soft ((uint16_t)0x0200) -#define SPI_NSS_Hard ((uint16_t)0x0000) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ - ((NSS) == SPI_NSS_Hard)) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler - * @{ - */ - -#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) -#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) -#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) -#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) -#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) -#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) -#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) -#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ - ((PRESCALER) == SPI_BaudRatePrescaler_256)) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission - * @{ - */ - -#define SPI_FirstBit_MSB ((uint16_t)0x0000) -#define SPI_FirstBit_LSB ((uint16_t)0x0080) -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ - ((BIT) == SPI_FirstBit_LSB)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Mode - * @{ - */ - -#define I2S_Mode_SlaveTx ((uint16_t)0x0000) -#define I2S_Mode_SlaveRx ((uint16_t)0x0100) -#define I2S_Mode_MasterTx ((uint16_t)0x0200) -#define I2S_Mode_MasterRx ((uint16_t)0x0300) -#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ - ((MODE) == I2S_Mode_SlaveRx) || \ - ((MODE) == I2S_Mode_MasterTx)|| \ - ((MODE) == I2S_Mode_MasterRx)) -/** - * @} - */ - - -/** @defgroup SPI_I2S_Standard - * @{ - */ - -#define I2S_Standard_Phillips ((uint16_t)0x0000) -#define I2S_Standard_MSB ((uint16_t)0x0010) -#define I2S_Standard_LSB ((uint16_t)0x0020) -#define I2S_Standard_PCMShort ((uint16_t)0x0030) -#define I2S_Standard_PCMLong ((uint16_t)0x00B0) -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ - ((STANDARD) == I2S_Standard_MSB) || \ - ((STANDARD) == I2S_Standard_LSB) || \ - ((STANDARD) == I2S_Standard_PCMShort) || \ - ((STANDARD) == I2S_Standard_PCMLong)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Data_Format - * @{ - */ - -#define I2S_DataFormat_16b ((uint16_t)0x0000) -#define I2S_DataFormat_16bextended ((uint16_t)0x0001) -#define I2S_DataFormat_24b ((uint16_t)0x0003) -#define I2S_DataFormat_32b ((uint16_t)0x0005) -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ - ((FORMAT) == I2S_DataFormat_16bextended) || \ - ((FORMAT) == I2S_DataFormat_24b) || \ - ((FORMAT) == I2S_DataFormat_32b)) -/** - * @} - */ - -/** @defgroup SPI_I2S_MCLK_Output - * @{ - */ - -#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) -#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ - ((OUTPUT) == I2S_MCLKOutput_Disable)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Audio_Frequency - * @{ - */ - -#define I2S_AudioFreq_192k ((uint32_t)192000) -#define I2S_AudioFreq_96k ((uint32_t)96000) -#define I2S_AudioFreq_48k ((uint32_t)48000) -#define I2S_AudioFreq_44k ((uint32_t)44100) -#define I2S_AudioFreq_32k ((uint32_t)32000) -#define I2S_AudioFreq_22k ((uint32_t)22050) -#define I2S_AudioFreq_16k ((uint32_t)16000) -#define I2S_AudioFreq_11k ((uint32_t)11025) -#define I2S_AudioFreq_8k ((uint32_t)8000) -#define I2S_AudioFreq_Default ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ - ((FREQ) <= I2S_AudioFreq_192k)) || \ - ((FREQ) == I2S_AudioFreq_Default)) -/** - * @} - */ - -/** @defgroup SPI_I2S_Clock_Polarity - * @{ - */ - -#define I2S_CPOL_Low ((uint16_t)0x0000) -#define I2S_CPOL_High ((uint16_t)0x0008) -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ - ((CPOL) == I2S_CPOL_High)) -/** - * @} - */ - -/** @defgroup SPI_I2S_DMA_transfer_requests - * @{ - */ - -#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) -#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) -#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) -/** - * @} - */ - -/** @defgroup SPI_NSS_internal_software_management - * @{ - */ - -#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) -#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) -#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ - ((INTERNAL) == SPI_NSSInternalSoft_Reset)) -/** - * @} - */ - -/** @defgroup SPI_CRC_Transmit_Receive - * @{ - */ - -#define SPI_CRC_Tx ((uint8_t)0x00) -#define SPI_CRC_Rx ((uint8_t)0x01) -#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) -/** - * @} - */ - -/** @defgroup SPI_direction_transmit_receive - * @{ - */ - -#define SPI_Direction_Rx ((uint16_t)0xBFFF) -#define SPI_Direction_Tx ((uint16_t)0x4000) -#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ - ((DIRECTION) == SPI_Direction_Tx)) -/** - * @} - */ - -/** @defgroup SPI_I2S_interrupts_definition - * @{ - */ - -#define SPI_I2S_IT_TXE ((uint8_t)0x71) -#define SPI_I2S_IT_RXNE ((uint8_t)0x60) -#define SPI_I2S_IT_ERR ((uint8_t)0x50) -#define I2S_IT_UDR ((uint8_t)0x53) -#define SPI_I2S_IT_TIFRFE ((uint8_t)0x58) - -#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_I2S_IT_RXNE) || \ - ((IT) == SPI_I2S_IT_ERR)) - -#define SPI_I2S_IT_OVR ((uint8_t)0x56) -#define SPI_IT_MODF ((uint8_t)0x55) -#define SPI_IT_CRCERR ((uint8_t)0x54) - -#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) - -#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \ - ((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \ - ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\ - ((IT) == SPI_I2S_IT_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_I2S_flags_definition - * @{ - */ - -#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) -#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) -#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) -#define I2S_FLAG_UDR ((uint16_t)0x0008) -#define SPI_FLAG_CRCERR ((uint16_t)0x0010) -#define SPI_FLAG_MODF ((uint16_t)0x0020) -#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) -#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) -#define SPI_I2S_FLAG_TIFRFE ((uint16_t)0x0100) - -#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) -#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ - ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ - ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ - ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \ - ((FLAG) == SPI_I2S_FLAG_TIFRFE)) -/** - * @} - */ - -/** @defgroup SPI_CRC_polynomial - * @{ - */ - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) -/** - * @} - */ - -/** @defgroup SPI_I2S_Legacy - * @{ - */ - -#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx -#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx -#define SPI_IT_TXE SPI_I2S_IT_TXE -#define SPI_IT_RXNE SPI_I2S_IT_RXNE -#define SPI_IT_ERR SPI_I2S_IT_ERR -#define SPI_IT_OVR SPI_I2S_IT_OVR -#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE -#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE -#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR -#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY -#define SPI_DeInit SPI_I2S_DeInit -#define SPI_ITConfig SPI_I2S_ITConfig -#define SPI_DMACmd SPI_I2S_DMACmd -#define SPI_SendData SPI_I2S_SendData -#define SPI_ReceiveData SPI_I2S_ReceiveData -#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus -#define SPI_ClearFlag SPI_I2S_ClearFlag -#define SPI_GetITStatus SPI_I2S_GetITStatus -#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the SPI configuration to the default reset state *****/ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx); - -/* Initialization and Configuration functions *********************************/ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); - -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct); - -/* Data transfers functions ***************************************************/ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); - -/* Hardware CRC Calculation functions *****************************************/ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); -void SPI_TransmitCRC(SPI_TypeDef* SPIx); -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); - -/* DMA transfers management functions *****************************************/ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SPI_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h deleted file mode 100644 index dbbe87b3a..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h +++ /dev/null @@ -1,350 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the SYSCFG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_SYSCFG_H -#define __STM32F4xx_SYSCFG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup SYSCFG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSCFG_Exported_Constants - * @{ - */ -#if defined(STM32F413_423xx) -/** @defgroup BITSTREAM_CLOCK Bit Stream clock source selection - * @{ - */ -#define BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL -#define BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000 -/** - * @} - */ - -/** @defgroup MCHDLY_CLOCK MCHDLY Clock enable - * @{ - */ -#define MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN -#define MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN -/** - * @} - */ - -/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection - * @{ - */ -#define DFSDM2_CKIN_PAD (uint32_t)0x00000000 -#define DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG -#define DFSDM1_CKIN_PAD (uint32_t)0x00000000 -#define DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG -/** - * @} - */ - -/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection - * @{ - */ -#define DFSDM2_CKOUT_DFSDM2 (uint32_t)0x00000000 -#define DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL -#define DFSDM1_CKOUT_DFSDM1 (uint32_t)0x00000000U -#define DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL -/** - * @} - */ - -/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0 - * @{ - */ -#define DATAIN0_DFSDM2_PAD (uint32_t)0x00000000 -#define DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL -#define DATAIN0_DFSDM1_PAD (uint32_t)0x00000000 -#define DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL -/** - * @} - */ - -/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2 - * @{ - */ -#define DATAIN2_DFSDM2_PAD (uint32_t)0x00000000 -#define DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL -#define DATAIN2_DFSDM1_PAD (uint32_t)0x00000000 -#define DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL -/** - * @} - */ - -/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 - * @{ - */ -#define DATAIN4_DFSDM2_PAD (uint32_t)0x00000000 -#define DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL -/** - * @} - */ - -/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 - * @{ - */ -#define DATAIN6_DFSDM2_PAD (uint32_t)0x00000000 -#define DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL -/** - * @} - */ - -/** @defgroup DFSDM_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN - * @{ - */ -#define DFSDM1_CLKIN0_TIM4OC2 (uint32_t)0x00000000 -#define DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL -#define DFSDM1_CLKIN1_TIM4OC1 (uint32_t)0x00000000 -#define DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL -/** - * @} - */ - -/** @defgroup DFSDM_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN - * @{ - */ -#define DFSDM2_CLKIN0_TIM3OC4 (uint32_t)0x00000000 -#define DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL -#define DFSDM2_CLKIN1_TIM3OC3 (uint32_t)0x00000000 -#define DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL -#define DFSDM2_CLKIN2_TIM3OC2 (uint32_t)0x00000000 -#define DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL -#define DFSDM2_CLKIN3_TIM3OC1 (uint32_t)0x00000000 -#define DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL -/** - * @} - */ -#endif /* STM32F413_423xx */ - -/** @defgroup SYSCFG_EXTI_Port_Sources - * @{ - */ -#define EXTI_PortSourceGPIOA ((uint8_t)0x00) -#define EXTI_PortSourceGPIOB ((uint8_t)0x01) -#define EXTI_PortSourceGPIOC ((uint8_t)0x02) -#define EXTI_PortSourceGPIOD ((uint8_t)0x03) -#define EXTI_PortSourceGPIOE ((uint8_t)0x04) -#define EXTI_PortSourceGPIOF ((uint8_t)0x05) -#define EXTI_PortSourceGPIOG ((uint8_t)0x06) -#define EXTI_PortSourceGPIOH ((uint8_t)0x07) -#define EXTI_PortSourceGPIOI ((uint8_t)0x08) -#define EXTI_PortSourceGPIOJ ((uint8_t)0x09) -#define EXTI_PortSourceGPIOK ((uint8_t)0x0A) - -#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOI) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || \ - ((PORTSOURCE) == EXTI_PortSourceGPIOK)) - -/** - * @} - */ - - -/** @defgroup SYSCFG_EXTI_Pin_Sources - * @{ - */ -#define EXTI_PinSource0 ((uint8_t)0x00) -#define EXTI_PinSource1 ((uint8_t)0x01) -#define EXTI_PinSource2 ((uint8_t)0x02) -#define EXTI_PinSource3 ((uint8_t)0x03) -#define EXTI_PinSource4 ((uint8_t)0x04) -#define EXTI_PinSource5 ((uint8_t)0x05) -#define EXTI_PinSource6 ((uint8_t)0x06) -#define EXTI_PinSource7 ((uint8_t)0x07) -#define EXTI_PinSource8 ((uint8_t)0x08) -#define EXTI_PinSource9 ((uint8_t)0x09) -#define EXTI_PinSource10 ((uint8_t)0x0A) -#define EXTI_PinSource11 ((uint8_t)0x0B) -#define EXTI_PinSource12 ((uint8_t)0x0C) -#define EXTI_PinSource13 ((uint8_t)0x0D) -#define EXTI_PinSource14 ((uint8_t)0x0E) -#define EXTI_PinSource15 ((uint8_t)0x0F) -#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ - ((PINSOURCE) == EXTI_PinSource1) || \ - ((PINSOURCE) == EXTI_PinSource2) || \ - ((PINSOURCE) == EXTI_PinSource3) || \ - ((PINSOURCE) == EXTI_PinSource4) || \ - ((PINSOURCE) == EXTI_PinSource5) || \ - ((PINSOURCE) == EXTI_PinSource6) || \ - ((PINSOURCE) == EXTI_PinSource7) || \ - ((PINSOURCE) == EXTI_PinSource8) || \ - ((PINSOURCE) == EXTI_PinSource9) || \ - ((PINSOURCE) == EXTI_PinSource10) || \ - ((PINSOURCE) == EXTI_PinSource11) || \ - ((PINSOURCE) == EXTI_PinSource12) || \ - ((PINSOURCE) == EXTI_PinSource13) || \ - ((PINSOURCE) == EXTI_PinSource14) || \ - ((PINSOURCE) == EXTI_PinSource15)) -/** - * @} - */ - - -/** @defgroup SYSCFG_Memory_Remap_Config - * @{ - */ -#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00) -#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01) -#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03) -#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04) - -#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02) -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F446xx) || defined (STM32F469_479xx) -#define SYSCFG_MemoryRemap_ExtMEM ((uint8_t)0x02) -#endif /* STM32F446xx || STM32F469_479xx */ - -#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FSMC)) -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */ - -#if defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM)) -#endif /* STM32F401xx || STM32F410xx || STM32F411xE */ - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_FMC)) -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F446xx) || defined (STM32F469_479xx) -#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ - ((REMAP) == SYSCFG_MemoryRemap_ExtMEM) || \ - ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \ - ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ - ((REMAP) == SYSCFG_MemoryRemap_SDRAM)) -#endif /* STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVDL -#define SYSCFG_Break_HardFault SYSCFG_CFGR2_CLL - -#define IS_SYSCFG_LOCK_CONFIG(BREAK) (((BREAK) == SYSCFG_Break_PVD) || \ - ((BREAK) == SYSCFG_Break_HardFault)) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ -/** - * @} - */ - - -/** @defgroup SYSCFG_ETHERNET_Media_Interface - * @{ - */ -#define SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000) -#define SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001) - -#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \ - ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -void SYSCFG_DeInit(void); -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap); -void SYSCFG_MemorySwappingBank(FunctionalState NewState); -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); -void SYSCFG_CompensationCellCmd(FunctionalState NewState); -FlagStatus SYSCFG_GetCompensationCellStatus(void); -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ -#if defined(STM32F413_423xx) -void DFSDM_BitstreamClock_SourceSelection(uint32_t source); -void DFSDM_DisableDelayClock(uint32_t MCHDLY); -void DFSDM_EnableDelayClock(uint32_t MCHDLY); -void DFSDM_ClockIn_SourceSelection(uint32_t source); -void DFSDM_ClockOut_SourceSelection(uint32_t source); -void DFSDM_DataIn0_SourceSelection(uint32_t source); -void DFSDM_DataIn2_SourceSelection(uint32_t source); -void DFSDM_DataIn4_SourceSelection(uint32_t source); -void DFSDM_DataIn6_SourceSelection(uint32_t source); -void DFSDM1_BitStreamClk_Config(uint32_t source); -void DFSDM2_BitStreamClk_Config(uint32_t source); -#endif /* STM32F413_423xx */ -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_SYSCFG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h deleted file mode 100644 index a6fe07d23..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h +++ /dev/null @@ -1,1150 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the TIM firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_TIM_H -#define __STM32F4xx_TIM_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief TIM Time Base Init structure definition - * @note This structure is used with all TIMx except for TIM6 and TIM7. - */ - -typedef struct -{ - uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between 0x0000 and 0xFFFF. */ - - uint16_t TIM_ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_Clock_Division_CKD */ - - uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_TimeBaseInitTypeDef; - -/** - * @brief TIM Output Compare Init structure definition - */ - -typedef struct -{ - uint16_t TIM_OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_State */ - - uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_Output_Compare_N_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between 0x0000 and 0xFFFF */ - - uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ - - uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for TIM1 and TIM8. */ -} TIM_OCInitTypeDef; - -/** - * @brief TIM Input Capture Init structure definition - */ - -typedef struct -{ - - uint16_t TIM_Channel; /*!< Specifies the TIM channel. - This parameter can be a value of @ref TIM_Channel */ - - uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint16_t TIM_ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between 0x0 and 0xF */ -} TIM_ICInitTypeDef; - -/** - * @brief BDTR structure definition - * @note This structure is used only with TIM1 and TIM8. - */ - -typedef struct -{ - - uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_Lock_level */ - - uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between 0x00 and 0xFF */ - - uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_Break_Polarity */ - - uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ -} TIM_BDTRInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_constants - * @{ - */ - -#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - (((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14))) -/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */ -#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM10) || \ - ((PERIPH) == TIM11) || \ - ((PERIPH) == TIM12) || \ - ((PERIPH) == TIM13) || \ - ((PERIPH) == TIM14)) - -/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */ -#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8) || \ - ((PERIPH) == TIM9) || \ - ((PERIPH) == TIM12)) -/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */ -#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM8)) -/* LIST4: TIM1 and TIM8 */ -#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM8)) -/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */ -#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ - ((PERIPH) == TIM2) || \ - ((PERIPH) == TIM3) || \ - ((PERIPH) == TIM4) || \ - ((PERIPH) == TIM5) || \ - ((PERIPH) == TIM6) || \ - ((PERIPH) == TIM7) || \ - ((PERIPH) == TIM8)) -/* LIST6: TIM2, TIM5 and TIM11 */ -#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \ - ((TIMx) == TIM5) || \ - ((TIMx) == TIM11)) - -/** @defgroup TIM_Output_Compare_and_PWM_modes - * @{ - */ - -#define TIM_OCMode_Timing ((uint16_t)0x0000) -#define TIM_OCMode_Active ((uint16_t)0x0010) -#define TIM_OCMode_Inactive ((uint16_t)0x0020) -#define TIM_OCMode_Toggle ((uint16_t)0x0030) -#define TIM_OCMode_PWM1 ((uint16_t)0x0060) -#define TIM_OCMode_PWM2 ((uint16_t)0x0070) -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2)) -#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ - ((MODE) == TIM_OCMode_Active) || \ - ((MODE) == TIM_OCMode_Inactive) || \ - ((MODE) == TIM_OCMode_Toggle)|| \ - ((MODE) == TIM_OCMode_PWM1) || \ - ((MODE) == TIM_OCMode_PWM2) || \ - ((MODE) == TIM_ForcedAction_Active) || \ - ((MODE) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode - * @{ - */ - -#define TIM_OPMode_Single ((uint16_t)0x0008) -#define TIM_OPMode_Repetitive ((uint16_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ - ((MODE) == TIM_OPMode_Repetitive)) -/** - * @} - */ - -/** @defgroup TIM_Channel - * @{ - */ - -#define TIM_Channel_1 ((uint16_t)0x0000) -#define TIM_Channel_2 ((uint16_t)0x0004) -#define TIM_Channel_3 ((uint16_t)0x0008) -#define TIM_Channel_4 ((uint16_t)0x000C) - -#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3) || \ - ((CHANNEL) == TIM_Channel_4)) - -#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2)) -#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ - ((CHANNEL) == TIM_Channel_2) || \ - ((CHANNEL) == TIM_Channel_3)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Division_CKD - * @{ - */ - -#define TIM_CKD_DIV1 ((uint16_t)0x0000) -#define TIM_CKD_DIV2 ((uint16_t)0x0100) -#define TIM_CKD_DIV4 ((uint16_t)0x0200) -#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ - ((DIV) == TIM_CKD_DIV2) || \ - ((DIV) == TIM_CKD_DIV4)) -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode - * @{ - */ - -#define TIM_CounterMode_Up ((uint16_t)0x0000) -#define TIM_CounterMode_Down ((uint16_t)0x0010) -#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) -#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) -#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ - ((MODE) == TIM_CounterMode_Down) || \ - ((MODE) == TIM_CounterMode_CenterAligned1) || \ - ((MODE) == TIM_CounterMode_CenterAligned2) || \ - ((MODE) == TIM_CounterMode_CenterAligned3)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity - * @{ - */ - -#define TIM_OCPolarity_High ((uint16_t)0x0000) -#define TIM_OCPolarity_Low ((uint16_t)0x0002) -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ - ((POLARITY) == TIM_OCPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity - * @{ - */ - -#define TIM_OCNPolarity_High ((uint16_t)0x0000) -#define TIM_OCNPolarity_Low ((uint16_t)0x0008) -#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ - ((POLARITY) == TIM_OCNPolarity_Low)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State - * @{ - */ - -#define TIM_OutputState_Disable ((uint16_t)0x0000) -#define TIM_OutputState_Enable ((uint16_t)0x0001) -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ - ((STATE) == TIM_OutputState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State - * @{ - */ - -#define TIM_OutputNState_Disable ((uint16_t)0x0000) -#define TIM_OutputNState_Enable ((uint16_t)0x0004) -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ - ((STATE) == TIM_OutputNState_Enable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_State - * @{ - */ - -#define TIM_CCx_Enable ((uint16_t)0x0001) -#define TIM_CCx_Disable ((uint16_t)0x0000) -#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ - ((CCX) == TIM_CCx_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Capture_Compare_N_State - * @{ - */ - -#define TIM_CCxN_Enable ((uint16_t)0x0004) -#define TIM_CCxN_Disable ((uint16_t)0x0000) -#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ - ((CCXN) == TIM_CCxN_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable - * @{ - */ - -#define TIM_Break_Enable ((uint16_t)0x1000) -#define TIM_Break_Disable ((uint16_t)0x0000) -#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ - ((STATE) == TIM_Break_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity - * @{ - */ - -#define TIM_BreakPolarity_Low ((uint16_t)0x0000) -#define TIM_BreakPolarity_High ((uint16_t)0x2000) -#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ - ((POLARITY) == TIM_BreakPolarity_High)) -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset - * @{ - */ - -#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) -#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ - ((STATE) == TIM_AutomaticOutput_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Lock_level - * @{ - */ - -#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) -#define TIM_LOCKLevel_1 ((uint16_t)0x0100) -#define TIM_LOCKLevel_2 ((uint16_t)0x0200) -#define TIM_LOCKLevel_3 ((uint16_t)0x0300) -#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ - ((LEVEL) == TIM_LOCKLevel_1) || \ - ((LEVEL) == TIM_LOCKLevel_2) || \ - ((LEVEL) == TIM_LOCKLevel_3)) -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state - * @{ - */ - -#define TIM_OSSIState_Enable ((uint16_t)0x0400) -#define TIM_OSSIState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ - ((STATE) == TIM_OSSIState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state - * @{ - */ - -#define TIM_OSSRState_Enable ((uint16_t)0x0800) -#define TIM_OSSRState_Disable ((uint16_t)0x0000) -#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ - ((STATE) == TIM_OSSRState_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State - * @{ - */ - -#define TIM_OCIdleState_Set ((uint16_t)0x0100) -#define TIM_OCIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ - ((STATE) == TIM_OCIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State - * @{ - */ - -#define TIM_OCNIdleState_Set ((uint16_t)0x0200) -#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) -#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ - ((STATE) == TIM_OCNIdleState_Reset)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity - * @{ - */ - -#define TIM_ICPolarity_Rising ((uint16_t)0x0000) -#define TIM_ICPolarity_Falling ((uint16_t)0x0002) -#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ - ((POLARITY) == TIM_ICPolarity_Falling)|| \ - ((POLARITY) == TIM_ICPolarity_BothEdge)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection - * @{ - */ - -#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively. */ -#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ - ((SELECTION) == TIM_ICSelection_IndirectTI) || \ - ((SELECTION) == TIM_ICSelection_TRC)) -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler - * @{ - */ - -#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ -#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ -#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ -#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_interrupt_sources - * @{ - */ - -#define TIM_IT_Update ((uint16_t)0x0001) -#define TIM_IT_CC1 ((uint16_t)0x0002) -#define TIM_IT_CC2 ((uint16_t)0x0004) -#define TIM_IT_CC3 ((uint16_t)0x0008) -#define TIM_IT_CC4 ((uint16_t)0x0010) -#define TIM_IT_COM ((uint16_t)0x0020) -#define TIM_IT_Trigger ((uint16_t)0x0040) -#define TIM_IT_Break ((uint16_t)0x0080) -#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_COM) || \ - ((IT) == TIM_IT_Trigger) || \ - ((IT) == TIM_IT_Break)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ - */ - -#define TIM_DMABase_CR1 ((uint16_t)0x0000) -#define TIM_DMABase_CR2 ((uint16_t)0x0001) -#define TIM_DMABase_SMCR ((uint16_t)0x0002) -#define TIM_DMABase_DIER ((uint16_t)0x0003) -#define TIM_DMABase_SR ((uint16_t)0x0004) -#define TIM_DMABase_EGR ((uint16_t)0x0005) -#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) -#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) -#define TIM_DMABase_CCER ((uint16_t)0x0008) -#define TIM_DMABase_CNT ((uint16_t)0x0009) -#define TIM_DMABase_PSC ((uint16_t)0x000A) -#define TIM_DMABase_ARR ((uint16_t)0x000B) -#define TIM_DMABase_RCR ((uint16_t)0x000C) -#define TIM_DMABase_CCR1 ((uint16_t)0x000D) -#define TIM_DMABase_CCR2 ((uint16_t)0x000E) -#define TIM_DMABase_CCR3 ((uint16_t)0x000F) -#define TIM_DMABase_CCR4 ((uint16_t)0x0010) -#define TIM_DMABase_BDTR ((uint16_t)0x0011) -#define TIM_DMABase_DCR ((uint16_t)0x0012) -#define TIM_DMABase_OR ((uint16_t)0x0013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_RCR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_BDTR) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length - * @{ - */ - -#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) -#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) -#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) -#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) -#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) -#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) -#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) -#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) -#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) -#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) -#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) -#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) -#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) -#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) -#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) -#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) -#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) -#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) -/** - * @} - */ - -/** @defgroup TIM_DMA_sources - * @{ - */ - -#define TIM_DMA_Update ((uint16_t)0x0100) -#define TIM_DMA_CC1 ((uint16_t)0x0200) -#define TIM_DMA_CC2 ((uint16_t)0x0400) -#define TIM_DMA_CC3 ((uint16_t)0x0800) -#define TIM_DMA_CC4 ((uint16_t)0x1000) -#define TIM_DMA_COM ((uint16_t)0x2000) -#define TIM_DMA_Trigger ((uint16_t)0x4000) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Prescaler - * @{ - */ - -#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) -#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) -#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) -#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) -#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ - ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Internal_Trigger_Selection - * @{ - */ - -#define TIM_TS_ITR0 ((uint16_t)0x0000) -#define TIM_TS_ITR1 ((uint16_t)0x0010) -#define TIM_TS_ITR2 ((uint16_t)0x0020) -#define TIM_TS_ITR3 ((uint16_t)0x0030) -#define TIM_TS_TI1F_ED ((uint16_t)0x0040) -#define TIM_TS_TI1FP1 ((uint16_t)0x0050) -#define TIM_TS_TI2FP2 ((uint16_t)0x0060) -#define TIM_TS_ETRF ((uint16_t)0x0070) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -/** - * @} - */ - -/** @defgroup TIM_TIx_External_Clock_Source - * @{ - */ - -#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) -#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) -#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) - -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Polarity - * @{ - */ -#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) -#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) -#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ - ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) -/** - * @} - */ - -/** @defgroup TIM_Prescaler_Reload_Mode - * @{ - */ - -#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) -#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) -#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ - ((RELOAD) == TIM_PSCReloadMode_Immediate)) -/** - * @} - */ - -/** @defgroup TIM_Forced_Action - * @{ - */ - -#define TIM_ForcedAction_Active ((uint16_t)0x0050) -#define TIM_ForcedAction_InActive ((uint16_t)0x0040) -#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ - ((ACTION) == TIM_ForcedAction_InActive)) -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode - * @{ - */ - -#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) -#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) -#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ - ((MODE) == TIM_EncoderMode_TI2) || \ - ((MODE) == TIM_EncoderMode_TI12)) -/** - * @} - */ - - -/** @defgroup TIM_Event_Source - * @{ - */ - -#define TIM_EventSource_Update ((uint16_t)0x0001) -#define TIM_EventSource_CC1 ((uint16_t)0x0002) -#define TIM_EventSource_CC2 ((uint16_t)0x0004) -#define TIM_EventSource_CC3 ((uint16_t)0x0008) -#define TIM_EventSource_CC4 ((uint16_t)0x0010) -#define TIM_EventSource_COM ((uint16_t)0x0020) -#define TIM_EventSource_Trigger ((uint16_t)0x0040) -#define TIM_EventSource_Break ((uint16_t)0x0080) -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) - -/** - * @} - */ - -/** @defgroup TIM_Update_Source - * @{ - */ - -#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow - or the setting of UG bit, or an update generation - through the slave mode controller. */ -#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ -#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ - ((SOURCE) == TIM_UpdateSource_Regular)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Preload_State - * @{ - */ - -#define TIM_OCPreload_Enable ((uint16_t)0x0008) -#define TIM_OCPreload_Disable ((uint16_t)0x0000) -#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ - ((STATE) == TIM_OCPreload_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Fast_State - * @{ - */ - -#define TIM_OCFast_Enable ((uint16_t)0x0004) -#define TIM_OCFast_Disable ((uint16_t)0x0000) -#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ - ((STATE) == TIM_OCFast_Disable)) - -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Clear_State - * @{ - */ - -#define TIM_OCClear_Enable ((uint16_t)0x0080) -#define TIM_OCClear_Disable ((uint16_t)0x0000) -#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ - ((STATE) == TIM_OCClear_Disable)) -/** - * @} - */ - -/** @defgroup TIM_Trigger_Output_Source - * @{ - */ - -#define TIM_TRGOSource_Reset ((uint16_t)0x0000) -#define TIM_TRGOSource_Enable ((uint16_t)0x0010) -#define TIM_TRGOSource_Update ((uint16_t)0x0020) -#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) -#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) -#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) -#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) -#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ - ((SOURCE) == TIM_TRGOSource_Enable) || \ - ((SOURCE) == TIM_TRGOSource_Update) || \ - ((SOURCE) == TIM_TRGOSource_OC1) || \ - ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ - ((SOURCE) == TIM_TRGOSource_OC4Ref)) -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode - * @{ - */ - -#define TIM_SlaveMode_Reset ((uint16_t)0x0004) -#define TIM_SlaveMode_Gated ((uint16_t)0x0005) -#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) -#define TIM_SlaveMode_External1 ((uint16_t)0x0007) -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ - ((MODE) == TIM_SlaveMode_Gated) || \ - ((MODE) == TIM_SlaveMode_Trigger) || \ - ((MODE) == TIM_SlaveMode_External1)) -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode - * @{ - */ - -#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) -#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ - ((STATE) == TIM_MasterSlaveMode_Disable)) -/** - * @} - */ -/** @defgroup TIM_Remap - * @{ - */ - -#define TIM2_TIM8_TRGO ((uint16_t)0x0000) -#define TIM2_ETH_PTP ((uint16_t)0x0400) -#define TIM2_USBFS_SOF ((uint16_t)0x0800) -#define TIM2_USBHS_SOF ((uint16_t)0x0C00) - -#define TIM5_GPIO ((uint16_t)0x0000) -#define TIM5_LSI ((uint16_t)0x0040) -#define TIM5_LSE ((uint16_t)0x0080) -#define TIM5_RTC ((uint16_t)0x00C0) - -#define TIM11_GPIO ((uint16_t)0x0000) -#define TIM11_HSE ((uint16_t)0x0002) - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\ - ((TIM_REMAP) == TIM2_ETH_PTP)||\ - ((TIM_REMAP) == TIM2_USBFS_SOF)||\ - ((TIM_REMAP) == TIM2_USBHS_SOF)||\ - ((TIM_REMAP) == TIM5_GPIO)||\ - ((TIM_REMAP) == TIM5_LSI)||\ - ((TIM_REMAP) == TIM5_LSE)||\ - ((TIM_REMAP) == TIM5_RTC)||\ - ((TIM_REMAP) == TIM11_GPIO)||\ - ((TIM_REMAP) == TIM11_HSE)) - -/** - * @} - */ -/** @defgroup TIM_Flags - * @{ - */ - -#define TIM_FLAG_Update ((uint16_t)0x0001) -#define TIM_FLAG_CC1 ((uint16_t)0x0002) -#define TIM_FLAG_CC2 ((uint16_t)0x0004) -#define TIM_FLAG_CC3 ((uint16_t)0x0008) -#define TIM_FLAG_CC4 ((uint16_t)0x0010) -#define TIM_FLAG_COM ((uint16_t)0x0020) -#define TIM_FLAG_Trigger ((uint16_t)0x0040) -#define TIM_FLAG_Break ((uint16_t)0x0080) -#define TIM_FLAG_CC1OF ((uint16_t)0x0200) -#define TIM_FLAG_CC2OF ((uint16_t)0x0400) -#define TIM_FLAG_CC3OF ((uint16_t)0x0800) -#define TIM_FLAG_CC4OF ((uint16_t)0x1000) -#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_COM) || \ - ((FLAG) == TIM_FLAG_Trigger) || \ - ((FLAG) == TIM_FLAG_Break) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) - -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value - * @{ - */ - -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_External_Trigger_Filter - * @{ - */ - -#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) -/** - * @} - */ - -/** @defgroup TIM_Legacy - * @{ - */ - -#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer -#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers -#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers -#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers -#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers -#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers -#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers -#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers -#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers -#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers -#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers -#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers -#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers -#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers -#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers -#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers -#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers -#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* TimeBase management ********************************************************/ -void TIM_DeInit(TIM_TypeDef* TIMx); -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Output Compare management **************************************************/ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); - -/* Input Capture management ***************************************************/ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); - -/* Advanced-control timers (TIM1 and TIM8) specific features ******************/ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Interrupts, DMA and flags management ***************************************/ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Clocks management **********************************************************/ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx); -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter); -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); - -/* Synchronization management *************************************************/ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - -/* Specific interface management **********************************************/ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); - -/* Specific remapping management **********************************************/ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap); - -#ifdef __cplusplus -} -#endif - -#endif /*__STM32F4xx_TIM_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h deleted file mode 100644 index ca341a82b..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h +++ /dev/null @@ -1,433 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the USART - * firmware library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_USART_H -#define __STM32F4xx_USART_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief USART Init Structure definition - */ - -typedef struct -{ - uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. - The baud rate is computed using the following formula: - - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate))) - - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 - Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */ - - uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_Word_Length */ - - uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits */ - - uint16_t USART_Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint16_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode */ - - uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref USART_Hardware_Flow_Control */ -} USART_InitTypeDef; - -/** - * @brief USART Clock Init Structure definition - */ - -typedef struct -{ - - uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_Clock */ - - uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity */ - - uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase */ - - uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit */ -} USART_ClockInitTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Constants - * @{ - */ - -#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == UART4) || \ - ((PERIPH) == UART5) || \ - ((PERIPH) == USART6) || \ - ((PERIPH) == UART7) || \ - ((PERIPH) == UART8) || \ - ((PERIPH) == UART9) || \ - ((PERIPH) == UART10)) - -#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \ - ((PERIPH) == USART2) || \ - ((PERIPH) == USART3) || \ - ((PERIPH) == USART6)) - -/** @defgroup USART_Word_Length - * @{ - */ - -#define USART_WordLength_8b ((uint16_t)0x0000) -#define USART_WordLength_9b ((uint16_t)0x1000) - -#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ - ((LENGTH) == USART_WordLength_9b)) -/** - * @} - */ - -/** @defgroup USART_Stop_Bits - * @{ - */ - -#define USART_StopBits_1 ((uint16_t)0x0000) -#define USART_StopBits_0_5 ((uint16_t)0x1000) -#define USART_StopBits_2 ((uint16_t)0x2000) -#define USART_StopBits_1_5 ((uint16_t)0x3000) -#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ - ((STOPBITS) == USART_StopBits_0_5) || \ - ((STOPBITS) == USART_StopBits_2) || \ - ((STOPBITS) == USART_StopBits_1_5)) -/** - * @} - */ - -/** @defgroup USART_Parity - * @{ - */ - -#define USART_Parity_No ((uint16_t)0x0000) -#define USART_Parity_Even ((uint16_t)0x0400) -#define USART_Parity_Odd ((uint16_t)0x0600) -#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ - ((PARITY) == USART_Parity_Even) || \ - ((PARITY) == USART_Parity_Odd)) -/** - * @} - */ - -/** @defgroup USART_Mode - * @{ - */ - -#define USART_Mode_Rx ((uint16_t)0x0004) -#define USART_Mode_Tx ((uint16_t)0x0008) -#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) -/** - * @} - */ - -/** @defgroup USART_Hardware_Flow_Control - * @{ - */ -#define USART_HardwareFlowControl_None ((uint16_t)0x0000) -#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) -#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) -#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) -#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ - (((CONTROL) == USART_HardwareFlowControl_None) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS) || \ - ((CONTROL) == USART_HardwareFlowControl_CTS) || \ - ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) -/** - * @} - */ - -/** @defgroup USART_Clock - * @{ - */ -#define USART_Clock_Disable ((uint16_t)0x0000) -#define USART_Clock_Enable ((uint16_t)0x0800) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ - ((CLOCK) == USART_Clock_Enable)) -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity - * @{ - */ - -#define USART_CPOL_Low ((uint16_t)0x0000) -#define USART_CPOL_High ((uint16_t)0x0400) -#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) - -/** - * @} - */ - -/** @defgroup USART_Clock_Phase - * @{ - */ - -#define USART_CPHA_1Edge ((uint16_t)0x0000) -#define USART_CPHA_2Edge ((uint16_t)0x0200) -#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) - -/** - * @} - */ - -/** @defgroup USART_Last_Bit - * @{ - */ - -#define USART_LastBit_Disable ((uint16_t)0x0000) -#define USART_LastBit_Enable ((uint16_t)0x0100) -#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ - ((LASTBIT) == USART_LastBit_Enable)) -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition - * @{ - */ - -#define USART_IT_PE ((uint16_t)0x0028) -#define USART_IT_TXE ((uint16_t)0x0727) -#define USART_IT_TC ((uint16_t)0x0626) -#define USART_IT_RXNE ((uint16_t)0x0525) -#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */ -#define USART_IT_IDLE ((uint16_t)0x0424) -#define USART_IT_LBD ((uint16_t)0x0846) -#define USART_IT_CTS ((uint16_t)0x096A) -#define USART_IT_ERR ((uint16_t)0x0060) -#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */ -#define USART_IT_NE ((uint16_t)0x0260) -#define USART_IT_FE ((uint16_t)0x0160) - -/** @defgroup USART_Legacy - * @{ - */ -#define USART_IT_ORE USART_IT_ORE_ER -/** - * @} - */ - -#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) -#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ - ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ - ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ - ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || \ - ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) -#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ - ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) -/** - * @} - */ - -/** @defgroup USART_DMA_Requests - * @{ - */ - -#define USART_DMAReq_Tx ((uint16_t)0x0080) -#define USART_DMAReq_Rx ((uint16_t)0x0040) -#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) - -/** - * @} - */ - -/** @defgroup USART_WakeUp_methods - * @{ - */ - -#define USART_WakeUp_IdleLine ((uint16_t)0x0000) -#define USART_WakeUp_AddressMark ((uint16_t)0x0800) -#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ - ((WAKEUP) == USART_WakeUp_AddressMark)) -/** - * @} - */ - -/** @defgroup USART_LIN_Break_Detection_Length - * @{ - */ - -#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) -#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) -#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ - (((LENGTH) == USART_LINBreakDetectLength_10b) || \ - ((LENGTH) == USART_LINBreakDetectLength_11b)) -/** - * @} - */ - -/** @defgroup USART_IrDA_Low_Power - * @{ - */ - -#define USART_IrDAMode_LowPower ((uint16_t)0x0004) -#define USART_IrDAMode_Normal ((uint16_t)0x0000) -#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ - ((MODE) == USART_IrDAMode_Normal)) -/** - * @} - */ - -/** @defgroup USART_Flags - * @{ - */ - -#define USART_FLAG_CTS ((uint16_t)0x0200) -#define USART_FLAG_LBD ((uint16_t)0x0100) -#define USART_FLAG_TXE ((uint16_t)0x0080) -#define USART_FLAG_TC ((uint16_t)0x0040) -#define USART_FLAG_RXNE ((uint16_t)0x0020) -#define USART_FLAG_IDLE ((uint16_t)0x0010) -#define USART_FLAG_ORE ((uint16_t)0x0008) -#define USART_FLAG_NE ((uint16_t)0x0004) -#define USART_FLAG_FE ((uint16_t)0x0002) -#define USART_FLAG_PE ((uint16_t)0x0001) -#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ - ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ - ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ - ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ - ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) - -#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) - -#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001)) -#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) -#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the USART configuration to the default reset state ***/ -void USART_DeInit(USART_TypeDef* USARTx); - -/* Initialization and Configuration functions *********************************/ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); -void USART_StructInit(USART_InitTypeDef* USART_InitStruct); -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Data transfers functions ***************************************************/ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); -uint16_t USART_ReceiveData(USART_TypeDef* USARTx); - -/* Multi-Processor Communication functions ************************************/ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* LIN mode functions *********************************************************/ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SendBreak(USART_TypeDef* USARTx); - -/* Half-duplex mode function **************************************************/ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* Smartcard mode functions ***************************************************/ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); - -/* IrDA mode functions ********************************************************/ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); - -/* DMA transfers management functions *****************************************/ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -/* Interrupts and flags management functions **********************************/ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_USART_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h deleted file mode 100644 index 6a7cf1b13..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h +++ /dev/null @@ -1,111 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.h - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file contains all the functions prototypes for the WWDG firmware - * library. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_WWDG_H -#define __STM32F4xx_WWDG_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants - * @{ - */ - -/** @defgroup WWDG_Prescaler - * @{ - */ - -#define WWDG_Prescaler_1 ((uint32_t)0x00000000) -#define WWDG_Prescaler_2 ((uint32_t)0x00000080) -#define WWDG_Prescaler_4 ((uint32_t)0x00000100) -#define WWDG_Prescaler_8 ((uint32_t)0x00000180) -#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ - ((PRESCALER) == WWDG_Prescaler_2) || \ - ((PRESCALER) == WWDG_Prescaler_4) || \ - ((PRESCALER) == WWDG_Prescaler_8)) -#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) -#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/* Function used to set the WWDG configuration to the default reset state ****/ -void WWDG_DeInit(void); - -/* Prescaler, Refresh window and Counter configuration functions **************/ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); -void WWDG_SetWindowValue(uint8_t WindowValue); -void WWDG_EnableIT(void); -void WWDG_SetCounter(uint8_t Counter); - -/* WWDG activation function ***************************************************/ -void WWDG_Enable(uint8_t Counter); - -/* Interrupts and flags management functions **********************************/ -FlagStatus WWDG_GetFlagStatus(void); -void WWDG_ClearFlag(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F4xx_WWDG_H */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c deleted file mode 100644 index 7f905418e..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c +++ /dev/null @@ -1,249 +0,0 @@ -/** - ****************************************************************************** - * @file misc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides all the miscellaneous firmware functions (add-on - * to CMSIS functions). - * - * @verbatim - * - * =================================================================== - * How to configure Interrupts using driver - * =================================================================== - * - * This section provide functions allowing to configure the NVIC interrupts (IRQ). - * The Cortex-M4 exceptions are managed by CMSIS functions. - * - * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig() - * function according to the following table. - - * The table below gives the allowed values of the pre-emption priority and subpriority according - * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function - * ========================================================================================================================== - * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description - * ========================================================================================================================== - * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority - * | | | 4 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority - * | | | 3 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - * | | | 2 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - * | | | 1 bits for subpriority - * -------------------------------------------------------------------------------------------------------------------------- - * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority - * | | | 0 bits for subpriority - * ========================================================================================================================== - * - * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init() - * - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * - * @note IRQ priority order (sorted by highest to lowest priority): - * - Lowest pre-emption priority - * - Lowest subpriority - * - Lowest hardware priority (IRQ number) - * - * @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "misc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup MISC - * @brief MISC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup MISC_Private_Functions - * @{ - */ - -/** - * @brief Configures the priority grouping: pre-emption priority and subpriority. - * @param NVIC_PriorityGroup: specifies the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority - * 4 bits for subpriority - * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority - * 3 bits for subpriority - * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority - * 2 bits for subpriority - * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority - * 1 bits for subpriority - * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ - SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; -} - -/** - * @brief Initializes the NVIC peripheral according to the specified - * parameters in the NVIC_InitStruct. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains - * the configuration information for the specified NVIC peripheral. - * @retval None - */ -void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) -{ - uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); - assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); - - if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) - { - /* Compute the Corresponding IRQ Priority --------------------------------*/ - tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; - tmppre = (0x4 - tmppriority); - tmpsub = tmpsub >> tmppriority; - - tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; - tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); - - tmppriority = tmppriority << 0x04; - - NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; - - /* Enable the Selected IRQ Channels --------------------------------------*/ - NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } - else - { - /* Disable the Selected IRQ Channels -------------------------------------*/ - NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = - (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); - } -} - -/** - * @brief Sets the vector table location and Offset. - * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. - * This parameter can be one of the following values: - * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. - * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. - * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. - * @retval None - */ -void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) -{ - /* Check the parameters */ - assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); - assert_param(IS_NVIC_OFFSET(Offset)); - - SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); -} - -/** - * @brief Selects the condition for the system to enter low power mode. - * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. - * This parameter can be one of the following values: - * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. - * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. - * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. - * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_NVIC_LP(LowPowerMode)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - SCB->SCR |= LowPowerMode; - } - else - { - SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); - } -} - -/** - * @brief Configures the SysTick clock source. - * @param SysTick_CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); - if (SysTick_CLKSource == SysTick_CLKSource_HCLK) - { - SysTick->CTRL |= SysTick_CLKSource_HCLK; - } - else - { - SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c deleted file mode 100644 index b292105fc..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c +++ /dev/null @@ -1,1745 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_adc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Convertor (ADC) peripheral: - * + Initialization and Configuration (in addition to ADC multi mode - * selection) - * + Analog Watchdog configuration - * + Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT - * management - * + Regular Channels Configuration - * + Regular Channels DMA Configuration - * + Injected channels Configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the ADC interface clock using - RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs using the following function: - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - (++) Configure these ADC pins in analog mode using GPIO_Init(); - - (#) Configure the ADC Prescaler, conversion resolution and data - alignment using the ADC_Init() function. - (#) Activate the ADC peripheral using ADC_Cmd() function. - - *** Regular channels group configuration *** - ============================================ - [..] - (+) To configure the ADC regular channels group features, use - ADC_Init() and ADC_RegularChannelConfig() functions. - (+) To activate the continuous mode, use the ADC_continuousModeCmd() - function. - (+) To configurate and activate the Discontinuous mode, use the - ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions. - (+) To read the ADC converted values, use the ADC_GetConversionValue() - function. - - *** Multi mode ADCs Regular channels configuration *** - ====================================================== - [..] - (+) Refer to "Regular channels group configuration" description to - configure the ADC1, ADC2 and ADC3 regular channels. - (+) Select the Multi mode ADC regular channels features (dual or - triple mode) using ADC_CommonInit() function and configure - the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() - functions. - (+) Read the ADCs converted values using the - ADC_GetMultiModeConversionValue() function. - - *** DMA for Regular channels group features configuration *** - ============================================================= - [..] - (+) To enable the DMA mode for regular channels group, use the - ADC_DMACmd() function. - (+) To enable the generation of DMA requests continuously at the end - of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() - function. - - *** Injected channels group configuration *** - ============================================= - [..] - (+) To configure the ADC Injected channels group features, use - ADC_InjectedChannelConfig() and ADC_InjectedSequencerLengthConfig() - functions. - (+) To activate the continuous mode, use the ADC_continuousModeCmd() - function. - (+) To activate the Injected Discontinuous mode, use the - ADC_InjectedDiscModeCmd() function. - (+) To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() - function. - (+) To read the ADC converted values, use the ADC_GetInjectedConversionValue() - function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_adc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup ADC - * @brief ADC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ADC DISCNUM mask */ -#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF) - -/* ADC AWDCH mask */ -#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0) - -/* ADC Analog watchdog enable mode mask */ -#define CR1_AWDMode_RESET ((uint32_t)0xFF3FFDFF) - -/* CR1 register Mask */ -#define CR1_CLEAR_MASK ((uint32_t)0xFCFFFEFF) - -/* ADC EXTEN mask */ -#define CR2_EXTEN_RESET ((uint32_t)0xCFFFFFFF) - -/* ADC JEXTEN mask */ -#define CR2_JEXTEN_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC JEXTSEL mask */ -#define CR2_JEXTSEL_RESET ((uint32_t)0xFFF0FFFF) - -/* CR2 register Mask */ -#define CR2_CLEAR_MASK ((uint32_t)0xC0FFF7FD) - -/* ADC SQx mask */ -#define SQR3_SQ_SET ((uint32_t)0x0000001F) -#define SQR2_SQ_SET ((uint32_t)0x0000001F) -#define SQR1_SQ_SET ((uint32_t)0x0000001F) - -/* ADC L Mask */ -#define SQR1_L_RESET ((uint32_t)0xFF0FFFFF) - -/* ADC JSQx mask */ -#define JSQR_JSQ_SET ((uint32_t)0x0000001F) - -/* ADC JL mask */ -#define JSQR_JL_SET ((uint32_t)0x00300000) -#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF) - -/* ADC SMPx mask */ -#define SMPR1_SMP_SET ((uint32_t)0x00000007) -#define SMPR2_SMP_SET ((uint32_t)0x00000007) - -/* ADC JDRx registers offset */ -#define JDR_OFFSET ((uint8_t)0x28) - -/* ADC CDR register base address */ -#define CDR_ADDRESS ((uint32_t)0x40012308) - -/* ADC CCR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0xFFFC30E0) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/** @defgroup ADC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC Prescaler - (+) ADC Conversion Resolution (12bit..6bit) - (+) Scan Conversion Mode (multichannel or one channel) for regular group - (+) ADC Continuous Conversion Mode (Continuous or Single conversion) for - regular group - (+) External trigger Edge and source of regular group, - (+) Converted data alignment (left or right) - (+) The number of ADC conversions that will be done using the sequencer for - regular channel group - (+) Multi ADC mode selection - (+) Direct memory access mode selection for multi ADC mode - (+) Delay between 2 sampling phases (used in dual or triple interleaved modes) - (+) Enable or disable the ADC peripheral -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes all ADCs peripherals registers to their default reset - * values. - * @param None - * @retval None - */ -void ADC_DeInit(void) -{ - /* Enable all ADCs reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); - - /* Release all ADCs from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); -} - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct. - * @note This function is used to configure the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains - * the configuration information for the specified ADC peripheral. - * @retval None - */ -void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) -{ - uint32_t tmpreg1 = 0; - uint8_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); - assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion)); - - /*---------------------------- ADCx CR1 Configuration -----------------*/ - /* Get the ADCx CR1 value */ - tmpreg1 = ADCx->CR1; - - /* Clear RES and SCAN bits */ - tmpreg1 &= CR1_CLEAR_MASK; - - /* Configure ADCx: scan conversion mode and resolution */ - /* Set SCAN bit according to ADC_ScanConvMode value */ - /* Set RES bit according to ADC_Resolution value */ - tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \ - ADC_InitStruct->ADC_Resolution); - /* Write to ADCx CR1 */ - ADCx->CR1 = tmpreg1; - /*---------------------------- ADCx CR2 Configuration -----------------*/ - /* Get the ADCx CR2 value */ - tmpreg1 = ADCx->CR2; - - /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */ - tmpreg1 &= CR2_CLEAR_MASK; - - /* Configure ADCx: external trigger event and edge, data alignment and - continuous conversion mode */ - /* Set ALIGN bit according to ADC_DataAlign value */ - /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ - /* Set EXTSEL bits according to ADC_ExternalTrigConv value */ - /* Set CONT bit according to ADC_ContinuousConvMode value */ - tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \ - ADC_InitStruct->ADC_ExternalTrigConv | - ADC_InitStruct->ADC_ExternalTrigConvEdge | \ - ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); - - /* Write to ADCx CR2 */ - ADCx->CR2 = tmpreg1; - /*---------------------------- ADCx SQR1 Configuration -----------------*/ - /* Get the ADCx SQR1 value */ - tmpreg1 = ADCx->SQR1; - - /* Clear L bits */ - tmpreg1 &= SQR1_L_RESET; - - /* Configure ADCx: regular channel sequence length */ - /* Set L bits according to ADC_NbrOfConversion value */ - tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1); - tmpreg1 |= ((uint32_t)tmpreg2 << 20); - - /* Write to ADCx SQR1 */ - ADCx->SQR1 = tmpreg1; -} - -/** - * @brief Fills each ADC_InitStruct member with its default value. - * @note This function is used to initialize the global features of the ADC ( - * Resolution and Data Alignment), however, the rest of the configuration - * parameters are specific to the regular channels group (scan mode - * activation, continuous mode activation, External trigger source and - * edge, number of conversion in the regular channels group sequencer). - * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b; - - /* initialize the ADC_ScanConvMode member */ - ADC_InitStruct->ADC_ScanConvMode = DISABLE; - - /* Initialize the ADC_ContinuousConvMode member */ - ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; - - /* Initialize the ADC_ExternalTrigConvEdge member */ - ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None; - - /* Initialize the ADC_ExternalTrigConv member */ - ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; - - /* Initialize the ADC_DataAlign member */ - ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; - - /* Initialize the ADC_NbrOfConversion member */ - ADC_InitStruct->ADC_NbrOfConversion = 1; -} - -/** - * @brief Initializes the ADCs peripherals according to the specified parameters - * in the ADC_CommonInitStruct. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * that contains the configuration information for All ADCs peripherals. - * @retval None - */ -void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - uint32_t tmpreg1 = 0; - /* Check the parameters */ - assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode)); - assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler)); - assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay)); - /*---------------------------- ADC CCR Configuration -----------------*/ - /* Get the ADC CCR value */ - tmpreg1 = ADC->CCR; - - /* Clear MULTI, DELAY, DMA and ADCPRE bits */ - tmpreg1 &= CR_CLEAR_MASK; - - /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler, - and DMA access mode for multimode */ - /* Set MULTI bits according to ADC_Mode value */ - /* Set ADCPRE bits according to ADC_Prescaler value */ - /* Set DMA bits according to ADC_DMAAccessMode value */ - /* Set DELAY bits according to ADC_TwoSamplingDelay value */ - tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | - ADC_CommonInitStruct->ADC_Prescaler | - ADC_CommonInitStruct->ADC_DMAAccessMode | - ADC_CommonInitStruct->ADC_TwoSamplingDelay); - - /* Write to ADC CCR */ - ADC->CCR = tmpreg1; -} - -/** - * @brief Fills each ADC_CommonInitStruct member with its default value. - * @param ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure - * which will be initialized. - * @retval None - */ -void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct) -{ - /* Initialize the ADC_Mode member */ - ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent; - - /* initialize the ADC_Prescaler member */ - ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2; - - /* Initialize the ADC_DMAAccessMode member */ - ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled; - - /* Initialize the ADC_TwoSamplingDelay member */ - ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles; -} - -/** - * @brief Enables or disables the specified ADC peripheral. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the ADCx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the ADON bit to wake up the ADC from power down mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_ADON; - } - else - { - /* Disable the selected ADC peripheral */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group2 Analog Watchdog configuration functions - * @brief Analog Watchdog configuration functions - * -@verbatim - =============================================================================== - ##### Analog Watchdog configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the Analog Watchdog - (AWD) feature in the ADC. - - [..] A typical configuration Analog Watchdog is done following these steps : - (#) the ADC guarded channel(s) is (are) selected using the - ADC_AnalogWatchdogSingleChannelConfig() function. - (#) The Analog watchdog lower and higher threshold are configured using the - ADC_AnalogWatchdogThresholdsConfig() function. - (#) The Analog watchdog is enabled and configured to enable the check, on one - or more channels, using the ADC_AnalogWatchdogCmd() function. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the analog watchdog on single/all regular or - * injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_AnalogWatchdog: the ADC analog watchdog configuration. - * This parameter can be one of the following values: - * @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel - * @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel - * @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel - * @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel - * @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel - * @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels - * @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog - * @retval None - */ -void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - tmpreg &= CR1_AWDMode_RESET; - - /* Set the analog watchdog enable mode */ - tmpreg |= ADC_AnalogWatchdog; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} - -/** - * @brief Configures the high and low thresholds of the analog watchdog. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param HighThreshold: the ADC analog watchdog High threshold value. - * This parameter must be a 12-bit value. - * @param LowThreshold: the ADC analog watchdog Low threshold value. - * This parameter must be a 12-bit value. - * @retval None - */ -void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, - uint16_t LowThreshold) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_THRESHOLD(HighThreshold)); - assert_param(IS_ADC_THRESHOLD(LowThreshold)); - - /* Set the ADCx high threshold */ - ADCx->HTR = HighThreshold; - - /* Set the ADCx low threshold */ - ADCx->LTR = LowThreshold; -} - -/** - * @brief Configures the analog watchdog guarded single channel - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure for the analog watchdog. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @retval None - */ -void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - - /* Get the old register value */ - tmpreg = ADCx->CR1; - - /* Clear the Analog watchdog channel select bits */ - tmpreg &= CR1_AWDCH_RESET; - - /* Set the Analog watchdog channel */ - tmpreg |= ADC_Channel; - - /* Store the new register value */ - ADCx->CR1 = tmpreg; -} -/** - * @} - */ - -/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) - * and VBAT (Voltage BATtery) management functions - * @brief Temperature Sensor, Vrefint and VBAT management functions - * -@verbatim - =============================================================================== - ##### Temperature Sensor, Vrefint and VBAT management functions ##### - =============================================================================== - [..] This section provides functions allowing to enable/ disable the internal - connections between the ADC and the Temperature Sensor, the Vrefint and - the Vbat sources. - - [..] A typical configuration to get the Temperature sensor and Vrefint channels - voltages is done following these steps : - (#) Enable the internal connection of Temperature sensor and Vrefint sources - with the ADC channels using ADC_TempSensorVrefintCmd() function. - (#) Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using - ADC_RegularChannelConfig() or ADC_InjectedChannelConfig() functions - (#) Get the voltage values, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - - [..] A typical configuration to get the VBAT channel voltage is done following - these steps : - (#) Enable the internal connection of VBAT source with the ADC channel using - ADC_VBATCmd() function. - (#) Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or - ADC_InjectedChannelConfig() functions - (#) Get the voltage value, using ADC_GetConversionValue() or - ADC_GetInjectedConversionValue(). - -@endverbatim - * @{ - */ - - -/** - * @brief Enables or disables the temperature sensor and Vrefint channels. - * @param NewState: new state of the temperature sensor and Vrefint channels. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_TempSensorVrefintCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the temperature sensor and Vrefint channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE; - } - else - { - /* Disable the temperature sensor and Vrefint channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE); - } -} - -/** - * @brief Enables or disables the VBAT (Voltage Battery) channel. - * - * @note the Battery voltage measured is equal to VBAT/2 on STM32F40xx and - * STM32F41xx devices and equal to VBAT/4 on STM32F42xx and STM32F43xx devices - * - * @param NewState: new state of the VBAT channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_VBATCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the VBAT channel*/ - ADC->CCR |= (uint32_t)ADC_CCR_VBATE; - } - else - { - /* Disable the VBAT channel*/ - ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE); - } -} - -/** - * @} - */ - -/** @defgroup ADC_Group4 Regular Channels Configuration functions - * @brief Regular Channels Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels Configuration functions ##### - =============================================================================== - - [..] This section provides functions allowing to manage the ADC's regular channels, - it is composed of 2 sub sections : - - (#) Configuration and management functions for regular channels: This subsection - provides functions allowing to configure the ADC regular channels : - (++) Configure the rank in the regular group sequencer for each channel - (++) Configure the sampling time for each channel - (++) select the conversion Trigger for regular channels - (++) select the desired EOC event behavior configuration - (++) Activate the continuous Mode (*) - (++) Activate the Discontinuous Mode - -@@- Please Note that the following features for regular channels - are configured using the ADC_Init() function : - (+@@) scan mode activation - (+@@) continuous mode activation (**) - (+@@) External trigger source - (+@@) External trigger edge - (+@@) number of conversion in the regular channels group sequencer. - - -@@- (*) and (**) are performing the same configuration - - (#) Get the conversion data: This subsection provides an important function in - the ADC peripheral since it returns the converted data of the current - regular channel. When the Conversion value is read, the EOC Flag is - automatically cleared. - - -@- For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions - results data (in the selected multi mode) can be returned in the same - time using ADC_GetMultiModeConversionValue() function. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the regular group sequencer. - * This parameter must be between 1 to 16. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_REGULAR_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10)); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* For Rank 1 to 6 */ - if (Rank < 7) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR3; - - /* Calculate the mask to clear */ - tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR3 = tmpreg1; - } - /* For Rank 7 to 12 */ - else if (Rank < 13) - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR2; - - /* Calculate the mask to clear */ - tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR2 = tmpreg1; - } - /* For Rank 13 to 16 */ - else - { - /* Get the old register value */ - tmpreg1 = ADCx->SQR1; - - /* Calculate the mask to clear */ - tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13)); - - /* Clear the old SQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); - - /* Set the SQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - - /* Store the new register value */ - ADCx->SQR1 = tmpreg1; - } -} - -/** - * @brief Enables the selected ADC software start conversion of the regular channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Enable the selected ADC conversion for regular group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART; -} - -/** - * @brief Gets the selected ADC Software start regular conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of SWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_SWSTART) != (uint32_t)RESET) - { - /* SWSTART bit is set */ - bitstatus = SET; - } - else - { - /* SWSTART bit is reset */ - bitstatus = RESET; - } - - /* Return the SWSTART bit status */ - return bitstatus; -} - - -/** - * @brief Enables or disables the EOC on each regular channel conversion - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC EOC flag rising - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS); - } -} - -/** - * @brief Enables or disables the ADC continuous conversion mode - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC continuous conversion mode - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC continuous conversion mode */ - ADCx->CR2 |= (uint32_t)ADC_CR2_CONT; - } - else - { - /* Disable the selected ADC continuous conversion mode */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT); - } -} - -/** - * @brief Configures the discontinuous mode for the selected ADC regular group - * channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Number: specifies the discontinuous mode regular channel count value. - * This number must be between 1 and 8. - * @retval None - */ -void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number)); - - /* Get the old register value */ - tmpreg1 = ADCx->CR1; - - /* Clear the old discontinuous mode channel count */ - tmpreg1 &= CR1_DISCNUM_RESET; - - /* Set the discontinuous mode channel count */ - tmpreg2 = Number - 1; - tmpreg1 |= tmpreg2 << 13; - - /* Store the new register value */ - ADCx->CR1 = tmpreg1; -} - -/** - * @brief Enables or disables the discontinuous mode on regular group channel - * for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on - * regular group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected ADC regular discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN; - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN); - } -} - -/** - * @brief Returns the last ADCx conversion result data for regular channel. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The Data conversion value. - */ -uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Return the selected ADC conversion value */ - return (uint16_t) ADCx->DR; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param None - * @retval The Data conversion value. - * @note In dual mode, the value returned by this function is as following - * Data[15:0] : these bits contain the regular data of ADC1. - * Data[31:16]: these bits contain the regular data of ADC2. - * @note In triple mode, the value returned by this function is as following - * Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2. - * Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3. - */ -uint32_t ADC_GetMultiModeConversionValue(void) -{ - /* Return the multi mode conversion value */ - return (*(__IO uint32_t *) CDR_ADDRESS); -} -/** - * @} - */ - -/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions - * @brief Regular Channels DMA Configuration functions - * -@verbatim - =============================================================================== - ##### Regular Channels DMA Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA for ADC - regular channels. - Since converted regular channel values are stored into a unique data - register, it is useful to use DMA for conversion of more than one regular - channel. This avoids the loss of the data already stored in the ADC - Data register. - When the DMA mode is enabled (using the ADC_DMACmd() function), after each - conversion of a regular channel, a DMA request is generated. - [..] Depending on the "DMA disable selection for Independent ADC mode" - configuration (using the ADC_DMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - [..] Depending on the "DMA disable selection for multi ADC mode" configuration - (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), - at the end of the last DMA transfer, two possibilities are allowed: - (+) No new DMA request is issued to the DMA controller (feature DISABLED) - (+) Requests can continue to be generated (feature ENABLED). - -@endverbatim - * @{ - */ - - /** - * @brief Enables or disables the specified ADC DMA request. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DMA; - } - else - { - /* Disable the selected ADC DMA request */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADCx->CR2 |= (uint32_t)ADC_CR2_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS); - } -} - -/** - * @brief Enables or disables the ADC DMA request after last transfer in multi ADC mode - * @param NewState: new state of the selected ADC DMA request after last transfer. - * This parameter can be: ENABLE or DISABLE. - * @note if Enabled, DMA requests are issued as long as data are converted and - * DMA mode for multi ADC mode (selected using ADC_CommonInit() function - * by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is - * ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3. - * @retval None - */ -void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= (uint32_t)ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC DMA request after last transfer */ - ADC->CCR &= (uint32_t)(~ADC_CCR_DDS); - } -} -/** - * @} - */ - -/** @defgroup ADC_Group6 Injected channels Configuration functions - * @brief Injected channels Configuration functions - * -@verbatim - =============================================================================== - ##### Injected channels Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the ADC Injected channels, - it is composed of 2 sub sections : - - (#) Configuration functions for Injected channels: This subsection provides - functions allowing to configure the ADC injected channels : - (++) Configure the rank in the injected group sequencer for each channel - (++) Configure the sampling time for each channel - (++) Activate the Auto injected Mode - (++) Activate the Discontinuous Mode - (++) scan mode activation - (++) External/software trigger source - (++) External trigger edge - (++) injected channels sequencer. - - (#) Get the Specified Injected channel conversion data: This subsection - provides an important function in the ADC peripheral since it returns the - converted data of the specific injected channel. - -@endverbatim - * @{ - */ -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_Channel: the ADC channel to configure. - * This parameter can be one of the following values: - * @arg ADC_Channel_0: ADC Channel0 selected - * @arg ADC_Channel_1: ADC Channel1 selected - * @arg ADC_Channel_2: ADC Channel2 selected - * @arg ADC_Channel_3: ADC Channel3 selected - * @arg ADC_Channel_4: ADC Channel4 selected - * @arg ADC_Channel_5: ADC Channel5 selected - * @arg ADC_Channel_6: ADC Channel6 selected - * @arg ADC_Channel_7: ADC Channel7 selected - * @arg ADC_Channel_8: ADC Channel8 selected - * @arg ADC_Channel_9: ADC Channel9 selected - * @arg ADC_Channel_10: ADC Channel10 selected - * @arg ADC_Channel_11: ADC Channel11 selected - * @arg ADC_Channel_12: ADC Channel12 selected - * @arg ADC_Channel_13: ADC Channel13 selected - * @arg ADC_Channel_14: ADC Channel14 selected - * @arg ADC_Channel_15: ADC Channel15 selected - * @arg ADC_Channel_16: ADC Channel16 selected - * @arg ADC_Channel_17: ADC Channel17 selected - * @arg ADC_Channel_18: ADC Channel18 selected - * @param Rank: The rank in the injected group sequencer. - * This parameter must be between 1 to 4. - * @param ADC_SampleTime: The sample time value to be set for the selected channel. - * This parameter can be one of the following values: - * @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles - * @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles - * @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles - * @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles - * @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles - * @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles - * @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles - * @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles - * @retval None - */ -void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CHANNEL(ADC_Channel)); - assert_param(IS_ADC_INJECTED_RANK(Rank)); - assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime)); - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (ADC_Channel > ADC_Channel_9) - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR1; - /* Calculate the mask to clear */ - tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10)); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10)); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR1 = tmpreg1; - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Get the old register value */ - tmpreg1 = ADCx->SMPR2; - /* Calculate the mask to clear */ - tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel); - /* Clear the old sample time */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set */ - tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); - /* Set the new sample time */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->SMPR2 = tmpreg1; - } - /* Rank configuration */ - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - /* Get JL value: Number = JL+1 */ - tmpreg3 = (tmpreg1 & JSQR_JL_SET)>> 20; - /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Clear the old JSQx bits for the selected rank */ - tmpreg1 &= ~tmpreg2; - /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */ - tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); - /* Set the JSQx bits for the selected rank */ - tmpreg1 |= tmpreg2; - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Configures the sequencer length for injected channels - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param Length: The sequencer length. - * This parameter must be a number between 1 to 4. - * @retval None - */ -void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length) -{ - uint32_t tmpreg1 = 0; - uint32_t tmpreg2 = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_LENGTH(Length)); - - /* Get the old register value */ - tmpreg1 = ADCx->JSQR; - - /* Clear the old injected sequence length JL bits */ - tmpreg1 &= JSQR_JL_RESET; - - /* Set the injected sequence length JL bits */ - tmpreg2 = Length - 1; - tmpreg1 |= tmpreg2 << 20; - - /* Store the new register value */ - ADCx->JSQR = tmpreg1; -} - -/** - * @brief Set the injected channels conversion value offset - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the ADC injected channel to set its offset. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @param Offset: the offset value for the selected ADC injected channel - * This parameter must be a 12bit value. - * @retval None - */ -void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) -{ - __IO uint32_t tmp = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - assert_param(IS_ADC_OFFSET(Offset)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel; - - /* Set the selected injected channel data offset */ - *(__IO uint32_t *) tmp = (uint32_t)Offset; -} - - /** - * @brief Configures the ADCx external trigger for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected - * @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected - * @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected - * @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected - * @retval None - */ -void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv)); - - /* Get the old register value */ - tmpreg = ADCx->CR2; - - /* Clear the old external event selection for injected group */ - tmpreg &= CR2_JEXTSEL_RESET; - - /* Set the external event selection for injected group */ - tmpreg |= ADC_ExternalTrigInjecConv; - - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Configures the ADCx external trigger edge for injected channels conversion. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge - * to start injected conversion. - * This parameter can be one of the following values: - * @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for - * injected conversion - * @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge - * @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge - * @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising - * and falling edge - * @retval None - */ -void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge)); - /* Get the old register value */ - tmpreg = ADCx->CR2; - /* Clear the old external trigger edge for injected group */ - tmpreg &= CR2_JEXTEN_RESET; - /* Set the new external trigger edge for injected group */ - tmpreg |= ADC_ExternalTrigInjecConvEdge; - /* Store the new register value */ - ADCx->CR2 = tmpreg; -} - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval None - */ -void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - /* Enable the selected ADC conversion for injected group */ - ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART; -} - -/** - * @brief Gets the selected ADC Software start injected conversion Status. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @retval The new state of ADC software start injected conversion (SET or RESET). - */ -FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - - /* Check the status of JSWSTART bit */ - if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET) - { - /* JSWSTART bit is set */ - bitstatus = SET; - } - else - { - /* JSWSTART bit is reset */ - bitstatus = RESET; - } - /* Return the JSWSTART bit status */ - return bitstatus; -} - -/** - * @brief Enables or disables the selected ADC automatic injected group - * conversion after regular one. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC auto injected conversion - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO); - } -} - -/** - * @brief Enables or disables the discontinuous mode for injected group - * channel for the specified ADC - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param NewState: new state of the selected ADC discontinuous mode on injected - * group channel. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN); - } -} - -/** - * @brief Returns the ADC injected channel conversion result - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_InjectedChannel: the converted ADC injected channel. - * This parameter can be one of the following values: - * @arg ADC_InjectedChannel_1: Injected Channel1 selected - * @arg ADC_InjectedChannel_2: Injected Channel2 selected - * @arg ADC_InjectedChannel_3: Injected Channel3 selected - * @arg ADC_InjectedChannel_4: Injected Channel4 selected - * @retval The Data conversion value. - */ -uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel)); - - tmp = (uint32_t)ADCx; - tmp += ADC_InjectedChannel + JDR_OFFSET; - - /* Returns the selected injected channel conversion data value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup ADC_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the ADC Interrupts - and to get the status and clear flags and Interrupts pending bits. - - [..] Each ADC provides 4 Interrupts sources and 6 Flags which can be divided - into 3 groups: - - *** Flags and Interrupts for ADC regular channels *** - ===================================================== - [..] - (+) Flags : - (##) ADC_FLAG_OVR : Overrun detection when regular converted data are lost - - (##) ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate - (depending on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) - the end of: - (+++) a regular CHANNEL conversion - (+++) sequence of regular GROUP conversions . - - (##) ADC_FLAG_STRT: Regular channel start ==> to indicate when regular - CHANNEL conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection - event. - (##) ADC_IT_EOC : specifies the interrupt source for Regular channel end - of conversion event. - - - *** Flags and Interrupts for ADC Injected channels *** - ====================================================== - [..] - (+) Flags : - (##) ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate - at the end of injected GROUP conversion - - (##) ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when - injected GROUP conversion starts. - [..] - (+) Interrupts : - (##) ADC_IT_JEOC : specifies the interrupt source for Injected channel - end of conversion event. - - *** General Flags and Interrupts for the ADC *** - ================================================ - [..] - (+)Flags : - (##) ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage - crosses the programmed thresholds values. - [..] - (+) Interrupts : - (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. - - - [..] The user should identify which mode will be used in his application to - manage the ADC controller events: Polling mode or Interrupt mode. - - [..] In the Polling Mode it is advised to use the following functions: - (+) ADC_GetFlagStatus() : to check if flags events occur. - (+) ADC_ClearFlag() : to clear the flags events. - - [..] In the Interrupt Mode it is advised to use the following functions: - (+) ADC_ITConfig() : to enable or disable the interrupt source. - (+) ADC_GetITStatus() : to check if Interrupt occurs. - (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified ADC interrupts. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt enable - * @param NewState: new state of the specified ADC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState) -{ - uint32_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = (uint8_t)ADC_IT; - itmask = (uint32_t)0x01 << itmask; - - if (NewState != DISABLE) - { - /* Enable the selected ADC interrupts */ - ADCx->CR1 |= itmask; - } - else - { - /* Disable the selected ADC interrupts */ - ADCx->CR1 &= (~(uint32_t)itmask); - } -} - -/** - * @brief Checks whether the specified ADC flag is set or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval The new state of ADC_FLAG (SET or RESET). - */ -FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); - - /* Check the status of the specified ADC flag */ - if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET) - { - /* ADC_FLAG is set */ - bitstatus = SET; - } - else - { - /* ADC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the ADC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's pending flags. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg ADC_FLAG_AWD: Analog watchdog flag - * @arg ADC_FLAG_EOC: End of conversion flag - * @arg ADC_FLAG_JEOC: End of injected group conversion flag - * @arg ADC_FLAG_JSTRT: Start of injected group conversion flag - * @arg ADC_FLAG_STRT: Start of regular group conversion flag - * @arg ADC_FLAG_OVR: Overrun flag - * @retval None - */ -void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); - - /* Clear the selected ADC flags */ - ADCx->SR = ~(uint32_t)ADC_FLAG; -} - -/** - * @brief Checks whether the specified ADC interrupt has occurred or not. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt source to check. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval The new state of ADC_IT (SET or RESET). - */ -ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - - /* Get the ADC IT index */ - itmask = ADC_IT >> 8; - - /* Get the ADC_IT enable bit status */ - enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ; - - /* Check the status of the specified ADC interrupt */ - if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus) - { - /* ADC_IT is set */ - bitstatus = SET; - } - else - { - /* ADC_IT is reset */ - bitstatus = RESET; - } - /* Return the ADC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the ADCx's interrupt pending bits. - * @param ADCx: where x can be 1, 2 or 3 to select the ADC peripheral. - * @param ADC_IT: specifies the ADC interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg ADC_IT_EOC: End of conversion interrupt mask - * @arg ADC_IT_AWD: Analog watchdog interrupt mask - * @arg ADC_IT_JEOC: End of injected conversion interrupt mask - * @arg ADC_IT_OVR: Overrun interrupt mask - * @retval None - */ -void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT) -{ - uint8_t itmask = 0; - /* Check the parameters */ - assert_param(IS_ADC_ALL_PERIPH(ADCx)); - assert_param(IS_ADC_IT(ADC_IT)); - /* Get the ADC IT index */ - itmask = (uint8_t)(ADC_IT >> 8); - /* Clear the selected ADC interrupt pending bits */ - ADCx->SR = ~(uint32_t)itmask; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c deleted file mode 100644 index e11936d24..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c +++ /dev/null @@ -1,1856 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_can.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Controller area network (CAN) peripheral: - * + Initialization and Configuration - * + CAN Frames Transmission - * + CAN Frames Reception - * + Operation modes switch - * + Error management - * + Interrupts and flags - * -@verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the CAN controller interface clock using - RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 - and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2 - -@- In case you are using CAN2 only, you have to enable the CAN1 clock. - - (#) CAN pins configuration - (++) Enable the clock for the CAN GPIOs using the following function: - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - (++) Connect the involved CAN pins to AF9 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); - (++) Configure these CAN pins in alternate function mode by calling - the function GPIO_Init(); - - (#) Initialize and configure the CAN using CAN_Init() and - CAN_FilterInit() functions. - - (#) Transmit the desired CAN frame using CAN_Transmit() function. - - (#) Check the transmission of a CAN frame using CAN_TransmitStatus() - function. - - (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() - function. - - (#) Receive a CAN frame using CAN_Receive() function. - - (#) Release the receive FIFOs using CAN_FIFORelease() function. - - (#) Return the number of pending received frames using - CAN_MessagePending() function. - - (#) To control CAN events you can use one of the following two methods: - (++) Check on CAN flags using the CAN_GetFlagStatus() function. - (++) Use CAN interrupts through the function CAN_ITConfig() at - initialization phase and CAN_GetITStatus() function into - interrupt routines to check if the event has occurred or not. - After checking on a flag you should clear it using CAN_ClearFlag() - function. And after checking on an interrupt event you should - clear it using CAN_ClearITPendingBit() function. - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_can.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CAN - * @brief CAN driver modules - * @{ - */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CAN Master Control Register bits */ -#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */ - -/* CAN Mailbox Transmit Request */ -#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ - -/* CAN Filter Master Register bits */ -#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ - -/* Time out for INAK bit */ -#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) -/* Time out for SLAK bit */ -#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) - -/* Flags in TSR register */ -#define CAN_FLAGS_TSR ((uint32_t)0x08000000) -/* Flags in RF1R register */ -#define CAN_FLAGS_RF1R ((uint32_t)0x04000000) -/* Flags in RF0R register */ -#define CAN_FLAGS_RF0R ((uint32_t)0x02000000) -/* Flags in MSR register */ -#define CAN_FLAGS_MSR ((uint32_t)0x01000000) -/* Flags in ESR register */ -#define CAN_FLAGS_ESR ((uint32_t)0x00F00000) - -/* Mailboxes definition */ -#define CAN_TXMAILBOX_0 ((uint8_t)0x00) -#define CAN_TXMAILBOX_1 ((uint8_t)0x01) -#define CAN_TXMAILBOX_2 ((uint8_t)0x02) - -#define CAN_MODE_MASK ((uint32_t) 0x00000003) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); - -/** @defgroup CAN_Private_Functions - * @{ - */ - -/** @defgroup CAN_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum - number of time quanta to perform resynchronization, the number of time - quanta in Bit Segment 1 and 2 and many other modes. - Refer to @ref CAN_InitTypeDef for more details. - (+) Configures the CAN reception filter. - (+) Select the start bank filter for slave CAN. - (+) Enables or disables the Debug Freeze mode for CAN - (+)Enables or disables the CAN Time Trigger Operation communication mode - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the CAN peripheral registers to their default reset values. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None. - */ -void CAN_DeInit(CAN_TypeDef* CANx) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - if (CANx == CAN1) - { - /* Enable CAN1 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); - /* Release CAN1 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); - } -#if defined(STM32F413_423xx) - else if(CANx == CAN2) - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } - - else /* CAN3 available only for STM32F413_423xx */ - { - /* Enable CAN3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, ENABLE); - /* Release CAN3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, DISABLE); - } -#else - else - { - /* Enable CAN2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); - /* Release CAN2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); - } -#endif /* STM32F413_423xx */ -} - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains - * the configuration information for the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval Constant indicates initialization succeed which will be - * CAN_InitStatus_Failed or CAN_InitStatus_Success. - */ -uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) -{ - uint8_t InitStatus = CAN_InitStatus_Failed; - uint32_t wait_ack = 0x00000000; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); - assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); - assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); - assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); - assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); - assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); - assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); - - /* Exit from sleep mode */ - CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP); - - /* Request initialisation */ - CANx->MCR |= CAN_MCR_INRQ ; - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* Check acknowledge */ - if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - /* Set the time triggered communication mode */ - if (CAN_InitStruct->CAN_TTCM == ENABLE) - { - CANx->MCR |= CAN_MCR_TTCM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM; - } - - /* Set the automatic bus-off management */ - if (CAN_InitStruct->CAN_ABOM == ENABLE) - { - CANx->MCR |= CAN_MCR_ABOM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM; - } - - /* Set the automatic wake-up mode */ - if (CAN_InitStruct->CAN_AWUM == ENABLE) - { - CANx->MCR |= CAN_MCR_AWUM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM; - } - - /* Set the no automatic retransmission */ - if (CAN_InitStruct->CAN_NART == ENABLE) - { - CANx->MCR |= CAN_MCR_NART; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_NART; - } - - /* Set the receive FIFO locked mode */ - if (CAN_InitStruct->CAN_RFLM == ENABLE) - { - CANx->MCR |= CAN_MCR_RFLM; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM; - } - - /* Set the transmit FIFO priority */ - if (CAN_InitStruct->CAN_TXFP == ENABLE) - { - CANx->MCR |= CAN_MCR_TXFP; - } - else - { - CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP; - } - - /* Set the bit timing register */ - CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \ - ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \ - ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \ - ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \ - ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); - - /* Request leave initialisation */ - CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ; - - /* Wait the acknowledge */ - wait_ack = 0; - - while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT)) - { - wait_ack++; - } - - /* ...and check acknowledged */ - if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) - { - InitStatus = CAN_InitStatus_Failed; - } - else - { - InitStatus = CAN_InitStatus_Success ; - } - } - - /* At this step, return the status of initialization */ - return InitStatus; -} - -#if defined(STM32F413_423xx) -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CANx: where x can be 1 or 3 to select the CAN peripheral. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CANx->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CANx->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CANx->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CANx->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CANx->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CANx->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CANx->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CANx->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CANx->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CANx->FMR &= ~FMR_FINIT; -} -#else -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that - * contains the configuration information. - * @retval None - */ -void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) -{ - uint32_t filter_number_bit_pos = 0; - /* Check the parameters */ - assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); - assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); - assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); - - filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; - - /* Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Filter Deactivation */ - CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; - - /* Filter Scale */ - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) - { - /* 16-bit scale for the filter */ - CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); - } - - if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) - { - /* 32-bit scale for the filter */ - CAN1->FS1R |= filter_number_bit_pos; - /* 32-bit identifier or First 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); - /* 32-bit mask or Second 32-bit identifier */ - CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = - ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | - (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); - } - - /* Filter Mode */ - if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) - { - /*Id/Mask mode for the filter*/ - CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /*Identifier list mode for the filter*/ - CAN1->FM1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter FIFO assignment */ - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; - } - - if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) - { - /* FIFO 1 assignation for the filter */ - CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; - } - - /* Filter activation */ - if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) - { - CAN1->FA1R |= filter_number_bit_pos; - } - - /* Leave the initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} -#endif /* STM32F413_423xx */ - -/** - * @brief Fills each CAN_InitStruct member with its default value. - * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized. - * @retval None - */ -void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct) -{ - /* Reset CAN init structure parameters values */ - - /* Initialize the time triggered communication mode */ - CAN_InitStruct->CAN_TTCM = DISABLE; - - /* Initialize the automatic bus-off management */ - CAN_InitStruct->CAN_ABOM = DISABLE; - - /* Initialize the automatic wake-up mode */ - CAN_InitStruct->CAN_AWUM = DISABLE; - - /* Initialize the no automatic retransmission */ - CAN_InitStruct->CAN_NART = DISABLE; - - /* Initialize the receive FIFO locked mode */ - CAN_InitStruct->CAN_RFLM = DISABLE; - - /* Initialize the transmit FIFO priority */ - CAN_InitStruct->CAN_TXFP = DISABLE; - - /* Initialize the CAN_Mode member */ - CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; - - /* Initialize the CAN_SJW member */ - CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; - - /* Initialize the CAN_BS1 member */ - CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; - - /* Initialize the CAN_BS2 member */ - CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; - - /* Initialize the CAN_Prescaler member */ - CAN_InitStruct->CAN_Prescaler = 1; -} - -#if defined(STM32F413_423xx) -/** - * @brief Select the start bank filter for slave CAN. - * @param CANx: where x can be 1 or 3 to select the CAN peripheral. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CANx->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CANx->FMR &= (uint32_t)0xFFFFC0F1 ; - CANx->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CANx->FMR &= ~FMR_FINIT; -} -#else -/** - * @brief Select the start bank filter for slave CAN. - * @param CAN_BankNumber: Select the start slave bank filter from 1..27. - * @retval None - */ -void CAN_SlaveStartBank(uint8_t CAN_BankNumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber)); - - /* Enter Initialisation mode for the filter */ - CAN1->FMR |= FMR_FINIT; - - /* Select the start slave bank */ - CAN1->FMR &= (uint32_t)0xFFFFC0F1 ; - CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8; - - /* Leave Initialisation mode for the filter */ - CAN1->FMR &= ~FMR_FINIT; -} -#endif /* STM32F413_423xx */ -/** - * @brief Enables or disables the DBG Freeze for CAN. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param NewState: new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Debug Freeze */ - CANx->MCR |= MCR_DBF; - } - else - { - /* Disable Debug Freeze */ - CANx->MCR &= ~MCR_DBF; - } -} - - -/** - * @brief Enables or disables the CAN Time TriggerOperation communication mode. - * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be - * sent over the CAN bus. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE. - * When enabled, Time stamp (TIME[15:0]) value is sent in the last two - * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] - * in data byte 7. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the TTCM mode */ - CANx->MCR |= CAN_MCR_TTCM; - - /* Set TGT bits */ - CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT); - } - else - { - /* Disable the TTCM mode */ - CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM); - - /* Reset TGT bits */ - CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT); - CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT); - CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT); - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group2 CAN Frames Transmission functions - * @brief CAN Frames Transmission functions - * -@verbatim - =============================================================================== - ##### CAN Frames Transmission functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initiate and transmit a CAN frame message (if there is an empty mailbox). - (+) Check the transmission status of a CAN Frame - (+) Cancel a transmit request - -@endverbatim - * @{ - */ - -/** - * @brief Initiates and transmits a CAN frame message. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval The number of the mailbox that is used for transmission or - * CAN_TxStatus_NoMailBox if there is no empty mailbox. - */ -uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage) -{ - uint8_t transmit_mailbox = 0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IDTYPE(TxMessage->IDE)); - assert_param(IS_CAN_RTR(TxMessage->RTR)); - assert_param(IS_CAN_DLC(TxMessage->DLC)); - - /* Select one empty transmit mailbox */ - if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) - { - transmit_mailbox = 0; - } - else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) - { - transmit_mailbox = 1; - } - else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2) - { - transmit_mailbox = 2; - } - else - { - transmit_mailbox = CAN_TxStatus_NoMailBox; - } - - if (transmit_mailbox != CAN_TxStatus_NoMailBox) - { - /* Set up the Id */ - CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ; - if (TxMessage->IDE == CAN_Id_Standard) - { - assert_param(IS_CAN_STDID(TxMessage->StdId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \ - TxMessage->RTR); - } - else - { - assert_param(IS_CAN_EXTID(TxMessage->ExtId)); - CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \ - TxMessage->IDE | \ - TxMessage->RTR); - } - - /* Set up the DLC */ - TxMessage->DLC &= (uint8_t)0x0000000F; - CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0; - CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC; - - /* Set up the data field */ - CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | - ((uint32_t)TxMessage->Data[2] << 16) | - ((uint32_t)TxMessage->Data[1] << 8) | - ((uint32_t)TxMessage->Data[0])); - CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | - ((uint32_t)TxMessage->Data[6] << 16) | - ((uint32_t)TxMessage->Data[5] << 8) | - ((uint32_t)TxMessage->Data[4])); - /* Request transmission */ - CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ; - } - return transmit_mailbox; -} - -/** - * @brief Checks the transmission status of a CAN Frame. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param TransmitMailbox: the number of the mailbox that is used for transmission. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, - * CAN_TxStatus_Failed in an other case. - */ -uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox) -{ - uint32_t state = 0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox)); - - switch (TransmitMailbox) - { - case (CAN_TXMAILBOX_0): - state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0); - break; - case (CAN_TXMAILBOX_1): - state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1); - break; - case (CAN_TXMAILBOX_2): - state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2); - break; - default: - state = CAN_TxStatus_Failed; - break; - } - switch (state) - { - /* transmit pending */ - case (0x0): state = CAN_TxStatus_Pending; - break; - /* transmit failed */ - case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed; - break; - /* transmit succeeded */ - case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok; - break; - case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok; - break; - default: state = CAN_TxStatus_Failed; - break; - } - return (uint8_t) state; -} - -/** - * @brief Cancels a transmit request. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param Mailbox: Mailbox number. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox)); - /* abort transmission */ - switch (Mailbox) - { - case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0; - break; - case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1; - break; - case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2; - break; - default: - break; - } -} -/** - * @} - */ - - -/** @defgroup CAN_Group3 CAN Frames Reception functions - * @brief CAN Frames Reception functions - * -@verbatim - =============================================================================== - ##### CAN Frames Reception functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Receive a correct CAN frame - (+) Release a specified receive FIFO (2 FIFOs are available) - (+) Return the number of the pending received CAN frames - -@endverbatim - * @{ - */ - -/** - * @brief Receives a correct CAN frame. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @param RxMessage: pointer to a structure receive frame which contains CAN Id, - * CAN DLC, CAN data and FMI number. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Get the Id */ - RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR; - if (RxMessage->IDE == CAN_Id_Standard) - { - RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21); - } - else - { - RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3); - } - - RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR; - /* Get the DLC */ - RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR; - /* Get the FMI */ - RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8); - /* Get the data field */ - RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR; - RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8); - RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16); - RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24); - RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR; - RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8); - RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16); - RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24); - /* Release the FIFO */ - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Releases the specified receive FIFO. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - /* Release FIFO0 */ - if (FIFONumber == CAN_FIFO0) - { - CANx->RF0R |= CAN_RF0R_RFOM0; - } - /* Release FIFO1 */ - else /* FIFONumber == CAN_FIFO1 */ - { - CANx->RF1R |= CAN_RF1R_RFOM1; - } -} - -/** - * @brief Returns the number of pending received messages. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval NbMessage : which is the number of pending message. - */ -uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber) -{ - uint8_t message_pending=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_FIFO(FIFONumber)); - if (FIFONumber == CAN_FIFO0) - { - message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03); - } - else if (FIFONumber == CAN_FIFO1) - { - message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03); - } - else - { - message_pending = 0; - } - return message_pending; -} -/** - * @} - */ - - -/** @defgroup CAN_Group4 CAN Operation modes functions - * @brief CAN Operation modes functions - * -@verbatim - =============================================================================== - ##### CAN Operation modes functions ##### - =============================================================================== - [..] This section provides functions allowing to select the CAN Operation modes - (+) sleep mode - (+) normal mode - (+) initialization mode - -@endverbatim - * @{ - */ - - -/** - * @brief Selects the CAN Operation mode. - * @param CAN_OperatingMode: CAN Operating Mode. - * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration. - * @retval status of the requested mode which can be - * - CAN_ModeStatus_Failed: CAN failed entering the specific mode - * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode - */ -uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode) -{ - uint8_t status = CAN_ModeStatus_Failed; - - /* Timeout for INAK or also for SLAK bits*/ - uint32_t timeout = INAK_TIMEOUT; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode)); - - if (CAN_OperatingMode == CAN_OperatingMode_Initialization) - { - /* Request initialisation */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Normal) - { - /* Request leave initialisation and sleep mode and enter Normal mode */ - CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ)); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != 0) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else if (CAN_OperatingMode == CAN_OperatingMode_Sleep) - { - /* Request Sleep mode */ - CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Wait the acknowledge */ - while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0)) - { - timeout--; - } - if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) - { - status = CAN_ModeStatus_Failed; - } - else - { - status = CAN_ModeStatus_Success; - } - } - else - { - status = CAN_ModeStatus_Failed; - } - - return (uint8_t) status; -} - -/** - * @brief Enters the Sleep (low power) mode. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise. - */ -uint8_t CAN_Sleep(CAN_TypeDef* CANx) -{ - uint8_t sleepstatus = CAN_Sleep_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Request Sleep mode */ - CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP); - - /* Sleep mode status */ - if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK) - { - /* Sleep mode not entered */ - sleepstatus = CAN_Sleep_Ok; - } - /* return sleep mode status */ - return (uint8_t)sleepstatus; -} - -/** - * @brief Wakes up the CAN peripheral from sleep mode . - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise. - */ -uint8_t CAN_WakeUp(CAN_TypeDef* CANx) -{ - uint32_t wait_slak = SLAK_TIMEOUT; - uint8_t wakeupstatus = CAN_WakeUp_Failed; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Wake up request */ - CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP; - - /* Sleep mode status */ - while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00)) - { - wait_slak--; - } - if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK) - { - /* wake up done : Sleep mode exited */ - wakeupstatus = CAN_WakeUp_Ok; - } - /* return wakeup status */ - return (uint8_t)wakeupstatus; -} -/** - * @} - */ - - -/** @defgroup CAN_Group5 CAN Bus Error management functions - * @brief CAN Bus Error management functions - * -@verbatim - =============================================================================== - ##### CAN Bus Error management functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Return the CANx's last error code (LEC) - (+) Return the CANx Receive Error Counter (REC) - (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC). - - -@- If TEC is greater than 255, The CAN is in bus-off state. - -@- if REC or TEC are greater than 96, an Error warning flag occurs. - -@- if REC or TEC are greater than 127, an Error Passive Flag occurs. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CANx's last error code (LEC). - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @retval Error code: - * - CAN_ERRORCODE_NoErr: No Error - * - CAN_ERRORCODE_StuffErr: Stuff Error - * - CAN_ERRORCODE_FormErr: Form Error - * - CAN_ERRORCODE_ACKErr : Acknowledgment Error - * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error - * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error - * - CAN_ERRORCODE_CRCErr: CRC Error - * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error - */ -uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx) -{ - uint8_t errorcode=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the error code*/ - errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC); - - /* Return the error code*/ - return errorcode; -} - -/** - * @brief Returns the CANx Receive Error Counter (REC). - * @note In case of an error during reception, this counter is incremented - * by 1 or by 8 depending on the error condition as defined by the CAN - * standard. After every successful reception, the counter is - * decremented by 1 or reset to 120 if its value was higher than 128. - * When the counter value exceeds 127, the CAN controller enters the - * error passive state. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval CAN Receive Error Counter. - */ -uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the Receive Error Counter*/ - counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24); - - /* Return the Receive Error Counter*/ - return counter; -} - - -/** - * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval LSB of the 9-bit CAN Transmit Error Counter. - */ -uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx) -{ - uint8_t counter=0; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - - /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16); - - /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */ - return counter; -} -/** - * @} - */ - -/** @defgroup CAN_Group6 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the CAN Interrupts - and to get the status and clear flags and Interrupts pending bits. - - The CAN provides 14 Interrupts sources and 15 Flags: - - - *** Flags *** - ============= - [..] The 15 flags can be divided on 4 groups: - - (+) Transmit Flags - (++) CAN_FLAG_RQCP0, - (++) CAN_FLAG_RQCP1, - (++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags - Set when the last request (transmit or abort) - has been performed. - - (+) Receive Flags - - - (++) CAN_FLAG_FMP0, - (++) CAN_FLAG_FMP1 : FIFO 0 and 1 Message Pending Flags - set to signal that messages are pending in the receive - FIFO. - These Flags are cleared only by hardware. - - (++) CAN_FLAG_FF0, - (++) CAN_FLAG_FF1 : FIFO 0 and 1 Full Flags - set when three messages are stored in the selected - FIFO. - - (++) CAN_FLAG_FOV0 - (++) CAN_FLAG_FOV1 : FIFO 0 and 1 Overrun Flags - set when a new message has been received and passed - the filter while the FIFO was full. - - (+) Operating Mode Flags - - (++) CAN_FLAG_WKU : Wake up Flag - set to signal that a SOF bit has been detected while - the CAN hardware was in Sleep mode. - - (++) CAN_FLAG_SLAK : Sleep acknowledge Flag - Set to signal that the CAN has entered Sleep Mode. - - (+) Error Flags - - (++) CAN_FLAG_EWG : Error Warning Flag - Set when the warning limit has been reached (Receive - Error Counter or Transmit Error Counter greater than 96). - This Flag is cleared only by hardware. - - (++) CAN_FLAG_EPV : Error Passive Flag - Set when the Error Passive limit has been reached - (Receive Error Counter or Transmit Error Counter - greater than 127). - This Flag is cleared only by hardware. - - (++) CAN_FLAG_BOF : Bus-Off Flag - set when CAN enters the bus-off state. The bus-off - state is entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - (++) CAN_FLAG_LEC : Last error code Flag - set If a message has been transferred (reception or - transmission) with error, and the error code is hold. - - *** Interrupts *** - ================== - [..] The 14 interrupts can be divided on 4 groups: - - (+) Transmit interrupt - - (++) CAN_IT_TME : Transmit mailbox empty Interrupt - if enabled, this interrupt source is pending when - no transmit request are pending for Tx mailboxes. - - (+) Receive Interrupts - - (++) CAN_IT_FMP0, - (++) CAN_IT_FMP1 : FIFO 0 and FIFO1 message pending Interrupts - if enabled, these interrupt sources are pending - when messages are pending in the receive FIFO. - The corresponding interrupt pending bits are cleared - only by hardware. - - (++) CAN_IT_FF0, - (++) CAN_IT_FF1 : FIFO 0 and FIFO1 full Interrupts - if enabled, these interrupt sources are pending - when three messages are stored in the selected FIFO. - - (++) CAN_IT_FOV0, - (++) CAN_IT_FOV1 : FIFO 0 and FIFO1 overrun Interrupts - if enabled, these interrupt sources are pending - when a new message has been received and passed - the filter while the FIFO was full. - - (+) Operating Mode Interrupts - - (++) CAN_IT_WKU : Wake-up Interrupt - if enabled, this interrupt source is pending when - a SOF bit has been detected while the CAN hardware - was in Sleep mode. - - (++) CAN_IT_SLK : Sleep acknowledge Interrupt - if enabled, this interrupt source is pending when - the CAN has entered Sleep Mode. - - (+) Error Interrupts - - (++) CAN_IT_EWG : Error warning Interrupt - if enabled, this interrupt source is pending when - the warning limit has been reached (Receive Error - Counter or Transmit Error Counter=96). - - (++) CAN_IT_EPV : Error passive Interrupt - if enabled, this interrupt source is pending when - the Error Passive limit has been reached (Receive - Error Counter or Transmit Error Counter>127). - - (++) CAN_IT_BOF : Bus-off Interrupt - if enabled, this interrupt source is pending when - CAN enters the bus-off state. The bus-off state is - entered on TEC overflow, greater than 255. - This Flag is cleared only by hardware. - - (++) CAN_IT_LEC : Last error code Interrupt - if enabled, this interrupt source is pending when - a message has been transferred (reception or - transmission) with error, and the error code is hold. - - (++) CAN_IT_ERR : Error Interrupt - if enabled, this interrupt source is pending when - an error condition is pending. - - [..] Managing the CAN controller events : - - The user should identify which mode will be used in his application to - manage the CAN controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) CAN_GetFlagStatus() : to check if flags events occur. - (++) CAN_ClearFlag() : to clear the flags events. - - - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) CAN_ITConfig() : to enable or disable the interrupt source. - (++) CAN_GetITStatus() : to check if Interrupt occurs. - (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@@- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts - pending bits since there are cleared only by hardware. - -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified CANx interrupts. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @param NewState: new state of the CAN interrupts. - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CANx interrupt */ - CANx->IER |= CAN_IT; - } - else - { - /* Disable the selected CANx interrupt */ - CANx->IER &= ~CAN_IT; - } -} -/** - * @brief Checks whether the specified CAN flag is set or not. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval The new state of CAN_FLAG (SET or RESET). - */ -FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_GET_FLAG(CAN_FLAG)); - - - if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET) - { - /* Check the status of the specified CAN flag */ - if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */ - { - /* Check the status of the specified CAN flag */ - if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) - { - /* CAN_FLAG is set */ - bitstatus = SET; - } - else - { - /* CAN_FLAG is reset */ - bitstatus = RESET; - } - } - /* Return the CAN_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the CAN's pending flags. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag - * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag - * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_LEC: Last error code Flag - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG) -{ - uint32_t flagtmp=0; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG)); - - if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */ - { - /* Clear the selected CAN flags */ - CANx->ESR = (uint32_t)RESET; - } - else /* MSR or TSR or RF0R or RF1R */ - { - flagtmp = CAN_FLAG & 0x000FFFFF; - - if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF0R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET) - { - /* Receive Flags */ - CANx->RF1R = (uint32_t)(flagtmp); - } - else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET) - { - /* Transmit Flags */ - CANx->TSR = (uint32_t)(flagtmp); - } - else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */ - { - /* Operating mode Flags */ - CANx->MSR = (uint32_t)(flagtmp); - } - } -} - -/** - * @brief Checks whether the specified CANx interrupt has occurred or not. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_IT: specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval The current state of CAN_IT (SET or RESET). - */ -ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - ITStatus itstatus = RESET; - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_IT(CAN_IT)); - - /* check the interrupt enable bit */ - if((CANx->IER & CAN_IT) != RESET) - { - /* in case the Interrupt is enabled, .... */ - switch (CAN_IT) - { - case CAN_IT_TME: - /* Check CAN_TSR_RQCPx bits */ - itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2); - break; - case CAN_IT_FMP0: - /* Check CAN_RF0R_FMP0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0); - break; - case CAN_IT_FF0: - /* Check CAN_RF0R_FULL0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0); - break; - case CAN_IT_FOV0: - /* Check CAN_RF0R_FOVR0 bit */ - itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0); - break; - case CAN_IT_FMP1: - /* Check CAN_RF1R_FMP1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1); - break; - case CAN_IT_FF1: - /* Check CAN_RF1R_FULL1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1); - break; - case CAN_IT_FOV1: - /* Check CAN_RF1R_FOVR1 bit */ - itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1); - break; - case CAN_IT_WKU: - /* Check CAN_MSR_WKUI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI); - break; - case CAN_IT_SLK: - /* Check CAN_MSR_SLAKI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI); - break; - case CAN_IT_EWG: - /* Check CAN_ESR_EWGF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF); - break; - case CAN_IT_EPV: - /* Check CAN_ESR_EPVF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF); - break; - case CAN_IT_BOF: - /* Check CAN_ESR_BOFF bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF); - break; - case CAN_IT_LEC: - /* Check CAN_ESR_LEC bit */ - itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC); - break; - case CAN_IT_ERR: - /* Check CAN_MSR_ERRI bit */ - itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); - break; - default: - /* in case of error, return RESET */ - itstatus = RESET; - break; - } - } - else - { - /* in case the Interrupt is not enabled, return RESET */ - itstatus = RESET; - } - - /* Return the CAN_IT status */ - return itstatus; -} - -/** - * @brief Clears the CANx's interrupt pending bits. - * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral. - * @param CAN_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty Interrupt - * @arg CAN_IT_FF0: FIFO 0 full Interrupt - * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt - * @arg CAN_IT_FF1: FIFO 1 full Interrupt - * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt - * @arg CAN_IT_WKU: Wake-up Interrupt - * @arg CAN_IT_SLK: Sleep acknowledge Interrupt - * @arg CAN_IT_EWG: Error warning Interrupt - * @arg CAN_IT_EPV: Error passive Interrupt - * @arg CAN_IT_BOF: Bus-off Interrupt - * @arg CAN_IT_LEC: Last error code Interrupt - * @arg CAN_IT_ERR: Error Interrupt - * @note CAN3 peripheral is available only for STM32F413_423xx devices - * @retval None - */ -void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT) -{ - /* Check the parameters */ - assert_param(IS_CAN_ALL_PERIPH(CANx)); - assert_param(IS_CAN_CLEAR_IT(CAN_IT)); - - switch (CAN_IT) - { - case CAN_IT_TME: - /* Clear CAN_TSR_RQCPx (rc_w1)*/ - CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2; - break; - case CAN_IT_FF0: - /* Clear CAN_RF0R_FULL0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FULL0; - break; - case CAN_IT_FOV0: - /* Clear CAN_RF0R_FOVR0 (rc_w1)*/ - CANx->RF0R = CAN_RF0R_FOVR0; - break; - case CAN_IT_FF1: - /* Clear CAN_RF1R_FULL1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FULL1; - break; - case CAN_IT_FOV1: - /* Clear CAN_RF1R_FOVR1 (rc_w1)*/ - CANx->RF1R = CAN_RF1R_FOVR1; - break; - case CAN_IT_WKU: - /* Clear CAN_MSR_WKUI (rc_w1)*/ - CANx->MSR = CAN_MSR_WKUI; - break; - case CAN_IT_SLK: - /* Clear CAN_MSR_SLAKI (rc_w1)*/ - CANx->MSR = CAN_MSR_SLAKI; - break; - case CAN_IT_EWG: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_EPV: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_BOF: - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ - break; - case CAN_IT_LEC: - /* Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - break; - case CAN_IT_ERR: - /*Clear LEC bits */ - CANx->ESR = RESET; - /* Clear CAN_MSR_ERRI (rc_w1) */ - CANx->MSR = CAN_MSR_ERRI; - /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/ - break; - default: - break; - } -} - /** - * @} - */ - -/** - * @brief Checks whether the CAN interrupt has occurred or not. - * @param CAN_Reg: specifies the CAN interrupt register to check. - * @param It_Bit: specifies the interrupt source bit to check. - * @retval The new state of the CAN Interrupt (SET or RESET). - */ -static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) -{ - ITStatus pendingbitstatus = RESET; - - if ((CAN_Reg & It_Bit) != (uint32_t)RESET) - { - /* CAN_IT is set */ - pendingbitstatus = SET; - } - else - { - /* CAN_IT is reset */ - pendingbitstatus = RESET; - } - return pendingbitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c deleted file mode 100644 index de0148eaa..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c +++ /dev/null @@ -1,133 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_crc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides all the CRC firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_crc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRC - * @brief CRC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Resets the CRC Data register (DR). - * @param None - * @retval None - */ -void CRC_ResetDR(void) -{ - /* Reset CRC generator */ - CRC->CR = CRC_CR_RESET; -} - -/** - * @brief Computes the 32-bit CRC of a given data word(32-bit). - * @param Data: data word(32-bit) to compute its CRC - * @retval 32-bit CRC - */ -uint32_t CRC_CalcCRC(uint32_t Data) -{ - CRC->DR = Data; - - return (CRC->DR); -} - -/** - * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed - * @retval 32-bit CRC - */ -uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index = 0; - - for(index = 0; index < BufferLength; index++) - { - CRC->DR = pBuffer[index]; - } - return (CRC->DR); -} - -/** - * @brief Returns the current CRC value. - * @param None - * @retval 32-bit CRC - */ -uint32_t CRC_GetCRC(void) -{ - return (CRC->DR); -} - -/** - * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param IDValue: 8-bit value to be stored in the ID register - * @retval None - */ -void CRC_SetIDRegister(uint8_t IDValue) -{ - CRC->IDR = IDValue; -} - -/** - * @brief Returns the 8-bit data stored in the Independent Data(ID) register - * @param None - * @retval 8-bit value of the ID register - */ -uint8_t CRC_GetIDRegister(void) -{ - return (CRC->IDR); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c deleted file mode 100644 index be75b7120..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c +++ /dev/null @@ -1,934 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Cryptographic processor (CRYP) peripheral: - * + Initialization and Configuration functions - * + Data treatment functions - * + Context swapping functions - * + DMA interface function - * + Interrupts and flags management - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable the CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Initialize the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed - CRYP_IVInit(). - - (#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function. - - (#) Enable the CRYP controller using the CRYP_Cmd() function. - - (#) If using DMA for Data input and output transfer, activate the needed DMA - Requests using CRYP_DMACmd() function - - (#) If DMA is not used for data transfer, use CRYP_DataIn() and CRYP_DataOut() - functions to enter data to IN FIFO and get result from OUT FIFO. - - (#) To control CRYP events you can use one of the following two methods: - (++) Check on CRYP flags using the CRYP_GetFlagStatus() function. - (++) Use CRYP interrupts through the function CRYP_ITConfig() at - initialization phase and CRYP_GetITStatus() function into interrupt - routines in processing phase. - - (#) Save and restore Cryptographic processor context using CRYP_SaveContext() - and CRYP_RestoreContext() functions. - - - *** Procedure to perform an encryption or a decryption *** - ========================================================== - - *** Initialization *** - ====================== - [..] - (#) Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and CRYP_IVInit - functions: - (++) Configure the key size (128-, 192- or 256-bit, in the AES only) - (++) Enter the symmetric key - (++) Configure the data type - (++) In case of decryption in AES-ECB or AES-CBC, you must prepare - the key: configure the key preparation mode. Then Enable the CRYP - peripheral using CRYP_Cmd() function: the BUSY flag is set. - Wait until BUSY flag is reset : the key is prepared for decryption - (++) Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the - AES in ECB/CBC/CTR) - (++) Configure the direction (encryption/decryption). - (++) Write the initialization vectors (in CBC or CTR modes only) - - (#) Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function - - - *** Basic Processing mode (polling mode) *** - ============================================ - [..] - (#) Enable the cryptographic processor using CRYP_Cmd() function. - - (#) Write the first blocks in the input FIFO (2 to 8 words) using - CRYP_DataIn() function. - - (#) Repeat the following sequence until the complete message has been - processed: - - (++) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() - function), then read the OUT-FIFO using CRYP_DataOut() function - (1 block or until the FIFO is empty) - - (++) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() - function then write the IN FIFO using CRYP_DataIn() function - (1 block or until the FIFO is full) - - (#) At the end of the processing, CRYP_FLAG_BUSY flag will be reset and - both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is - reset). You can disable the peripheral using CRYP_Cmd() function. - - *** Interrupts Processing mode *** - ================================== - [..] In this mode, Processing is done when the data are transferred by the - CPU during interrupts. - - (#) Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using CRYP_ITConfig() - function. - - (#) Enable the cryptographic processor using CRYP_Cmd() function. - - (#) In the CRYP_IT_INI interrupt handler : load the input message into the - IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a - time, or load data until the IN FIFO is full. When the last word of - the message has been entered into the IN FIFO, disable the CRYP_IT_INI - interrupt (using CRYP_ITConfig() function). - - (#) In the CRYP_IT_OUTI interrupt handler : read the output message from - the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or - 4 words) at a time or read data until the FIFO is empty. - When the last word has been read, INIM=0, BUSY=0 and both FIFOs are - empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). - You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() - function) and you can disable the peripheral using CRYP_Cmd() function. - - *** DMA Processing mode *** - =========================== - [..] In this mode, Processing is done when the DMA is used to transfer the - data from/to the memory. - - (#) Configure the DMA controller to transfer the input data from the - memory using DMA_Init() function. - The transfer length is the length of the message. - As message padding is not managed by the peripheral, the message - length must be an entire number of blocks. The data are transferred - in burst mode. The burst length is 4 words in the AES and 2 or 4 - words in the DES/TDES. The DMA should be configured to set an - interrupt on transfer completion of the output data to indicate that - the processing is finished. - Refer to DMA peripheral driver for more details. - - (#) Enable the cryptographic processor using CRYP_Cmd() function. - Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT - using CRYP_DMACmd() function. - - (#) All the transfers and processing are managed by the DMA and the - cryptographic processor. The DMA transfer complete interrupt indicates - that the processing is complete. Both FIFOs are normally empty and - CRYP_FLAG_BUSY flag is reset. - - @endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define FLAG_MASK ((uint8_t)0x20) -#define MAX_TIMEOUT ((uint16_t)0xFFFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the cryptographic Processor using CRYP_Init() function - (++) Encrypt or Decrypt - (++) mode : TDES-ECB, TDES-CBC, - DES-ECB, DES-CBC, - AES-ECB, AES-CBC, AES-CTR, AES-Key, AES-GCM, AES-CCM - (++) DataType : 32-bit data, 16-bit data, bit data or bit-string - (++) Key Size (only in AES modes) - (+) Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function - (+) Configure the Initialization Vectors(IV) for CBC and CTR modes using - CRYP_IVInit() function. - (+) Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function. - (+) Enable or disable the CRYP Processor using CRYP_Cmd() function - -@endverbatim - * @{ - */ -/** - * @brief Deinitializes the CRYP peripheral registers to their default reset values - * @param None - * @retval None - */ -void CRYP_DeInit(void) -{ - /* Enable CRYP reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE); - - /* Release CRYP from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE); -} - -/** - * @brief Initializes the CRYP peripheral according to the specified parameters - * in the CRYP_InitStruct. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains - * the configuration information for the CRYP peripheral. - * @retval None - */ -void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode)); - assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType)); - assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir)); - - /* Select Algorithm mode*/ - CRYP->CR &= ~CRYP_CR_ALGOMODE; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode; - - /* Select dataType */ - CRYP->CR &= ~CRYP_CR_DATATYPE; - CRYP->CR |= CRYP_InitStruct->CRYP_DataType; - - /* select Key size (used only with AES algorithm) */ - if ((CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_ECB) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_TDES_CBC) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_ECB) && - (CRYP_InitStruct->CRYP_AlgoMode != CRYP_AlgoMode_DES_CBC)) - { - assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize)); - CRYP->CR &= ~CRYP_CR_KEYSIZE; - CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be - configured once the key has - been prepared */ - } - - /* Select data Direction */ - CRYP->CR &= ~CRYP_CR_ALGODIR; - CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir; -} - -/** - * @brief Fills each CRYP_InitStruct member with its default value. - * @param CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct) -{ - /* Initialize the CRYP_AlgoDir member */ - CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - - /* initialize the CRYP_AlgoMode member */ - CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - - /* initialize the CRYP_DataType member */ - CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b; - - /* Initialize the CRYP_KeySize member */ - CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b; -} - -/** - * @brief Initializes the CRYP Keys according to the specified parameters in - * the CRYP_KeyInitStruct. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - /* Key Initialisation */ - CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; -} - -/** - * @brief Fills each CRYP_KeyInitStruct member with its default value. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure - * which will be initialized. - * @retval None - */ -void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - CRYP_KeyInitStruct->CRYP_Key0Left = 0; - CRYP_KeyInitStruct->CRYP_Key0Right = 0; - CRYP_KeyInitStruct->CRYP_Key1Left = 0; - CRYP_KeyInitStruct->CRYP_Key1Right = 0; - CRYP_KeyInitStruct->CRYP_Key2Left = 0; - CRYP_KeyInitStruct->CRYP_Key2Right = 0; - CRYP_KeyInitStruct->CRYP_Key3Left = 0; - CRYP_KeyInitStruct->CRYP_Key3Right = 0; -} -/** - * @brief Initializes the CRYP Initialization Vectors(IV) according to the - * specified parameters in the CRYP_IVInitStruct. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains - * the configuration information for the CRYP Initialization Vectors(IV). - * @retval None - */ -void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left; - CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right; - CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left; - CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right; -} - -/** - * @brief Fills each CRYP_IVInitStruct member with its default value. - * @param CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization - * Vectors(IV) structure which will be initialized. - * @retval None - */ -void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct) -{ - CRYP_IVInitStruct->CRYP_IV0Left = 0; - CRYP_IVInitStruct->CRYP_IV0Right = 0; - CRYP_IVInitStruct->CRYP_IV1Left = 0; - CRYP_IVInitStruct->CRYP_IV1Right = 0; -} - -/** - * @brief Configures the AES-CCM and AES-GCM phases - * @note This function is used only with AES-CCM or AES-GCM Algorithms - * @param CRYP_Phase: specifies the CRYP AES-CCM and AES-GCM phase to be configured. - * This parameter can be one of the following values: - * @arg CRYP_Phase_Init: Initialization phase - * @arg CRYP_Phase_Header: Header phase - * @arg CRYP_Phase_Payload: Payload phase - * @arg CRYP_Phase_Final: Final phase - * @retval None - */ -void CRYP_PhaseConfig(uint32_t CRYP_Phase) -{ uint32_t tempcr = 0; - - /* Check the parameter */ - assert_param(IS_CRYP_PHASE(CRYP_Phase)); - - /* Get the CR register */ - tempcr = CRYP->CR; - - /* Reset the phase configuration bits: GCMP_CCMPH */ - tempcr &= (uint32_t)(~CRYP_CR_GCM_CCMPH); - /* Set the selected phase */ - tempcr |= (uint32_t)CRYP_Phase; - - /* Set the CR register */ - CRYP->CR = tempcr; -} - -/** - * @brief Flushes the IN and OUT FIFOs (that is read and write pointers of the - * FIFOs are reset) - * @note The FIFOs must be flushed only when BUSY flag is reset. - * @param None - * @retval None - */ -void CRYP_FIFOFlush(void) -{ - /* Reset the read and write pointers of the FIFOs */ - CRYP->CR |= CRYP_CR_FFLUSH; -} - -/** - * @brief Enables or disables the CRYP peripheral. - * @param NewState: new state of the CRYP peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; - } - else - { - /* Disable the Cryptographic processor */ - CRYP->CR &= ~CRYP_CR_CRYPEN; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group2 CRYP Data processing functions - * @brief CRYP Data processing functions - * -@verbatim - =============================================================================== - ##### CRYP Data processing functions ##### - =============================================================================== - [..] This section provides functions allowing the encryption and decryption - operations: - (+) Enter data to be treated in the IN FIFO : using CRYP_DataIn() function. - (+) Get the data result from the OUT FIFO : using CRYP_DataOut() function. - -@endverbatim - * @{ - */ - -/** - * @brief Writes data in the Data Input register (DIN). - * @note After the DIN register has been read once or several times, - * the FIFO must be flushed (using CRYP_FIFOFlush() function). - * @param Data: data to write in Data Input register - * @retval None - */ -void CRYP_DataIn(uint32_t Data) -{ - CRYP->DR = Data; -} - -/** - * @brief Returns the last data entered into the output FIFO. - * @param None - * @retval Last data entered into the output FIFO. - */ -uint32_t CRYP_DataOut(void) -{ - return CRYP->DOUT; -} -/** - * @} - */ - -/** @defgroup CRYP_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - ##### Context swapping functions ##### - =============================================================================== - [..] This section provides functions allowing to save and store CRYP Context - - [..] It is possible to interrupt an encryption/ decryption/ key generation process - to perform another processing with a higher priority, and to complete the - interrupted process later on, when the higher-priority task is complete. To do - so, the context of the interrupted task must be saved from the CRYP registers - to memory, and then be restored from memory to the CRYP registers. - - (#) To save the current context, use CRYP_SaveContext() function - (#) To restore the saved context, use CRYP_RestoreContext() function - -@endverbatim - * @{ - */ - -/** - * @brief Saves the CRYP peripheral Context. - * @note This function stops DMA transfer before to save the context. After - * restoring the context, you have to enable the DMA again (if the DMA - * was previously used). - * @param CRYP_ContextSave: pointer to a CRYP_Context structure that contains - * the repository for current context. - * @param CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that - * contains the configuration information for the CRYP Keys. - * @retval None - */ -ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave, - CRYP_KeyInitTypeDef* CRYP_KeyInitStruct) -{ - __IO uint32_t timeout = 0; - uint32_t ckeckmask = 0, bitstatus; - ErrorStatus status = ERROR; - - /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */ - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN; - - /* Wait until both the IN and OUT FIFOs are empty - (IFEM=1 and OFNE=0 in the CRYP_SR register) and the - BUSY bit is cleared. */ - - if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY ; - } - else /* AES or DES */ - { - ckeckmask = CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE; - } - - do - { - bitstatus = CRYP->SR & ckeckmask; - timeout++; - } - while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM)); - - if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM) - { - status = ERROR; - } - else - { - /* Stop DMA transfers on the OUT FIFO by - - writing the DOEN bit to 0 in the CRYP_DMACR register - - and clear the CRYPEN bit. */ - - CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN; - CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN; - - /* Save the current configuration (bit 19, bit[17:16] and bits [9:2] in the CRYP_CR register) */ - CRYP_ContextSave->CR_CurrentConfig = CRYP->CR & (CRYP_CR_GCM_CCMPH | - CRYP_CR_KEYSIZE | - CRYP_CR_DATATYPE | - CRYP_CR_ALGOMODE | - CRYP_CR_ALGODIR); - - /* and, if not in ECB mode, the initialization vectors. */ - CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR; - CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR; - CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR; - CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR; - - /* save The key value */ - CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; - CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; - CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; - CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; - CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; - CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; - CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; - CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; - - /* Save the content of context swap registers */ - CRYP_ContextSave->CRYP_CSGCMCCMR[0] = CRYP->CSGCMCCM0R; - CRYP_ContextSave->CRYP_CSGCMCCMR[1] = CRYP->CSGCMCCM1R; - CRYP_ContextSave->CRYP_CSGCMCCMR[2] = CRYP->CSGCMCCM2R; - CRYP_ContextSave->CRYP_CSGCMCCMR[3] = CRYP->CSGCMCCM3R; - CRYP_ContextSave->CRYP_CSGCMCCMR[4] = CRYP->CSGCMCCM4R; - CRYP_ContextSave->CRYP_CSGCMCCMR[5] = CRYP->CSGCMCCM5R; - CRYP_ContextSave->CRYP_CSGCMCCMR[6] = CRYP->CSGCMCCM6R; - CRYP_ContextSave->CRYP_CSGCMCCMR[7] = CRYP->CSGCMCCM7R; - - CRYP_ContextSave->CRYP_CSGCMR[0] = CRYP->CSGCM0R; - CRYP_ContextSave->CRYP_CSGCMR[1] = CRYP->CSGCM1R; - CRYP_ContextSave->CRYP_CSGCMR[2] = CRYP->CSGCM2R; - CRYP_ContextSave->CRYP_CSGCMR[3] = CRYP->CSGCM3R; - CRYP_ContextSave->CRYP_CSGCMR[4] = CRYP->CSGCM4R; - CRYP_ContextSave->CRYP_CSGCMR[5] = CRYP->CSGCM5R; - CRYP_ContextSave->CRYP_CSGCMR[6] = CRYP->CSGCM6R; - CRYP_ContextSave->CRYP_CSGCMR[7] = CRYP->CSGCM7R; - - /* When needed, save the DMA status (pointers for IN and OUT messages, - number of remaining bytes, etc.) */ - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Restores the CRYP peripheral Context. - * @note Since the DMA transfer is stopped in CRYP_SaveContext() function, - * after restoring the context, you have to enable the DMA again (if the - * DMA was previously used). - * @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains - * the repository for saved context. - * @note The data that were saved during context saving must be rewritten into - * the IN FIFO. - * @retval None - */ -void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore) -{ - - /* Configure the processor with the saved configuration */ - CRYP->CR = CRYP_ContextRestore->CR_CurrentConfig; - - /* restore The key value */ - CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; - CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR; - CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR; - CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR; - CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR; - CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR; - CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR; - CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR; - - /* and the initialization vectors. */ - CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR; - CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR; - CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR; - CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR; - - /* Restore the content of context swap registers */ - CRYP->CSGCMCCM0R = CRYP_ContextRestore->CRYP_CSGCMCCMR[0]; - CRYP->CSGCMCCM1R = CRYP_ContextRestore->CRYP_CSGCMCCMR[1]; - CRYP->CSGCMCCM2R = CRYP_ContextRestore->CRYP_CSGCMCCMR[2]; - CRYP->CSGCMCCM3R = CRYP_ContextRestore->CRYP_CSGCMCCMR[3]; - CRYP->CSGCMCCM4R = CRYP_ContextRestore->CRYP_CSGCMCCMR[4]; - CRYP->CSGCMCCM5R = CRYP_ContextRestore->CRYP_CSGCMCCMR[5]; - CRYP->CSGCMCCM6R = CRYP_ContextRestore->CRYP_CSGCMCCMR[6]; - CRYP->CSGCMCCM7R = CRYP_ContextRestore->CRYP_CSGCMCCMR[7]; - - CRYP->CSGCM0R = CRYP_ContextRestore->CRYP_CSGCMR[0]; - CRYP->CSGCM1R = CRYP_ContextRestore->CRYP_CSGCMR[1]; - CRYP->CSGCM2R = CRYP_ContextRestore->CRYP_CSGCMR[2]; - CRYP->CSGCM3R = CRYP_ContextRestore->CRYP_CSGCMR[3]; - CRYP->CSGCM4R = CRYP_ContextRestore->CRYP_CSGCMR[4]; - CRYP->CSGCM5R = CRYP_ContextRestore->CRYP_CSGCMR[5]; - CRYP->CSGCM6R = CRYP_ContextRestore->CRYP_CSGCMR[6]; - CRYP->CSGCM7R = CRYP_ContextRestore->CRYP_CSGCMR[7]; - - /* Enable the cryptographic processor */ - CRYP->CR |= CRYP_CR_CRYPEN; -} -/** - * @} - */ - -/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function - * @brief CRYP's DMA interface Configuration function - * -@verbatim - =============================================================================== - ##### CRYP's DMA interface Configuration function ##### - =============================================================================== - [..] This section provides functions allowing to configure the DMA interface for - CRYP data input and output transfer. - - [..] When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be - transferred: - (+) From memory to the CRYP IN FIFO using the DMA peripheral by enabling - the CRYP_DMAReq_DataIN request. - (+) From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling - the CRYP_DMAReq_DataOUT request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRYP DMA interface. - * @param CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer - * @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer - * @param NewState: new state of the selected CRYP DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP DMA request */ - CRYP->DMACR |= CRYP_DMAReq; - } - else - { - /* Disable the selected CRYP DMA request */ - CRYP->DMACR &= (uint8_t)~CRYP_DMAReq; - } -} -/** - * @} - */ - -/** @defgroup CRYP_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the CRYP Interrupts and - to get the status and Interrupts pending bits. - - [..] The CRYP provides 2 Interrupts sources and 7 Flags: - - *** Flags : *** - =============== - [..] - (#) CRYP_FLAG_IFEM : Set when Input FIFO is empty. This Flag is cleared only - by hardware. - - (#) CRYP_FLAG_IFNF : Set when Input FIFO is not full. This Flag is cleared - only by hardware. - - - (#) CRYP_FLAG_INRIS : Set when Input FIFO Raw interrupt is pending it gives - the raw interrupt state prior to masking of the input FIFO service interrupt. - This Flag is cleared only by hardware. - - (#) CRYP_FLAG_OFNE : Set when Output FIFO not empty. This Flag is cleared - only by hardware. - - (#) CRYP_FLAG_OFFU : Set when Output FIFO is full. This Flag is cleared only - by hardware. - - (#) CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending it gives - the raw interrupt state prior to masking of the output FIFO service interrupt. - This Flag is cleared only by hardware. - - (#) CRYP_FLAG_BUSY : Set when the CRYP core is currently processing a block - of data or a key preparation (for AES decryption). This Flag is cleared - only by hardware. To clear it, the CRYP core must be disabled and the last - processing has completed. - - *** Interrupts : *** - ==================== - [..] - (#) CRYP_IT_INI : The input FIFO service interrupt is asserted when there - are less than 4 words in the input FIFO. This interrupt is associated to - CRYP_FLAG_INRIS flag. - - -@- This interrupt is cleared by performing write operations to the input FIFO - until it holds 4 or more words. The input FIFO service interrupt INMIS is - enabled with the CRYP enable bit. Consequently, when CRYP is disabled, the - INMIS signal is low even if the input FIFO is empty. - - - - (#) CRYP_IT_OUTI : The output FIFO service interrupt is asserted when there - is one or more (32-bit word) data items in the output FIFO. This interrupt - is associated to CRYP_FLAG_OUTRIS flag. - - -@- This interrupt is cleared by reading data from the output FIFO until there - is no valid (32-bit) word left (that is, the interrupt follows the state - of the OFNE (output FIFO not empty) flag). - - *** Managing the CRYP controller events : *** - ============================================= - [..] The user should identify which mode will be used in his application to manage - the CRYP controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) CRYP_GetFlagStatus() : to check if flags events occur. - - -@@- The CRYPT flags do not need to be cleared since they are cleared as - soon as the associated event are reset. - - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) CRYP_ITConfig() : to enable or disable the interrupt source. - (++) CRYP_GetITStatus() : to check if Interrupt occurs. - - -@@- The CRYPT interrupts have no pending bits, the interrupt is cleared as - soon as the associated event is reset. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified CRYP interrupts. - * @param CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @param NewState: new state of the specified CRYP interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_CRYP_CONFIG_IT(CRYP_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected CRYP interrupt */ - CRYP->IMSCR |= CRYP_IT; - } - else - { - /* Disable the selected CRYP interrupt */ - CRYP->IMSCR &= (uint8_t)~CRYP_IT; - } -} - -/** - * @brief Checks whether the specified CRYP interrupt has occurred or not. - * @note This function checks the status of the masked interrupt (i.e the - * interrupt should be previously enabled). - * @param CRYP_IT: specifies the CRYP (masked) interrupt source to check. - * This parameter can be one of the following values: - * @arg CRYP_IT_INI: Input FIFO interrupt - * @arg CRYP_IT_OUTI: Output FIFO interrupt - * @retval The new state of CRYP_IT (SET or RESET). - */ -ITStatus CRYP_GetITStatus(uint8_t CRYP_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_CRYP_GET_IT(CRYP_IT)); - - /* Check the status of the specified CRYP interrupt */ - if ((CRYP->MISR & CRYP_IT) != (uint8_t)RESET) - { - /* CRYP_IT is set */ - bitstatus = SET; - } - else - { - /* CRYP_IT is reset */ - bitstatus = RESET; - } - /* Return the CRYP_IT status */ - return bitstatus; -} - -/** - * @brief Returns whether CRYP peripheral is enabled or disabled. - * @param none. - * @retval Current state of the CRYP peripheral (ENABLE or DISABLE). - */ -FunctionalState CRYP_GetCmdStatus(void) -{ - FunctionalState state = DISABLE; - - if ((CRYP->CR & CRYP_CR_CRYPEN) != 0) - { - /* CRYPEN bit is set */ - state = ENABLE; - } - else - { - /* CRYPEN bit is reset */ - state = DISABLE; - } - return state; -} - -/** - * @brief Checks whether the specified CRYP flag is set or not. - * @param CRYP_FLAG: specifies the CRYP flag to check. - * This parameter can be one of the following values: - * @arg CRYP_FLAG_IFEM: Input FIFO Empty flag. - * @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag. - * @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag. - * @arg CRYP_FLAG_OFFU: Output FIFO Full flag. - * @arg CRYP_FLAG_BUSY: Busy flag. - * @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag. - * @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag. - * @retval The new state of CRYP_FLAG (SET or RESET). - */ -FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG)); - - /* check if the FLAG is in RISR register */ - if ((CRYP_FLAG & FLAG_MASK) != 0x00) - { - tempreg = CRYP->RISR; - } - else /* The FLAG is in SR register */ - { - tempreg = CRYP->SR; - } - - - /* Check the status of the specified CRYP flag */ - if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET) - { - /* CRYP_FLAG is set */ - bitstatus = SET; - } - else - { - /* CRYP_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the CRYP_FLAG status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c deleted file mode 100644 index c02fef76e..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c +++ /dev/null @@ -1,1707 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp_aes.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using AES in ECB/CBC/CTR/GCM/CCM modes. - * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP - * peripheral. - * AES-ECB/CBC/CTR/GCM/CCM modes are available on STM32F437x Devices. - * For STM32F41xx Devices, only AES-ECB/CBC/CTR modes are available. - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB() function. - - (#) Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC() function. - - (#) Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR() function. - - (#) Encrypt and decrypt using AES in GCM Mode using CRYP_AES_GCM() function. - - (#) Encrypt and decrypt using AES in CCM Mode using CRYP_AES_CCM() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define AESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group6 High Level AES functions - * @brief High Level AES functions - * -@verbatim - =============================================================================== - ##### High Level AES functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using AES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer, must be a multiple of 16. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize, - uint8_t* Input, uint32_t Ilength, uint8_t* Output) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /*------------------ AES Decryption ------------------*/ - if(Mode == MODE_DECRYPT) /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* wait until the Busy flag is RESET */ - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Crypto Init for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - } - /*------------------ AES Encryption ------------------*/ - else /* AES encryption */ - { - - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(i=0; ((i>32)); - CRYP_DataIn(__REV(headerlength)); - CRYP_DataIn(__REV(inputlength>>32)); - CRYP_DataIn(__REV(inputlength)); - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - tagaddr = (uint32_t)AuthTAG; - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - } - /*------------------ AES Decryption ------------------*/ - else /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_GCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - - /***************************** header phase *******************************/ - if(HLength != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < HLength); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - /* Write number of bits concatenated with header in the IN FIFO */ - CRYP_DataIn(__REV(headerlength>>32)); - CRYP_DataIn(__REV(headerlength)); - CRYP_DataIn(__REV(inputlength>>32)); - CRYP_DataIn(__REV(inputlength)); - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - tagaddr = (uint32_t)AuthTAG; - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - *(uint32_t*)(tagaddr) = CRYP_DataOut(); - tagaddr+=4; - } - /* Disable Crypto */ - CRYP_Cmd(DISABLE); - - return status; -} - -/** - * @brief Encrypt and decrypt using AES in CCM Mode. The GCM and CCM modes - * are available only on STM32F437x Devices. - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Nonce: the nonce used for AES algorithm. It shall be unique for each processing. - * @param Key: Key used for AES algorithm. - * @param Keysize: length of the Key, must be a 128, 192 or 256. - * @param Input: pointer to the Input buffer. - * @param Ilength: length of the Input buffer in bytes, must be a multiple of 16. - * @param Header: pointer to the header buffer. - * @param Hlength: length of the header buffer in bytes. - * @param HBuffer: pointer to temporary buffer used to append the header - * HBuffer size must be equal to Hlength + 21 - * @param Output: pointer to the returned buffer. - * @param AuthTAG: pointer to the authentication TAG buffer. - * @param TAGSize: the size of the TAG (called also MAC). - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_AES_CCM(uint8_t Mode, - uint8_t* Nonce, uint32_t NonceSize, - uint8_t *Key, uint16_t Keysize, - uint8_t *Input, uint32_t ILength, - uint8_t *Header, uint32_t HLength, uint8_t *HBuffer, - uint8_t *Output, - uint8_t *AuthTAG, uint32_t TAGSize) -{ - CRYP_InitTypeDef AES_CRYP_InitStructure; - CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; - CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t headeraddr = (uint32_t)Header; - uint32_t tagaddr = (uint32_t)AuthTAG; - uint32_t headersize = HLength; - uint32_t loopcounter = 0; - uint32_t bufferidx = 0; - uint8_t blockb0[16] = {0};/* Block B0 */ - uint8_t ctr[16] = {0}; /* Counter */ - uint32_t temptag[4] = {0}; /* temporary TAG (MAC) */ - uint32_t ctraddr = (uint32_t)ctr; - uint32_t b0addr = (uint32_t)blockb0; - - /************************ Formatting the header block ***********************/ - if(headersize != 0) - { - /* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */ - if(headersize < 65280) - { - HBuffer[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF); - HBuffer[bufferidx++] = (uint8_t) ((headersize) & 0xFF); - headersize += 2; - } - else - { - /* header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */ - HBuffer[bufferidx++] = 0xFF; - HBuffer[bufferidx++] = 0xFE; - HBuffer[bufferidx++] = headersize & 0xff000000; - HBuffer[bufferidx++] = headersize & 0x00ff0000; - HBuffer[bufferidx++] = headersize & 0x0000ff00; - HBuffer[bufferidx++] = headersize & 0x000000ff; - headersize += 6; - } - /* Copy the header buffer in internal buffer "HBuffer" */ - for(loopcounter = 0; loopcounter < headersize; loopcounter++) - { - HBuffer[bufferidx++] = Header[loopcounter]; - } - /* Check if the header size is modulo 16 */ - if ((headersize % 16) != 0) - { - /* Padd the header buffer with 0s till the HBuffer length is modulo 16 */ - for(loopcounter = headersize; loopcounter <= ((headersize/16) + 1) * 16; loopcounter++) - { - HBuffer[loopcounter] = 0; - } - /* Set the header size to modulo 16 */ - headersize = ((headersize/16) + 1) * 16; - } - /* set the pointer headeraddr to HBuffer */ - headeraddr = (uint32_t)HBuffer; - } - /************************* Formatting the block B0 **************************/ - if(headersize != 0) - { - blockb0[0] = 0x40; - } - /* Flags byte */ - blockb0[0] |= 0u | (((( (uint8_t) TAGSize - 2) / 2) & 0x07 ) << 3 ) | ( ( (uint8_t) (15 - NonceSize) - 1) & 0x07); - - for (loopcounter = 0; loopcounter < NonceSize; loopcounter++) - { - blockb0[loopcounter+1] = Nonce[loopcounter]; - } - for ( ; loopcounter < 13; loopcounter++) - { - blockb0[loopcounter+1] = 0; - } - - blockb0[14] = ((ILength >> 8) & 0xFF); - blockb0[15] = (ILength & 0xFF); - - /************************* Formatting the initial counter *******************/ - /* Byte 0: - Bits 7 and 6 are reserved and shall be set to 0 - Bits 3, 4, and 5 shall also be set to 0, to ensure that all the counter blocks - are distinct from B0 - Bits 0, 1, and 2 contain the same encoding of q as in B0 - */ - ctr[0] = blockb0[0] & 0x07; - /* byte 1 to NonceSize is the IV (Nonce) */ - for(loopcounter = 1; loopcounter < NonceSize + 1; loopcounter++) - { - ctr[loopcounter] = blockb0[loopcounter]; - } - /* Set the LSB to 1 */ - ctr[15] |= 0x01; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure); - - switch(Keysize) - { - case 128: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 192: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - case 256: - AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b; - AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - break; - default: - break; - } - - /* CRYP Initialization Vectors */ - AES_CRYP_IVInitStructure.CRYP_IV0Left = (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV0Right= (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV1Left = (__REV(*(uint32_t*)(ctraddr))); - ctraddr+=4; - AES_CRYP_IVInitStructure.CRYP_IV1Right= (__REV(*(uint32_t*)(ctraddr))); - - /*------------------ AES Encryption ------------------*/ - if(Mode == MODE_ENCRYPT) /* AES encryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - /***************************** header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - ctraddr = (uint32_t)ctr; - /* Write the counter block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ - CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); - - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Auth TAG in the IN FIFO */ - temptag[0] = CRYP_DataOut(); - temptag[1] = CRYP_DataOut(); - temptag[2] = CRYP_DataOut(); - temptag[3] = CRYP_DataOut(); - } - /*------------------ AES Decryption ------------------*/ - else /* AES decryption */ - { - /* Flush IN/OUT FIFOs */ - CRYP_FIFOFlush(); - - /* Key Initialisation */ - CRYP_KeyInit(&AES_CRYP_KeyInitStructure); - - /* CRYP Initialization Vectors */ - CRYP_IVInit(&AES_CRYP_IVInitStructure); - - /* Crypto Init for Key preparation for decryption process */ - AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_CCM; - AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&AES_CRYP_InitStructure); - - /***************************** Init phase *********************************/ - /* Select init phase */ - CRYP_PhaseConfig(CRYP_Phase_Init); - - b0addr = (uint32_t)blockb0; - /* Write the blockb0 block in the IN FIFO */ - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - b0addr+=4; - CRYP_DataIn((*(uint32_t*)(b0addr))); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - /* Wait for CRYPEN bit to be 0 */ - while(CRYP_GetCmdStatus() == ENABLE) - { - } - - /***************************** header phase *******************************/ - if(headersize != 0) - { - /* Select header phase */ - CRYP_PhaseConfig(CRYP_Phase_Header); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; (loopcounter < headersize); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - CRYP_DataIn(*(uint32_t*)(headeraddr)); - headeraddr+=4; - } - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - } - - /**************************** payload phase *******************************/ - if(ILength != 0) - { - /* Select payload phase */ - CRYP_PhaseConfig(CRYP_Phase_Payload); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - for(loopcounter = 0; ((loopcounter < ILength) && (status != ERROR)); loopcounter+=16) - { - /* Wait until the IFEM flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_IFEM) == RESET) - { - } - - /* Write the Input block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - CRYP_DataIn(*(uint32_t*)(inputaddr)); - inputaddr+=4; - - /* Wait until the complete message has been processed */ - counter = 0; - do - { - busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY); - counter++; - }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET)); - - if (busystatus != RESET) - { - status = ERROR; - } - else - { - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Output block from the Output FIFO */ - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - *(uint32_t*)(outputaddr) = CRYP_DataOut(); - outputaddr+=4; - } - } - } - - /***************************** final phase ********************************/ - /* Select final phase */ - CRYP_PhaseConfig(CRYP_Phase_Final); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - return(ERROR); - } - - ctraddr = (uint32_t)ctr; - /* Write the counter block in the IN FIFO */ - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - CRYP_DataIn(*(uint32_t*)(ctraddr)); - ctraddr+=4; - /* Reset bit 0 (after 8-bit swap) is equivalent to reset bit 24 (before 8-bit swap) */ - CRYP_DataIn(*(uint32_t*)(ctraddr) & 0xfeffffff); - - /* Wait until the OFNE flag is reset */ - while(CRYP_GetFlagStatus(CRYP_FLAG_OFNE) == RESET) - { - } - - /* Read the Authentification TAG (MAC) in the IN FIFO */ - temptag[0] = CRYP_DataOut(); - temptag[1] = CRYP_DataOut(); - temptag[2] = CRYP_DataOut(); - temptag[3] = CRYP_DataOut(); - } - - /* Copy temporary authentication TAG in user TAG buffer */ - for(loopcounter = 0; (loopcounter < TAGSize); loopcounter++) - { - /* Set the authentication TAG buffer */ - *((uint8_t*)tagaddr+loopcounter) = *((uint8_t*)temptag+loopcounter); - } - - /* Disable Crypto */ - CRYP_Cmd(DISABLE); - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c deleted file mode 100644 index c32137b2f..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_cryp_des.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides high level functions to encrypt and decrypt an - * input message using DES in ECB/CBC modes. - * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP - * peripheral. - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The CRYP controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function. - - (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function. - - (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group8 High Level DES functions - * @brief High Level DES functions - * -@verbatim - =============================================================================== - ##### High Level DES functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using DES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for DES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef DES_CRYP_InitStructure; - CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if( Mode == MODE_ENCRYPT ) /* DES encryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */ - { - DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB; - DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&DES_CRYP_InitStructure); - - /* Key Initialisation */ - DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& DES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - status = ERROR; - } - else - { - for(i=0; ((i
© COPYRIGHT 2016 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_cryp.h" - - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup CRYP - * @brief CRYP driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup CRYP_Private_Functions - * @{ - */ - -/** @defgroup CRYP_Group7 High Level TDES functions - * @brief High Level TDES functions - * -@verbatim - =============================================================================== - ##### High Level TDES functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Encrypt and decrypt using TDES in ECB Mode - * @param Mode: encryption or decryption Mode. - * This parameter can be one of the following values: - * @arg MODE_ENCRYPT: Encryption - * @arg MODE_DECRYPT: Decryption - * @param Key: Key used for TDES algorithm. - * @param Ilength: length of the Input buffer, must be a multiple of 8. - * @param Input: pointer to the Input buffer. - * @param Output: pointer to the returned buffer. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Operation done - * - ERROR: Operation failed - */ -ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, - uint32_t Ilength, uint8_t *Output) -{ - CRYP_InitTypeDef TDES_CRYP_InitStructure; - CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t keyaddr = (uint32_t)Key; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - uint32_t i = 0; - - /* Crypto structures initialisation*/ - CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure); - - /* Crypto Init for Encryption process */ - if(Mode == MODE_ENCRYPT) /* TDES encryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt; - } - else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */ - { - TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; - } - - TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB; - TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b; - CRYP_Init(&TDES_CRYP_InitStructure); - - /* Key Initialisation */ - TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr)); - keyaddr+=4; - TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr)); - CRYP_KeyInit(& TDES_CRYP_KeyInitStructure); - - /* Flush IN/OUT FIFO */ - CRYP_FIFOFlush(); - - /* Enable Crypto processor */ - CRYP_Cmd(ENABLE); - - if(CRYP_GetCmdStatus() == DISABLE) - { - /* The CRYP peripheral clock is not enabled or the device doesn't embed - the CRYP peripheral (please check the device sales type. */ - status = ERROR; - } - else - { - for(i=0; ((i
© COPYRIGHT 2016 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dac.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* CR register Mask */ -#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) - -/* DAC Dual Channels SWTRIG masks */ -#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) -#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) - -/* DHR registers offsets */ -#define DHR12R1_OFFSET ((uint32_t)0x00000008) -#define DHR12R2_OFFSET ((uint32_t)0x00000014) -#define DHR12RD_OFFSET ((uint32_t)0x00000020) - -/* DOR register offset */ -#define DOR_OFFSET ((uint32_t)0x0000002C) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/** @defgroup DAC_Group1 DAC channels configuration - * @brief DAC channels configuration: trigger, output buffer, data format - * -@verbatim - =============================================================================== - ##### DAC channels configuration: trigger, output buffer, data format ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param None - * @retval None - */ -void DAC_DeInit(void) -{ - /* Enable DAC reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); - /* Release DAC from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); -} - -/** - * @brief Initializes the DAC peripheral according to the specified parameters - * in the DAC_InitStruct. - * @param DAC_Channel: the selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains - * the configuration information for the specified DAC channel. - * @retval None - */ -void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct) -{ - uint32_t tmpreg1 = 0, tmpreg2 = 0; - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger)); - assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer)); - -/*---------------------------- DAC CR Configuration --------------------------*/ - /* Get the DAC CR value */ - tmpreg1 = DAC->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel); - /* Configure for the selected DAC channel: buffer output, trigger, - wave generation, mask/amplitude for wave generation */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set WAVEx bits according to DAC_WaveGeneration value */ - /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \ - DAC_InitStruct->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << DAC_Channel; - /* Write to DAC CR */ - DAC->CR = tmpreg1; -} - -/** - * @brief Fills each DAC_InitStruct member with its default value. - * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct) -{ -/*--------------- Reset DAC init structure parameters values -----------------*/ - /* Initialize the DAC_Trigger member */ - DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; - /* Initialize the DAC_WaveGeneration member */ - DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; - /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */ - DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; - /* Initialize the DAC_OutputBuffer member */ - DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; -} - -/** - * @brief Enables or disables the specified DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the DAC channel. - * This parameter can be: ENABLE or DISABLE. - * @note When the DAC channel is enabled the trigger source can no more be modified. - * @retval None - */ -void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel */ - DAC->CR |= (DAC_CR_EN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel */ - DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel)); - } -} - -/** - * @brief Enables or disables the selected DAC channel software trigger. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel software trigger. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for the selected DAC channel */ - DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4); - } - else - { - /* Disable software trigger for the selected DAC channel */ - DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4)); - } -} - -/** - * @brief Enables or disables simultaneously the two DAC channels software triggers. - * @param NewState: new state of the DAC channels software triggers. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable software trigger for both DAC channels */ - DAC->SWTRIGR |= DUAL_SWTRIG_SET; - } - else - { - /* Disable software trigger for both DAC channels */ - DAC->SWTRIGR &= DUAL_SWTRIG_RESET; - } -} - -/** - * @brief Enables or disables the selected DAC channel wave generation. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_Wave: specifies the wave type to enable or disable. - * This parameter can be one of the following values: - * @arg DAC_Wave_Noise: noise wave generation - * @arg DAC_Wave_Triangle: triangle wave generation - * @param NewState: new state of the selected DAC channel wave generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_WAVE(DAC_Wave)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected wave generation for the selected DAC channel */ - DAC->CR |= DAC_Wave << DAC_Channel; - } - else - { - /* Disable the selected wave generation for the selected DAC channel */ - DAC->CR &= ~(DAC_Wave << DAC_Channel); - } -} - -/** - * @brief Set the specified data holding register value for DAC channel1. - * @param DAC_Align: Specifies the data alignment for DAC channel1. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R1_OFFSET + DAC_Align; - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = Data; -} - -/** - * @brief Set the specified data holding register value for DAC channel2. - * @param DAC_Align: Specifies the data alignment for DAC channel2. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. - * @retval None - */ -void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12R2_OFFSET + DAC_Align; - - /* Set the DAC channel2 selected data holding register */ - *(__IO uint32_t *)tmp = Data; -} - -/** - * @brief Set the specified data holding register value for dual channel DAC. - * @param DAC_Align: Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * @arg DAC_Align_8b_R: 8bit right data alignment selected - * @arg DAC_Align_12b_L: 12bit left data alignment selected - * @arg DAC_Align_12b_R: 12bit right data alignment selected - * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval None - */ -void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) -{ - uint32_t data = 0, tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(DAC_Align)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (DAC_Align == DAC_Align_8b_R) - { - data = ((uint32_t)Data2 << 8) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16) | Data1; - } - - tmp = (uint32_t)DAC_BASE; - tmp += DHR12RD_OFFSET + DAC_Align; - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; -} - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - - tmp = (uint32_t) DAC_BASE ; - tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); - - /* Returns the DAC channel data output register value */ - return (uint16_t) (*(__IO uint32_t*) tmp); -} -/** - * @} - */ - -/** @defgroup DAC_Group2 DMA management functions - * @brief DMA management functions - * -@verbatim - =============================================================================== - ##### DMA management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC channel DMA request. - * @note When enabled DMA1 is generated when an external trigger (EXTI Line9, - * TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8 but not a software trigger) occurs. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param NewState: new state of the selected DAC channel DMA request. - * This parameter can be: ENABLE or DISABLE. - * @note The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be - * already configured. - * @note The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be - * already configured. - * @retval None - */ -void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC channel DMA request */ - DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel); - } - else - { - /* Disable the selected DAC channel DMA request */ - DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel)); - } -} -/** - * @} - */ - -/** @defgroup DAC_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified DAC interrupts. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @param NewState: new state of the specified DAC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_DAC_IT(DAC_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected DAC interrupts */ - DAC->CR |= (DAC_IT << DAC_Channel); - } - else - { - /* Disable the selected DAC interrupts */ - DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel)); - } -} - -/** - * @brief Checks whether the specified DAC flag is set or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to check. - * This parameter can be only of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_FLAG (SET or RESET). - */ -FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Check the status of the specified DAC flag */ - if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET) - { - /* DAC_FLAG is set */ - bitstatus = SET; - } - else - { - /* DAC_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DAC_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's pending flags. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_FLAG: specifies the flag to clear. - * This parameter can be of the following value: - * @arg DAC_FLAG_DMAUDR: DMA underrun flag - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_FLAG(DAC_FLAG)); - - /* Clear the selected DAC flags */ - DAC->SR = (DAC_FLAG << DAC_Channel); -} - -/** - * @brief Checks whether the specified DAC interrupt has occurred or not. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt source to check. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval The new state of DAC_IT (SET or RESET). - */ -ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Get the DAC_IT enable bit status */ - enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ; - - /* Check the status of the specified DAC interrupt */ - if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus) - { - /* DAC_IT is set */ - bitstatus = SET; - } - else - { - /* DAC_IT is reset */ - bitstatus = RESET; - } - /* Return the DAC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DAC channel's interrupt pending bits. - * @param DAC_Channel: The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_Channel_1: DAC Channel1 selected - * @arg DAC_Channel_2: DAC Channel2 selected - * @param DAC_IT: specifies the DAC interrupt pending bit to clear. - * This parameter can be the following values: - * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask - * @note The DMA underrun occurs when a second external trigger arrives before the - * acknowledgement for the first external trigger is received (first request). - * @retval None - */ -void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT) -{ - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(DAC_Channel)); - assert_param(IS_DAC_IT(DAC_IT)); - - /* Clear the selected DAC interrupt pending bits */ - DAC->SR = (DAC_IT << DAC_Channel); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c deleted file mode 100644 index 4ed40dc91..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c +++ /dev/null @@ -1,180 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dbgmcu.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides all the DBGMCU firmware functions. - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dbgmcu.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DBGMCU - * @brief DBGMCU driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DBGMCU_Private_Functions - * @{ - */ - -/** - * @brief Returns the device revision identifier. - * @param None - * @retval Device revision identifier - */ -uint32_t DBGMCU_GetREVID(void) -{ - return(DBGMCU->IDCODE >> 16); -} - -/** - * @brief Returns the device identifier. - * @param None - * @retval Device identifier - */ -uint32_t DBGMCU_GetDEVID(void) -{ - return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); -} - -/** - * @brief Configures low power mode behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the low power mode. - * This parameter can be any combination of the following values: - * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode - * @arg DBGMCU_STOP: Keep debugger connection during STOP mode - * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= DBGMCU_Periph; - } - else - { - DBGMCU->CR &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB1 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted - * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted - * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted - * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted - * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted - * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted - * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted - * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted - * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted - * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted. - * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted - * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted - * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted - * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted - * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB1FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB1FZ &= ~DBGMCU_Periph; - } -} - -/** - * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. - * @param DBGMCU_Periph: specifies the APB2 peripheral. - * This parameter can be any combination of the following values: - * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted - * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted - * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted - * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted - * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted - * @param NewState: new state of the specified peripheral in Debug mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - DBGMCU->APB2FZ |= DBGMCU_Periph; - } - else - { - DBGMCU->APB2FZ &= ~DBGMCU_Periph; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c deleted file mode 100644 index af9c42c24..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c +++ /dev/null @@ -1,538 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dcmi.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the DCMI peripheral: - * + Initialization and Configuration - * + Image capture functions - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The sequence below describes how to use this driver to capture image - from a camera module connected to the DCMI Interface. - This sequence does not take into account the configuration of the - camera module, which should be made before to configure and enable - the DCMI to capture images. - - (#) Enable the clock for the DCMI and associated GPIOs using the following - functions: - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) DCMI pins configuration - (++) Connect the involved DCMI pins to AF13 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); - (++) Configure these DCMI pins in alternate function mode by calling - the function GPIO_Init(); - - (#) Declare a DCMI_InitTypeDef structure, for example: - DCMI_InitTypeDef DCMI_InitStructure; - and fill the DCMI_InitStructure variable with the allowed values - of the structure member. - - (#) Initialize the DCMI interface by calling the function - DCMI_Init(&DCMI_InitStructure); - - (#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR - register to the destination memory buffer. - - (#) Enable DCMI interface using the function - DCMI_Cmd(ENABLE); - - (#) Start the image capture using the function - DCMI_CaptureCmd(ENABLE); - - (#) At this stage the DCMI interface waits for the first start of frame, - then a DMA request is generated continuously/once (depending on the - mode used, Continuous/Snapshot) to transfer the received data into - the destination memory. - - -@- If you need to capture only a rectangular window from the received - image, you have to use the DCMI_CROPConfig() function to configure - the coordinates and size of the window to be captured, then enable - the Crop feature using DCMI_CROPCmd(ENABLE); - In this case, the Crop configuration should be made before to enable - and start the DCMI interface. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dcmi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DCMI - * @brief DCMI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup DCMI_Private_Functions - * @{ - */ - -/** @defgroup DCMI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DCMI registers to their default reset values. - * @param None - * @retval None - */ -void DCMI_DeInit(void) -{ - DCMI->CR = 0x0; - DCMI->IER = 0x0; - DCMI->ICR = 0x1F; - DCMI->ESCR = 0x0; - DCMI->ESUR = 0x0; - DCMI->CWSTRTR = 0x0; - DCMI->CWSIZER = 0x0; -} - -/** - * @brief Initializes the DCMI according to the specified parameters in the DCMI_InitStruct. - * @param DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct) -{ - uint32_t temp = 0x0; - - /* Check the parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode)); - assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode)); - assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity)); - assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode)); - - /* The DCMI configuration registers should be programmed correctly before - enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */ - DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE); - - /* Reset the old DCMI configuration */ - temp = DCMI->CR; - - temp &= ~((uint32_t)DCMI_CR_CM | DCMI_CR_ESS | DCMI_CR_PCKPOL | - DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | - DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); - - /* Sets the new configuration of the DCMI peripheral */ - temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode | - DCMI_InitStruct->DCMI_SynchroMode | - DCMI_InitStruct->DCMI_PCKPolarity | - DCMI_InitStruct->DCMI_VSPolarity | - DCMI_InitStruct->DCMI_HSPolarity | - DCMI_InitStruct->DCMI_CaptureRate | - DCMI_InitStruct->DCMI_ExtendedDataMode); - - DCMI->CR = temp; -} - -/** - * @brief Fills each DCMI_InitStruct member with its default value. - * @param DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct) -{ - /* Set the default configuration */ - DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous; - DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware; - DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling; - DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low; - DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low; - DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame; - DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b; -} - -/** - * @brief Initializes the DCMI peripheral CROP mode according to the specified - * parameters in the DCMI_CROPInitStruct. - * @note This function should be called before to enable and start the DCMI interface. - * @param DCMI_CROPInitStruct: pointer to a DCMI_CROPInitTypeDef structure that - * contains the configuration information for the DCMI peripheral CROP mode. - * @retval None - */ -void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct) -{ - /* Sets the CROP window coordinates */ - DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16)); - - /* Sets the CROP window size */ - DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount | - ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16)); -} - -/** - * @brief Enables or disables the DCMI Crop feature. - * @note This function should be called before to enable and start the DCMI interface. - * @param NewState: new state of the DCMI Crop feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CROPCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Crop feature */ - DCMI->CR |= (uint32_t)DCMI_CR_CROP; - } - else - { - /* Disable the DCMI Crop feature */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CROP; - } -} - -/** - * @brief Sets the embedded synchronization codes - * @param DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that - * contains the embedded synchronization codes for the DCMI peripheral. - * @retval None - */ -void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct) -{ - DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode | - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)| - ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24)); -} - -/** - * @brief Enables or disables the DCMI JPEG format. - * @note The Crop and Embedded Synchronization features cannot be used in this mode. - * @param NewState: new state of the DCMI JPEG format. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_JPEGCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI JPEG format */ - DCMI->CR |= (uint32_t)DCMI_CR_JPEG; - } - else - { - /* Disable the DCMI JPEG format */ - DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG; - } -} -/** - * @} - */ - -/** @defgroup DCMI_Group2 Image capture functions - * @brief Image capture functions - * -@verbatim - =============================================================================== - ##### Image capture functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface. - * @param NewState: new state of the DCMI interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI by setting ENABLE bit */ - DCMI->CR |= (uint32_t)DCMI_CR_ENABLE; - } - else - { - /* Disable the DCMI by clearing ENABLE bit */ - DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE; - } -} - -/** - * @brief Enables or disables the DCMI Capture. - * @param NewState: new state of the DCMI capture. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_CaptureCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DCMI Capture */ - DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE; - } - else - { - /* Disable the DCMI Capture */ - DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE; - } -} - -/** - * @brief Reads the data stored in the DR register. - * @param None - * @retval Data register value - */ -uint32_t DCMI_ReadData(void) -{ - return DCMI->DR; -} -/** - * @} - */ - -/** @defgroup DCMI_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the DCMI interface interrupts. - * @param DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @param NewState: new state of the specified DCMI interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CONFIG_IT(DCMI_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - DCMI->IER |= DCMI_IT; - } - else - { - /* Disable the Interrupt sources */ - DCMI->IER &= (uint16_t)(~DCMI_IT); - } -} - -/** - * @brief Checks whether the DCMI interface flag is set or not. - * @param DCMI_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask - * @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask - * @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask - * @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask - * @arg DCMI_FLAG_LINEMI: Line Masked flag mask - * @arg DCMI_FLAG_HSYNC: HSYNC flag mask - * @arg DCMI_FLAG_VSYNC: VSYNC flag mask - * @arg DCMI_FLAG_FNE: Fifo not empty flag mask - * @retval The new state of DCMI_FLAG (SET or RESET). - */ -FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t dcmireg, tempreg = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG)); - - /* Get the DCMI register index */ - dcmireg = (((uint16_t)DCMI_FLAG) >> 12); - - if (dcmireg == 0x00) /* The FLAG is in RISR register */ - { - tempreg= DCMI->RISR; - } - else if (dcmireg == 0x02) /* The FLAG is in SR register */ - { - tempreg = DCMI->SR; - } - else /* The FLAG is in MISR register */ - { - tempreg = DCMI->MISR; - } - - if ((tempreg & DCMI_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the DCMI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DCMI's pending flags. - * @param DCMI_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask - * @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask - * @arg DCMI_FLAG_LINERI: Line Raw flag mask - * @retval None - */ -void DCMI_ClearFlag(uint16_t DCMI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG)); - - /* Clear the flag by writing in the ICR register 1 in the corresponding - Flag position*/ - - DCMI->ICR = DCMI_FLAG; -} - -/** - * @brief Checks whether the DCMI interrupt has occurred or not. - * @param DCMI_IT: specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The new state of DCMI_IT (SET or RESET). - */ -ITStatus DCMI_GetITStatus(uint16_t DCMI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t itstatus = 0; - - /* Check the parameters */ - assert_param(IS_DCMI_GET_IT(DCMI_IT)); - - itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */ - - if ((itstatus != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DCMI's interrupt pending bits. - * @param DCMI_IT: specifies the DCMI interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -void DCMI_ClearITPendingBit(uint16_t DCMI_IT) -{ - /* Clear the interrupt pending Bit by writing in the ICR register 1 in the - corresponding pending Bit position*/ - - DCMI->ICR = DCMI_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c deleted file mode 100644 index 43f9fcad3..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c +++ /dev/null @@ -1,1301 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access controller (DMA): - * + Initialization and Configuration - * + Data Counter - * + Double Buffer mode configuration and command - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE) - function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE) - function for DMA2. - - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM / FLASH memories: no initialization is - necessary). - - (#) For a given Stream, program the required configuration through following parameters: - Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination - data formats, Circular or Normal mode, Stream Priority level, Source and Destination - Incrementation mode, FIFO mode and its Threshold (if needed), Burst - mode for Source and/or Destination (if needed) using the DMA_Init() function. - To avoid filling unnecessary fields, you can call DMA_StructInit() function - to initialize a given structure with default values (reset values), the modify - only necessary fields - (ie. Source and Destination addresses, Transfer size and Data Formats). - - (#) Enable the NVIC and the corresponding interrupt(s) using the function - DMA_ITConfig() if you need to use DMA interrupts. - - (#) Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring - the second Memory address and the first Memory to be used through the function - DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function - DMA_DoubleBufferModeCmd(). These operations must be done before step 6. - - (#) Enable the DMA stream using the DMA_Cmd() function. - - (#) Activate the needed Stream Request using PPP_DMACmd() function for - any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...) - The function allowing this operation is provided in each PPP peripheral - driver (ie. SPI_DMACmd for SPI peripheral). - Once the Stream is enabled, it is not possible to modify its configuration - unless the stream is stopped and disabled. - After enabling the Stream, it is advised to monitor the EN bit status using - the function DMA_GetCmdStatus(). In case of configuration errors or bus errors - this bit will remain reset and all transfers on this Stream will remain on hold. - - (#) Optionally, you can configure the number of data to be transferred - when the Stream is disabled (ie. after each Transfer Complete event - or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter(). - And you can get the number of remaining data to be transferred using - the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is - enabled and running). - - (#) To control DMA events you can use one of the following two methods: - (##) Check on DMA Stream flags using the function DMA_GetFlagStatus(). - (##) Use DMA interrupts through the function DMA_ITConfig() at initialization - phase and DMA_GetITStatus() function into interrupt routines in - communication phase. - [..] - After checking on a flag you should clear it using DMA_ClearFlag() - function. And after checking on an interrupt event you should - clear it using DMA_ClearITPendingBit() function. - - (#) Optionally, if Circular mode and Double Buffer mode are enabled, you can modify - the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that - the Memory Address to be modified is not the one currently in use by DMA Stream. - This condition can be monitored using the function DMA_GetCurrentMemoryTarget(). - - (#) Optionally, Pause-Resume operations may be performed: - The DMA_Cmd() function may be used to perform Pause-Resume operation. - When a transfer is ongoing, calling this function to disable the - Stream will cause the transfer to be paused. All configuration registers - and the number of remaining data will be preserved. When calling again - this function to re-enable the Stream, the transfer will be resumed from - the point where it was paused. - - -@- Memory-to-Memory transfer is possible by setting the address of the memory into - the Peripheral registers. In this mode, Circular mode and Double Buffer mode - are not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data - packing/unpacking: it is possible to set different Data Sizes for - the Peripheral and the Memory (ie. you can set Half-Word data size - for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two Half-words will be - packed and written in a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different - Data Sizes for Source and Destination. In this case the Peripheral - Data Size will be applied to both Source and Destination. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA - * @brief DMA driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \ - DMA_SxCR_TEIE | DMA_SxCR_DMEIE) - -#define DMA_Stream0_IT_MASK (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \ - DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \ - DMA_LISR_TCIF0) - -#define DMA_Stream1_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 6) -#define DMA_Stream2_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 16) -#define DMA_Stream3_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK << 22) -#define DMA_Stream4_IT_MASK (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream5_IT_MASK (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream6_IT_MASK (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000) -#define DMA_Stream7_IT_MASK (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000) -#define TRANSFER_IT_MASK (uint32_t)0x0F3C0F3C -#define HIGH_ISR_MASK (uint32_t)0x20000000 -#define RESERVED_MASK (uint32_t)0x0F7D0F7D - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/** @defgroup DMA_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - buffer size, circular/normal mode selection, memory-to-memory mode selection - and Stream priority value. - [..] - The DMA_Init() function follows the DMA configuration procedures as described in - reference manual (RM0090) except the first point: waiting on EN bit to be reset. - This condition should be checked by user application using the function DMA_GetCmdStatus() - before calling the DMA_Init() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the DMAy Streamx registers to their default reset values. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval None - */ -void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Disable the selected DMAy Streamx */ - DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN); - - /* Reset DMAy Streamx control register */ - DMAy_Streamx->CR = 0; - - /* Reset DMAy Streamx Number of Data to Transfer register */ - DMAy_Streamx->NDTR = 0; - - /* Reset DMAy Streamx peripheral address register */ - DMAy_Streamx->PAR = 0; - - /* Reset DMAy Streamx memory 0 address register */ - DMAy_Streamx->M0AR = 0; - - /* Reset DMAy Streamx memory 1 address register */ - DMAy_Streamx->M1AR = 0; - - /* Reset DMAy Streamx FIFO control register */ - DMAy_Streamx->FCR = (uint32_t)0x00000021; - - /* Reset interrupt pending bits for the selected stream */ - if (DMAy_Streamx == DMA1_Stream0) - { - /* Reset interrupt pending bits for DMA1 Stream0 */ - DMA1->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream1) - { - /* Reset interrupt pending bits for DMA1 Stream1 */ - DMA1->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream2) - { - /* Reset interrupt pending bits for DMA1 Stream2 */ - DMA1->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream3) - { - /* Reset interrupt pending bits for DMA1 Stream3 */ - DMA1->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream4) - { - /* Reset interrupt pending bits for DMA1 Stream4 */ - DMA1->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream5) - { - /* Reset interrupt pending bits for DMA1 Stream5 */ - DMA1->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream6) - { - /* Reset interrupt pending bits for DMA1 Stream6 */ - DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK; - } - else if (DMAy_Streamx == DMA1_Stream7) - { - /* Reset interrupt pending bits for DMA1 Stream7 */ - DMA1->HIFCR = DMA_Stream7_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream0) - { - /* Reset interrupt pending bits for DMA2 Stream0 */ - DMA2->LIFCR = DMA_Stream0_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream1) - { - /* Reset interrupt pending bits for DMA2 Stream1 */ - DMA2->LIFCR = DMA_Stream1_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream2) - { - /* Reset interrupt pending bits for DMA2 Stream2 */ - DMA2->LIFCR = DMA_Stream2_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream3) - { - /* Reset interrupt pending bits for DMA2 Stream3 */ - DMA2->LIFCR = DMA_Stream3_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream4) - { - /* Reset interrupt pending bits for DMA2 Stream4 */ - DMA2->HIFCR = DMA_Stream4_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream5) - { - /* Reset interrupt pending bits for DMA2 Stream5 */ - DMA2->HIFCR = DMA_Stream5_IT_MASK; - } - else if (DMAy_Streamx == DMA2_Stream6) - { - /* Reset interrupt pending bits for DMA2 Stream6 */ - DMA2->HIFCR = DMA_Stream6_IT_MASK; - } - else - { - if (DMAy_Streamx == DMA2_Stream7) - { - /* Reset interrupt pending bits for DMA2 Stream7 */ - DMA2->HIFCR = DMA_Stream7_IT_MASK; - } - } -} - -/** - * @brief Initializes the DMAy Streamx according to the specified parameters in - * the DMA_InitStruct structure. - * @note Before calling this function, it is recommended to check that the Stream - * is actually disabled using the function DMA_GetCmdStatus(). - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel)); - assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR)); - assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize)); - assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode)); - assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode)); - assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst)); - - /*------------------------- DMAy Streamx CR Configuration ------------------*/ - /* Get the DMAy_Streamx CR value */ - tmpreg = DMAy_Streamx->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */ - tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR)); - - /* Configure DMAy Streamx: */ - /* Set CHSEL bits according to DMA_CHSEL value */ - /* Set DIR bits according to DMA_DIR value */ - /* Set PINC bit according to DMA_PeripheralInc value */ - /* Set MINC bit according to DMA_MemoryInc value */ - /* Set PSIZE bits according to DMA_PeripheralDataSize value */ - /* Set MSIZE bits according to DMA_MemoryDataSize value */ - /* Set CIRC bit according to DMA_Mode value */ - /* Set PL bits according to DMA_Priority value */ - /* Set MBURST bits according to DMA_MemoryBurst value */ - /* Set PBURST bits according to DMA_PeripheralBurst value */ - tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR | - DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | - DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | - DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority | - DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst; - - /* Write to DMAy Streamx CR register */ - DMAy_Streamx->CR = tmpreg; - - /*------------------------- DMAy Streamx FCR Configuration -----------------*/ - /* Get the DMAy_Streamx FCR value */ - tmpreg = DMAy_Streamx->FCR; - - /* Clear DMDIS and FTH bits */ - tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Configure DMAy Streamx FIFO: - Set DMDIS bits according to DMA_FIFOMode value - Set FTH bits according to DMA_FIFOThreshold value */ - tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold; - - /* Write to DMAy Streamx CR */ - DMAy_Streamx->FCR = tmpreg; - - /*------------------------- DMAy Streamx NDTR Configuration ----------------*/ - /* Write to DMAy Streamx NDTR register */ - DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize; - - /*------------------------- DMAy Streamx PAR Configuration -----------------*/ - /* Write to DMAy Streamx PAR */ - DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr; - - /*------------------------- DMAy Streamx M0AR Configuration ----------------*/ - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr; -} - -/** - * @brief Fills each DMA_InitStruct member with its default value. - * @param DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) -{ - /*-------------- Reset DMA init structure parameters values ----------------*/ - /* Initialize the DMA_Channel member */ - DMA_InitStruct->DMA_Channel = 0; - - /* Initialize the DMA_PeripheralBaseAddr member */ - DMA_InitStruct->DMA_PeripheralBaseAddr = 0; - - /* Initialize the DMA_Memory0BaseAddr member */ - DMA_InitStruct->DMA_Memory0BaseAddr = 0; - - /* Initialize the DMA_DIR member */ - DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory; - - /* Initialize the DMA_BufferSize member */ - DMA_InitStruct->DMA_BufferSize = 0; - - /* Initialize the DMA_PeripheralInc member */ - DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; - - /* Initialize the DMA_MemoryInc member */ - DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; - - /* Initialize the DMA_PeripheralDataSize member */ - DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; - - /* Initialize the DMA_MemoryDataSize member */ - DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; - - /* Initialize the DMA_Mode member */ - DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; - - /* Initialize the DMA_Priority member */ - DMA_InitStruct->DMA_Priority = DMA_Priority_Low; - - /* Initialize the DMA_FIFOMode member */ - DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable; - - /* Initialize the DMA_FIFOThreshold member */ - DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull; - - /* Initialize the DMA_MemoryBurst member */ - DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single; - - /* Initialize the DMA_PeripheralBurst member */ - DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single; -} - -/** - * @brief Enables or disables the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx. - * This parameter can be: ENABLE or DISABLE. - * - * @note This function may be used to perform Pause-Resume operation. When a - * transfer is ongoing, calling this function to disable the Stream will - * cause the transfer to be paused. All configuration registers and the - * number of remaining data will be preserved. When calling again this - * function to re-enable the Stream, the transfer will be resumed from - * the point where it was paused. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling the - * stream, it is recommended to check (or wait until) the DMA Stream is - * effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * - * @retval None - */ -void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMAy Streamx by setting EN bit */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN; - } - else - { - /* Disable the selected DMAy Streamx by clearing EN bit */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN; - } -} - -/** - * @brief Configures, when the PINC (Peripheral Increment address mode) bit is - * set, if the peripheral address should be incremented with the data - * size (configured with PSIZE bits) or by a fixed offset equal to 4 - * (32-bit aligned addresses). - * - * @note This function has no effect if the Peripheral Increment mode is disabled. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_Pincos: specifies the Peripheral increment offset size. - * This parameter can be one of the following values: - * @arg DMA_PINCOS_Psize: Peripheral address increment is done - * accordingly to PSIZE parameter. - * @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is - * fixed to 4 (32-bit aligned addresses). - * @retval None - */ -void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos)); - - /* Check the needed Peripheral increment offset */ - if(DMA_Pincos != DMA_PINCOS_Psize) - { - /* Configure DMA_SxCR_PINCOS bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS; - } - else - { - /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS; - } -} - -/** - * @brief Configures, when the DMAy Streamx is disabled, the flow controller for - * the next transactions (Peripheral or Memory). - * - * @note Before enabling this feature, check if the used peripheral supports - * the Flow Controller mode or not. - * - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FlowCtrl: specifies the DMA flow controller. - * This parameter can be one of the following values: - * @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is - * the DMA controller. - * @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller - * is the peripheral. - * @retval None - */ -void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl)); - - /* Check the needed flow controller */ - if(DMA_FlowCtrl != DMA_FlowCtrl_Memory) - { - /* Configure DMA_SxCR_PFCTRL bit with the input parameter */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL; - } - else - { - /* Clear the PFCTRL bit: Memory is the flow controller */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL; - } -} -/** - * @} - */ - -/** @defgroup DMA_Group2 Data Counter functions - * @brief Data Counter functions - * -@verbatim - =============================================================================== - ##### Data Counter functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and read the buffer size - (number of data to be transferred). - [..] - The DMA data counter can be written only when the DMA Stream is disabled - (ie. after transfer complete event). - [..] - The following function can be used to write the Stream data counter value: - (+) void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter); - -@- It is advised to use this function rather than DMA_Init() in situations - where only the Data buffer needs to be reloaded. - -@- If the Source and Destination Data Sizes are different, then the value - written in data counter, expressing the number of transfers, is relative - to the number of transfers from the Peripheral point of view. - ie. If Memory data size is Word, Peripheral data size is Half-Words, - then the value to be configured in the data counter is the number - of Half-Words to be transferred from/to the peripheral. - [..] - The DMA data counter can be read to indicate the number of remaining transfers for - the relative DMA Stream. This counter is decremented at the end of each data - transfer and when the transfer is complete: - (+) If Normal mode is selected: the counter is set to 0. - (+) If Circular mode is selected: the counter is reloaded with the initial value - (configured before enabling the DMA Stream) - [..] - The following function can be used to read the Stream data counter value: - (+) uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx); - -@endverbatim - * @{ - */ - -/** - * @brief Writes the number of data units to be transferred on the DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Counter: Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @note In Memory-to-Memory transfer mode, the memory buffer pointed by - * DMAy_SxPAR register is considered as Peripheral. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Write the number of data units to be transferred */ - DMAy_Streamx->NDTR = (uint16_t)Counter; -} - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Return the number of remaining data units for DMAy Streamx */ - return ((uint16_t)(DMAy_Streamx->NDTR)); -} -/** - * @} - */ - -/** @defgroup DMA_Group3 Double Buffer mode functions - * @brief Double Buffer mode functions - * -@verbatim - =============================================================================== - ##### Double Buffer mode functions ##### - =============================================================================== - [..] - This subsection provides function allowing to configure and control the double - buffer mode parameters. - - [..] - The Double Buffer mode can be used only when Circular mode is enabled. - The Double Buffer mode cannot be used when transferring data from Memory to Memory. - - [..] - The Double Buffer mode allows to set two different Memory addresses from/to which - the DMA controller will access alternatively (after completing transfer to/from - target memory 0, it will start transfer to/from target memory 1). - This allows to reduce software overhead for double buffering and reduce the CPU - access time. - - [..] - Two functions must be called before calling the DMA_Init() function: - (+) void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t Memory1BaseAddr, uint32_t DMA_CurrentMemory); - (+) void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState); - - [..] - DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address - and the first Memory target from/to which the transfer will start after - enabling the DMA Stream. Then DMA_DoubleBufferModeCmd() must be called - to enable the Double Buffer mode (or disable it when it should not be used). - - [..] - Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is - stopped) to modify on of the target Memories addresses or to check which Memory target is currently - used: - (+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, - uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget); - (+) uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx); - - [..] - DMA_MemoryTargetConfig() can be called to modify the base address of one of - the two target Memories. - The Memory of which the base address will be modified must not be currently - be used by the DMA Stream (ie. if the DMA Stream is currently transferring - from Memory 1 then you can only modify base address of target Memory 0 and vice versa). - To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which - returns the index of the Memory target currently in use by the DMA Stream. - -@endverbatim - * @{ - */ - -/** - * @brief Configures, when the DMAy Streamx is disabled, the double buffer mode - * and the current memory target. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param Memory1BaseAddr: the base address of the second buffer (Memory 1) - * @param DMA_CurrentMemory: specifies which memory will be first buffer for - * the transactions when the Stream will be enabled. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: Memory 0 is the current buffer. - * @arg DMA_Memory_1: Memory 1 is the current buffer. - * - * @note Memory0BaseAddr is set by the DMA structure configuration in DMA_Init(). - * - * @retval None - */ -void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr, - uint32_t DMA_CurrentMemory) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory)); - - if (DMA_CurrentMemory != DMA_Memory_0) - { - /* Set Memory 1 as current memory address */ - DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT); - } - else - { - /* Set Memory 0 as current memory address */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT); - } - - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = Memory1BaseAddr; -} - -/** - * @brief Enables or disables the double buffer mode for the selected DMA stream. - * @note This function can be called only when the DMA Stream is disabled. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param NewState: new state of the DMAy Streamx double buffer mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Configure the Double Buffer mode */ - if (NewState != DISABLE) - { - /* Enable the Double buffer mode */ - DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM; - } - else - { - /* Disable the Double buffer mode */ - DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM; - } -} - -/** - * @brief Configures the Memory address for the next buffer transfer in double - * buffer mode (for dynamic use). This function can be called when the - * DMA Stream is enabled and when the transfer is ongoing. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param MemoryBaseAddr: The base address of the target memory buffer - * @param DMA_MemoryTarget: Next memory target to be used. - * This parameter can be one of the following values: - * @arg DMA_Memory_0: To use the memory address 0 - * @arg DMA_Memory_1: To use the memory address 1 - * - * @note It is not allowed to modify the Base Address of a target Memory when - * this target is involved in the current transfer. ie. If the DMA Stream - * is currently transferring to/from Memory 1, then it not possible to - * modify Base address of Memory 1, but it is possible to modify Base - * address of Memory 0. - * To know which Memory is currently used, you can use the function - * DMA_GetCurrentMemoryTarget(). - * - * @retval None - */ -void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr, - uint32_t DMA_MemoryTarget) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget)); - - /* Check the Memory target to be configured */ - if (DMA_MemoryTarget != DMA_Memory_0) - { - /* Write to DMAy Streamx M1AR */ - DMAy_Streamx->M1AR = MemoryBaseAddr; - } - else - { - /* Write to DMAy Streamx M0AR */ - DMAy_Streamx->M0AR = MemoryBaseAddr; - } -} - -/** - * @brief Returns the current memory target used by double buffer transfer. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The memory target number: 0 for Memory0 or 1 for Memory1. - */ -uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the current memory target */ - if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0) - { - /* Current memory buffer used is Memory 1 */ - tmp = 1; - } - else - { - /* Current memory buffer used is Memory 0 */ - tmp = 0; - } - return tmp; -} -/** - * @} - */ - -/** @defgroup DMA_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA enable status - (+) Check the FIFO status - (+) Configure the DMA Interrupts sources and check or clear the flags or - pending bits status. - - [..] - (#) DMA Enable status: - After configuring the DMA Stream (DMA_Init() function) and enabling - the stream, it is recommended to check (or wait until) the DMA Stream - is effectively enabled. A Stream may remain disabled if a configuration - parameter is wrong. After disabling a DMA Stream, it is also recommended - to check (or wait until) the DMA Stream is effectively disabled. - If a Stream is disabled while a data transfer is ongoing, the current - data will be transferred and the Stream will be effectively disabled - only after this data transfer completion. - To monitor this state it is possible to use the following function: - (++) FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) FIFO Status: - It is possible to monitor the FIFO status when a transfer is ongoing - using the following function: - (++) uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); - - (#) DMA Interrupts and Flags: - The user should identify which mode will be used in his application - to manage the DMA controller events: Polling mode or Interrupt mode. - - *** Polling Mode *** - ==================== - [..] - Each DMA stream can be managed through 4 event Flags: - (x : DMA Stream number ) - (#) DMA_FLAG_FEIFx : to indicate that a FIFO Mode Transfer Error event occurred. - (#) DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred. - (#) DMA_FLAG_TEIFx : to indicate that a Transfer Error event occurred. - (#) DMA_FLAG_HTIFx : to indicate that a Half-Transfer Complete event occurred. - (#) DMA_FLAG_TCIFx : to indicate that a Transfer Complete event occurred . - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - (+) void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - Each DMA Stream can be managed through 4 Interrupts: - - *** Interrupt Source *** - ======================== - [..] - (#) DMA_IT_FEIFx : specifies the interrupt source for the FIFO Mode Transfer Error event. - (#) DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event. - (#) DMA_IT_TEIFx : specifies the interrupt source for the Transfer Error event. - (#) DMA_IT_HTIFx : specifies the interrupt source for the Half-Transfer Complete event. - (#) DMA_IT_TCIFx : specifies the interrupt source for the a Transfer Complete event. - [..] - In this Mode it is advised to use the following functions: - (+) void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState); - (+) ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - (+) void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT); - -@endverbatim - * @{ - */ - -/** - * @brief Returns the status of EN bit for the specified DMAy Streamx. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * - * @note After configuring the DMA Stream (DMA_Init() function) and enabling - * the stream, it is recommended to check (or wait until) the DMA Stream - * is effectively enabled. A Stream may remain disabled if a configuration - * parameter is wrong. - * After disabling a DMA Stream, it is also recommended to check (or wait - * until) the DMA Stream is effectively disabled. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer - * of this single data is finished. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0) - { - /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */ - state = ENABLE; - } - else - { - /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current DMAy Streamx FIFO filled level. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS)); - - return tmpreg; -} - -/** - * @brief Checks whether the specified DMAy Streamx flag is set or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_FLAG (SET or RESET). - */ -FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - FlagStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the flag is in HISR or LISR */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR; - } - - /* Mask the reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA flag */ - if ((tmpreg & DMA_FLAG) != (uint32_t)RESET) - { - /* DMA_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the DMA_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's pending flags. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Streamx transfer complete flag - * @arg DMA_FLAG_HTIFx: Streamx half transfer complete flag - * @arg DMA_FLAG_TEIFx: Streamx transfer error flag - * @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag - * @arg DMA_FLAG_FEIFx: Streamx FIFO error flag - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear flag bits */ - DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear flag bits */ - DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK); - } -} - -/** - * @brief Enables or disables the specified DMAy Streamx interrupts. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask - * @arg DMA_IT_HT: Half transfer complete interrupt mask - * @arg DMA_IT_TE: Transfer error interrupt mask - * @arg DMA_IT_FE: FIFO error interrupt mask - * @param NewState: new state of the specified DMA interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CONFIG_IT(DMA_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Check if the DMA_IT parameter contains a FIFO interrupt */ - if ((DMA_IT & DMA_IT_FE) != 0) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE; - } - else - { - /* Disable the selected DMA FIFO interrupts */ - DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE; - } - } - - /* Check if the DMA_IT parameter contains a Transfer interrupt */ - if (DMA_IT != DMA_IT_FE) - { - if (NewState != DISABLE) - { - /* Enable the selected DMA transfer interrupts */ - DMAy_Streamx->CR |= (uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - else - { - /* Disable the selected DMA transfer interrupts */ - DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK); - } - } -} - -/** - * @brief Checks whether the specified DMAy Streamx interrupt has occurred or not. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval The new state of DMA_IT (SET or RESET). - */ -ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - ITStatus bitstatus = RESET; - DMA_TypeDef* DMAy; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_GET_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if the interrupt enable bit is in the CR or FCR register */ - if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET) - { - /* Get the interrupt enable position mask in CR register */ - tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK); - - /* Check the enable bit in CR register */ - enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg); - } - else - { - /* Check the enable bit in FCR register */ - enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); - } - - /* Check if the interrupt pending flag is in LISR or HISR */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Get DMAy HISR register value */ - tmpreg = DMAy->HISR ; - } - else - { - /* Get DMAy LISR register value */ - tmpreg = DMAy->LISR ; - } - - /* mask all reserved bits */ - tmpreg &= (uint32_t)RESERVED_MASK; - - /* Check the status of the specified DMA interrupt */ - if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* DMA_IT is set */ - bitstatus = SET; - } - else - { - /* DMA_IT is reset */ - bitstatus = RESET; - } - - /* Return the DMA_IT status */ - return bitstatus; -} - -/** - * @brief Clears the DMAy Streamx's interrupt pending bits. - * @param DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 - * to 7 to select the DMA Stream. - * @param DMA_IT: specifies the DMA interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TCIFx: Streamx transfer complete interrupt - * @arg DMA_IT_HTIFx: Streamx half transfer complete interrupt - * @arg DMA_IT_TEIFx: Streamx transfer error interrupt - * @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt - * @arg DMA_IT_FEIFx: Streamx FIFO error interrupt - * Where x can be 0 to 7 to select the DMA Stream. - * @retval None - */ -void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT) -{ - DMA_TypeDef* DMAy; - - /* Check the parameters */ - assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx)); - assert_param(IS_DMA_CLEAR_IT(DMA_IT)); - - /* Determine the DMA to which belongs the stream */ - if (DMAy_Streamx < DMA2_Stream0) - { - /* DMAy_Streamx belongs to DMA1 */ - DMAy = DMA1; - } - else - { - /* DMAy_Streamx belongs to DMA2 */ - DMAy = DMA2; - } - - /* Check if LIFCR or HIFCR register is targeted */ - if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET) - { - /* Set DMAy HIFCR register clear interrupt bits */ - DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } - else - { - /* Set DMAy LIFCR register clear interrupt bits */ - DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c deleted file mode 100644 index f38b71c21..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c +++ /dev/null @@ -1,784 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_dma2d.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the DMA2D controller (DMA2D) peripheral: - * + Initialization and configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable DMA2D clock using - RCC_APB2PeriphResetCmd(RCC_APB2Periph_DMA2D, ENABLE) function. - - (#) Configures DMA2D - (++) transfer mode - (++) pixel format, line_number, pixel_per_line - (++) output memory address - (++) alpha value - (++) output offset - (++) Default color (RGB) - - (#) Configures Foreground or/and background - (++) memory address - (++) alpha value - (++) offset and default color - - (#) Call the DMA2D_Start() to enable the DMA2D controller. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_dma2d.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup DMA2D - * @brief DMA2D driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#define CR_MASK ((uint32_t)0xFFFCE0FC) /* DMA2D CR Mask */ -#define PFCCR_MASK ((uint32_t)0x00FC00C0) /* DMA2D FGPFCCR Mask */ -#define DEAD_MASK ((uint32_t)0xFFFF00FE) /* DMA2D DEAD Mask */ - -/** @defgroup DMA2D_Private_Functions - * @{ - */ - -/** @defgroup DMA2D_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DMA2D - (+) Start/Abort/Suspend Transfer - (+) Initialize, configure and set Foreground and background - (+) configure and enable DeadTime - (+) configure lineWatermark - - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the DMA2D peripheral registers to their default reset - * values. - * @param None - * @retval None - */ - -void DMA2D_DeInit(void) -{ - /* Enable DMA2D reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, ENABLE); - /* Release DMA2D from reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2D, DISABLE); -} - - -/** - * @brief Initializes the DMA2D peripheral according to the specified parameters - * in the DMA2D_InitStruct. - * @note This function can be used only when the DMA2D is disabled. - * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure that contains - * the configuration information for the specified DMA2D peripheral. - * @retval None - */ -void DMA2D_Init(DMA2D_InitTypeDef* DMA2D_InitStruct) -{ - - uint32_t outgreen = 0; - uint32_t outred = 0; - uint32_t outalpha = 0; - uint32_t pixline = 0; - - /* Check the parameters */ - assert_param(IS_DMA2D_MODE(DMA2D_InitStruct->DMA2D_Mode)); - assert_param(IS_DMA2D_CMODE(DMA2D_InitStruct->DMA2D_CMode)); - assert_param(IS_DMA2D_OGREEN(DMA2D_InitStruct->DMA2D_OutputGreen)); - assert_param(IS_DMA2D_ORED(DMA2D_InitStruct->DMA2D_OutputRed)); - assert_param(IS_DMA2D_OBLUE(DMA2D_InitStruct->DMA2D_OutputBlue)); - assert_param(IS_DMA2D_OALPHA(DMA2D_InitStruct->DMA2D_OutputAlpha)); - assert_param(IS_DMA2D_OUTPUT_OFFSET(DMA2D_InitStruct->DMA2D_OutputOffset)); - assert_param(IS_DMA2D_LINE(DMA2D_InitStruct->DMA2D_NumberOfLine)); - assert_param(IS_DMA2D_PIXEL(DMA2D_InitStruct->DMA2D_PixelPerLine)); - - /* Configures the DMA2D operation mode */ - DMA2D->CR &= (uint32_t)CR_MASK; - DMA2D->CR |= (DMA2D_InitStruct->DMA2D_Mode); - - /* Configures the color mode of the output image */ - DMA2D->OPFCCR &= ~(uint32_t)DMA2D_OPFCCR_CM; - DMA2D->OPFCCR |= (DMA2D_InitStruct->DMA2D_CMode); - - /* Configures the output color */ - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB8888) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 24; - } - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB888) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 8; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 16; - outalpha = (uint32_t)0x00000000; - } - - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_RGB565) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 11; - outalpha = (uint32_t)0x00000000; - } - - else - - if (DMA2D_InitStruct->DMA2D_CMode == DMA2D_ARGB1555) - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 5; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 10; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 15; - } - - else /* DMA2D_CMode = DMA2D_ARGB4444 */ - { - outgreen = DMA2D_InitStruct->DMA2D_OutputGreen << 4; - outred = DMA2D_InitStruct->DMA2D_OutputRed << 8; - outalpha = DMA2D_InitStruct->DMA2D_OutputAlpha << 12; - } - DMA2D->OCOLR |= ((outgreen) | (outred) | (DMA2D_InitStruct->DMA2D_OutputBlue) | (outalpha)); - - /* Configures the output memory address */ - DMA2D->OMAR = (DMA2D_InitStruct->DMA2D_OutputMemoryAdd); - - /* Configure the line Offset */ - DMA2D->OOR &= ~(uint32_t)DMA2D_OOR_LO; - DMA2D->OOR |= (DMA2D_InitStruct->DMA2D_OutputOffset); - - /* Configure the number of line and pixel per line */ - pixline = DMA2D_InitStruct->DMA2D_PixelPerLine << 16; - DMA2D->NLR &= ~(DMA2D_NLR_NL | DMA2D_NLR_PL); - DMA2D->NLR |= ((DMA2D_InitStruct->DMA2D_NumberOfLine) | (pixline)); - -/** - * @brief Fills each DMA2D_InitStruct member with its default value. - * @param DMA2D_InitStruct: pointer to a DMA2D_InitTypeDef structure which will - * be initialized. - * @retval None - */ -} -void DMA2D_StructInit(DMA2D_InitTypeDef* DMA2D_InitStruct) -{ - /* Initialize the transfer mode member */ - DMA2D_InitStruct->DMA2D_Mode = DMA2D_M2M; - - /* Initialize the output color mode members */ - DMA2D_InitStruct->DMA2D_CMode = DMA2D_ARGB8888; - - /* Initialize the alpha and RGB values */ - DMA2D_InitStruct->DMA2D_OutputGreen = 0x00; - DMA2D_InitStruct->DMA2D_OutputBlue = 0x00; - DMA2D_InitStruct->DMA2D_OutputRed = 0x00; - DMA2D_InitStruct->DMA2D_OutputAlpha = 0x00; - - /* Initialize the output memory address */ - DMA2D_InitStruct->DMA2D_OutputMemoryAdd = 0x00; - - /* Initialize the output offset */ - DMA2D_InitStruct->DMA2D_OutputOffset = 0x00; - - /* Initialize the number of line and the number of pixel per line */ - DMA2D_InitStruct->DMA2D_NumberOfLine = 0x00; - DMA2D_InitStruct->DMA2D_PixelPerLine = 0x00; -} - -/** - * @brief Start the DMA2D transfer. - * @param - * @retval None - */ - -void DMA2D_StartTransfer(void) -{ - /* Start DMA2D transfer by setting START bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_START; -} - -/** - * @brief Abort the DMA2D transfer. - * @param - * @retval None - */ - -void DMA2D_AbortTransfer(void) -{ - /* Start DMA2D transfer by setting START bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_ABORT; - -} - -/** - * @brief Stop or continue the DMA2D transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void DMA2D_Suspend(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Suspend DMA2D transfer by setting STOP bit */ - DMA2D->CR |= (uint32_t)DMA2D_CR_SUSP; - } - else - { - /* Continue DMA2D transfer by clearing STOP bit */ - DMA2D->CR &= ~(uint32_t)DMA2D_CR_SUSP; - } -} - -/** - * @brief Configures the Foreground according to the specified parameters - * in the DMA2D_FGStruct. - * @note This function can be used only when the transfer is disabled. - * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure that contains - * the configuration information for the specified Background. - * @retval None - */ -void DMA2D_FGConfig(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) -{ - - uint32_t fg_clutcolormode = 0; - uint32_t fg_clutsize = 0; - uint32_t fg_alpha_mode = 0; - uint32_t fg_alphavalue = 0; - uint32_t fg_colorgreen = 0; - uint32_t fg_colorred = 0; - - assert_param(IS_DMA2D_FGO(DMA2D_FG_InitStruct->DMA2D_FGO)); - assert_param(IS_DMA2D_FGCM(DMA2D_FG_InitStruct->DMA2D_FGCM)); - assert_param(IS_DMA2D_FG_CLUT_CM(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM)); - assert_param(IS_DMA2D_FG_CLUT_SIZE(DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE)); - assert_param(IS_DMA2D_FG_ALPHA_MODE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE)); - assert_param(IS_DMA2D_FG_ALPHA_VALUE(DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE)); - assert_param(IS_DMA2D_FGC_BLUE(DMA2D_FG_InitStruct->DMA2D_FGC_BLUE)); - assert_param(IS_DMA2D_FGC_GREEN(DMA2D_FG_InitStruct->DMA2D_FGC_GREEN)); - assert_param(IS_DMA2D_FGC_RED(DMA2D_FG_InitStruct->DMA2D_FGC_RED)); - - /* Configures the FG memory address */ - DMA2D->FGMAR = (DMA2D_FG_InitStruct->DMA2D_FGMA); - - /* Configures the FG offset */ - DMA2D->FGOR &= ~(uint32_t)DMA2D_FGOR_LO; - DMA2D->FGOR |= (DMA2D_FG_InitStruct->DMA2D_FGO); - - /* Configures foreground Pixel Format Convertor */ - DMA2D->FGPFCCR &= (uint32_t)PFCCR_MASK; - fg_clutcolormode = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM << 4; - fg_clutsize = DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE << 8; - fg_alpha_mode = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE << 16; - fg_alphavalue = DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE << 24; - DMA2D->FGPFCCR |= (DMA2D_FG_InitStruct->DMA2D_FGCM | fg_clutcolormode | fg_clutsize | \ - fg_alpha_mode | fg_alphavalue); - - /* Configures foreground color */ - DMA2D->FGCOLR &= ~(DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_RED); - fg_colorgreen = DMA2D_FG_InitStruct->DMA2D_FGC_GREEN << 8; - fg_colorred = DMA2D_FG_InitStruct->DMA2D_FGC_RED << 16; - DMA2D->FGCOLR |= (DMA2D_FG_InitStruct->DMA2D_FGC_BLUE | fg_colorgreen | fg_colorred); - - /* Configures foreground CLUT memory address */ - DMA2D->FGCMAR = DMA2D_FG_InitStruct->DMA2D_FGCMAR; -} - -/** - * @brief Fills each DMA2D_FGStruct member with its default value. - * @param DMA2D_FGStruct: pointer to a DMA2D_FGTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA2D_FG_StructInit(DMA2D_FG_InitTypeDef* DMA2D_FG_InitStruct) -{ - /*!< Initialize the DMA2D foreground memory address */ - DMA2D_FG_InitStruct->DMA2D_FGMA = 0x00; - - /*!< Initialize the DMA2D foreground offset */ - DMA2D_FG_InitStruct->DMA2D_FGO = 0x00; - - /*!< Initialize the DMA2D foreground color mode */ - DMA2D_FG_InitStruct->DMA2D_FGCM = CM_ARGB8888; - - /*!< Initialize the DMA2D foreground CLUT color mode */ - DMA2D_FG_InitStruct->DMA2D_FG_CLUT_CM = CLUT_CM_ARGB8888; - - /*!< Initialize the DMA2D foreground CLUT size */ - DMA2D_FG_InitStruct->DMA2D_FG_CLUT_SIZE = 0x00; - - /*!< Initialize the DMA2D foreground alpha mode */ - DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - - /*!< Initialize the DMA2D foreground alpha value */ - DMA2D_FG_InitStruct->DMA2D_FGPFC_ALPHA_VALUE = 0x00; - - /*!< Initialize the DMA2D foreground blue value */ - DMA2D_FG_InitStruct->DMA2D_FGC_BLUE = 0x00; - - /*!< Initialize the DMA2D foreground green value */ - DMA2D_FG_InitStruct->DMA2D_FGC_GREEN = 0x00; - - /*!< Initialize the DMA2D foreground red value */ - DMA2D_FG_InitStruct->DMA2D_FGC_RED = 0x00; - - /*!< Initialize the DMA2D foreground CLUT memory address */ - DMA2D_FG_InitStruct->DMA2D_FGCMAR = 0x00; -} - - -/** - * @brief Configures the Background according to the specified parameters - * in the DMA2D_BGStruct. - * @note This function can be used only when the transfer is disabled. - * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure that contains - * the configuration information for the specified Background. - * @retval None - */ -void DMA2D_BGConfig(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) -{ - - uint32_t bg_clutcolormode = 0; - uint32_t bg_clutsize = 0; - uint32_t bg_alpha_mode = 0; - uint32_t bg_alphavalue = 0; - uint32_t bg_colorgreen = 0; - uint32_t bg_colorred = 0; - - assert_param(IS_DMA2D_BGO(DMA2D_BG_InitStruct->DMA2D_BGO)); - assert_param(IS_DMA2D_BGCM(DMA2D_BG_InitStruct->DMA2D_BGCM)); - assert_param(IS_DMA2D_BG_CLUT_CM(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM)); - assert_param(IS_DMA2D_BG_CLUT_SIZE(DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE)); - assert_param(IS_DMA2D_BG_ALPHA_MODE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE)); - assert_param(IS_DMA2D_BG_ALPHA_VALUE(DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE)); - assert_param(IS_DMA2D_BGC_BLUE(DMA2D_BG_InitStruct->DMA2D_BGC_BLUE)); - assert_param(IS_DMA2D_BGC_GREEN(DMA2D_BG_InitStruct->DMA2D_BGC_GREEN)); - assert_param(IS_DMA2D_BGC_RED(DMA2D_BG_InitStruct->DMA2D_BGC_RED)); - - /* Configures the BG memory address */ - DMA2D->BGMAR = (DMA2D_BG_InitStruct->DMA2D_BGMA); - - /* Configures the BG offset */ - DMA2D->BGOR &= ~(uint32_t)DMA2D_BGOR_LO; - DMA2D->BGOR |= (DMA2D_BG_InitStruct->DMA2D_BGO); - - /* Configures background Pixel Format Convertor */ - DMA2D->BGPFCCR &= (uint32_t)PFCCR_MASK; - bg_clutcolormode = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM << 4; - bg_clutsize = DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE << 8; - bg_alpha_mode = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE << 16; - bg_alphavalue = DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE << 24; - DMA2D->BGPFCCR |= (DMA2D_BG_InitStruct->DMA2D_BGCM | bg_clutcolormode | bg_clutsize | \ - bg_alpha_mode | bg_alphavalue); - - /* Configures background color */ - DMA2D->BGCOLR &= ~(DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_RED); - bg_colorgreen = DMA2D_BG_InitStruct->DMA2D_BGC_GREEN << 8; - bg_colorred = DMA2D_BG_InitStruct->DMA2D_BGC_RED << 16; - DMA2D->BGCOLR |= (DMA2D_BG_InitStruct->DMA2D_BGC_BLUE | bg_colorgreen | bg_colorred); - - /* Configures background CLUT memory address */ - DMA2D->BGCMAR = DMA2D_BG_InitStruct->DMA2D_BGCMAR; - -} - -/** - * @brief Fills each DMA2D_BGStruct member with its default value. - * @param DMA2D_BGStruct: pointer to a DMA2D_BGTypeDef structure which will - * be initialized. - * @retval None - */ -void DMA2D_BG_StructInit(DMA2D_BG_InitTypeDef* DMA2D_BG_InitStruct) -{ - /*!< Initialize the DMA2D background memory address */ - DMA2D_BG_InitStruct->DMA2D_BGMA = 0x00; - - /*!< Initialize the DMA2D background offset */ - DMA2D_BG_InitStruct->DMA2D_BGO = 0x00; - - /*!< Initialize the DMA2D background color mode */ - DMA2D_BG_InitStruct->DMA2D_BGCM = CM_ARGB8888; - - /*!< Initialize the DMA2D background CLUT color mode */ - DMA2D_BG_InitStruct->DMA2D_BG_CLUT_CM = CLUT_CM_ARGB8888; - - /*!< Initialize the DMA2D background CLUT size */ - DMA2D_BG_InitStruct->DMA2D_BG_CLUT_SIZE = 0x00; - - /*!< Initialize the DMA2D background alpha mode */ - DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_MODE = NO_MODIF_ALPHA_VALUE; - - /*!< Initialize the DMA2D background alpha value */ - DMA2D_BG_InitStruct->DMA2D_BGPFC_ALPHA_VALUE = 0x00; - - /*!< Initialize the DMA2D background blue value */ - DMA2D_BG_InitStruct->DMA2D_BGC_BLUE = 0x00; - - /*!< Initialize the DMA2D background green value */ - DMA2D_BG_InitStruct->DMA2D_BGC_GREEN = 0x00; - - /*!< Initialize the DMA2D background red value */ - DMA2D_BG_InitStruct->DMA2D_BGC_RED = 0x00; - - /*!< Initialize the DMA2D background CLUT memory address */ - DMA2D_BG_InitStruct->DMA2D_BGCMAR = 0x00; -} - -/** - * @brief Start the automatic loading of the CLUT or abort the transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_FGStart(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Start the automatic loading of the CLUT */ - DMA2D->FGPFCCR |= DMA2D_FGPFCCR_START; - } - else - { - /* abort the transfer */ - DMA2D->FGPFCCR &= (uint32_t)~DMA2D_FGPFCCR_START; - } -} - -/** - * @brief Start the automatic loading of the CLUT or abort the transfer. - * @param NewState: new state of the DMA2D peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_BGStart(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Start the automatic loading of the CLUT */ - DMA2D->BGPFCCR |= DMA2D_BGPFCCR_START; - } - else - { - /* abort the transfer */ - DMA2D->BGPFCCR &= (uint32_t)~DMA2D_BGPFCCR_START; - } -} - -/** - * @brief Configures the DMA2D dead time. - * @param DMA2D_DeadTime: specifies the DMA2D dead time. - * This parameter can be one of the following values: - * @retval None - */ -void DMA2D_DeadTimeConfig(uint32_t DMA2D_DeadTime, FunctionalState NewState) -{ - uint32_t DeadTime; - - /* Check the parameters */ - assert_param(IS_DMA2D_DEAD_TIME(DMA2D_DeadTime)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable and Configures the dead time */ - DMA2D->AMTCR &= (uint32_t)DEAD_MASK; - DeadTime = DMA2D_DeadTime << 8; - DMA2D->AMTCR |= (DeadTime | DMA2D_AMTCR_EN); - } - else - { - DMA2D->AMTCR &= ~(uint32_t)DMA2D_AMTCR_EN; - } -} - -/** - * @brief Define the configuration of the line watermark . - * @param DMA2D_LWatermarkConfig: Line Watermark configuration. - * @retval None - */ - -void DMA2D_LineWatermarkConfig(uint32_t DMA2D_LWatermarkConfig) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LineWatermark(DMA2D_LWatermarkConfig)); - - /* Sets the Line watermark configuration */ - DMA2D->LWR = (uint32_t)DMA2D_LWatermarkConfig; -} - -/** - * @} - */ - -/** @defgroup DMA2D_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the DMA2D - Interrupts and to get the status and clear flags and Interrupts - pending bits. - [..] The DMA2D provides 6 Interrupts sources and 6 Flags - - *** Flags *** - ============= - [..] - (+) DMA2D_FLAG_CE : Configuration Error Interrupt flag - (+) DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag - (+) DMA2D_FLAG_TW: Transfer Watermark Interrupt flag - (+) DMA2D_FLAG_TC: Transfer Complete interrupt flag - (+) DMA2D_FLAG_TE: Transfer Error interrupt flag - (+) DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag - - *** Interrupts *** - ================== - [..] - (+) DMA2D_IT_CE: Configuration Error Interrupt is generated when a wrong - configuration is detected - (+) DMA2D_IT_CAE: CLUT Access Error Interrupt - (+) DMA2D_IT_TW: Transfer Watermark Interrupt is generated when - the programmed watermark is reached - (+) DMA2D_IT_TE: Transfer Error interrupt is generated when the CPU trying - to access the CLUT while a CLUT loading or a DMA2D1 transfer - is on going - (+) DMA2D_IT_CTC: CLUT Transfer Complete Interrupt - (+) DMA2D_IT_TC: Transfer Complete interrupt -@endverbatim - * @{ - */ -/** - * @brief Enables or disables the specified DMA2D's interrupts. - * @param DMA2D_IT: specifies the DMA2D interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. - * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. - * @arg DMA2D_IT_TE: Transfer Error interrupt enable. - * @param NewState: new state of the specified DMA2D interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void DMA2D_ITConfig(uint32_t DMA2D_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected DMA2D interrupts */ - DMA2D->CR |= DMA2D_IT; - } - else - { - /* Disable the selected DMA2D interrupts */ - DMA2D->CR &= (uint32_t)~DMA2D_IT; - } -} - -/** - * @brief Checks whether the specified DMA2D's flag is set or not. - * @param DMA2D_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. - * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. - * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. - * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. - * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. - * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. - * @retval The new state of DMA2D_FLAG (SET or RESET). - */ - -FlagStatus DMA2D_GetFlagStatus(uint32_t DMA2D_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); - - /* Check the status of the specified DMA2D flag */ - if (((DMA2D->ISR) & DMA2D_FLAG) != (uint32_t)RESET) - { - /* DMA2D_FLAG is set */ - bitstatus = SET; - } - else - { - /* DMA2D_FLAG is reset */ - bitstatus = RESET; - } - /* Return the DMA2D_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the DMA2D's pending flags. - * @param DMA2D_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA2D_FLAG_CE: Configuration Error Interrupt flag. - * @arg DMA2D_FLAG_CTC: CLUT Transfer Complete Interrupt flag. - * @arg DMA2D_FLAG_CAE: CLUT Access Error Interrupt flag. - * @arg DMA2D_FLAG_TW: Transfer Watermark Interrupt flag. - * @arg DMA2D_FLAG_TC: Transfer Complete interrupt flag. - * @arg DMA2D_FLAG_TE: Transfer Error interrupt flag. - * @retval None - */ -void DMA2D_ClearFlag(uint32_t DMA2D_FLAG) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_GET_FLAG(DMA2D_FLAG)); - - /* Clear the corresponding DMA2D flag */ - DMA2D->IFCR = (uint32_t)DMA2D_FLAG; -} - -/** - * @brief Checks whether the specified DMA2D's interrupt has occurred or not. - * @param DMA2D_IT: specifies the DMA2D interrupts sources to check. - * This parameter can be one of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt Enable. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt Enable. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt Enable. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt Enable. - * @arg DMA2D_IT_TC: Transfer Complete interrupt enable. - * @arg DMA2D_IT_TE: Transfer Error interrupt enable. - * @retval The new state of the DMA2D_IT (SET or RESET). - */ -ITStatus DMA2D_GetITStatus(uint32_t DMA2D_IT) -{ - ITStatus bitstatus = RESET; - uint32_t DMA2D_IT_FLAG = DMA2D_IT >> 8; - - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - - if ((DMA2D->ISR & DMA2D_IT_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - if (((DMA2D->CR & DMA2D_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the DMA2D's interrupt pending bits. - * @param DMA2D_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration Error Interrupt. - * @arg DMA2D_IT_CTC: CLUT Transfer Complete Interrupt. - * @arg DMA2D_IT_CAE: CLUT Access Error Interrupt. - * @arg DMA2D_IT_TW: Transfer Watermark Interrupt. - * @arg DMA2D_IT_TC: Transfer Complete interrupt. - * @arg DMA2D_IT_TE: Transfer Error interrupt. - * @retval None - */ -void DMA2D_ClearITPendingBit(uint32_t DMA2D_IT) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_IT(DMA2D_IT)); - DMA2D_IT = DMA2D_IT >> 8; - - /* Clear the corresponding DMA2D Interrupt */ - DMA2D->IFCR = (uint32_t)DMA2D_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c deleted file mode 100644 index 2ab0201a3..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_exti.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the EXTI peripheral: - * + Initialization and Configuration - * + Interrupts and flags management - * -@verbatim - - =============================================================================== - ##### EXTI features ##### - =============================================================================== - - [..] External interrupt/event lines are mapped as following: - (#) All available GPIO pins are connected to the 16 external - interrupt/event lines from EXTI0 to EXTI15. - (#) EXTI line 16 is connected to the PVD Output - (#) EXTI line 17 is connected to the RTC Alarm event - (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event - (#) EXTI line 19 is connected to the Ethernet Wakeup event - (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event - (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events - (#) EXTI line 22 is connected to the RTC Wakeup event - (#) EXTI line 23 is connected to the LPTIM Wakeup event - - ##### How to use this driver ##### - =============================================================================== - - [..] In order to use an I/O pin as an external interrupt source, follow steps - below: - (#) Configure the I/O in input mode using GPIO_Init() - (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig() - (#) Select the mode(interrupt, event) and configure the trigger - selection (Rising, falling or both) using EXTI_Init() - (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init() - - [..] - (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx - registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_exti.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup EXTI - * @brief EXTI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup EXTI_Private_Functions - * @{ - */ - -/** @defgroup EXTI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the EXTI peripheral registers to their default reset values. - * @param None - * @retval None - */ -void EXTI_DeInit(void) -{ - EXTI->IMR = 0x00000000; - EXTI->EMR = 0x00000000; - EXTI->RTSR = 0x00000000; - EXTI->FTSR = 0x00000000; - EXTI->PR = 0x007FFFFF; -} - -/** - * @brief Initializes the EXTI peripheral according to the specified - * parameters in the EXTI_InitStruct. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure - * that contains the configuration information for the EXTI peripheral. - * @retval None - */ -void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) -{ - uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); - assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); - assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); - - tmp = (uint32_t)EXTI_BASE; - - if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; - - tmp += EXTI_InitStruct->EXTI_Mode; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; - EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; - - /* Select the trigger for the selected external interrupts */ - if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) - { - /* Rising Falling edge */ - EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; - EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; - } - else - { - tmp = (uint32_t)EXTI_BASE; - tmp += EXTI_InitStruct->EXTI_Trigger; - - *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; - } - } - else - { - tmp += EXTI_InitStruct->EXTI_Mode; - - /* Disable the selected external lines */ - *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; - } -} - -/** - * @brief Fills each EXTI_InitStruct member with its reset value. - * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) -{ - EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; - EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; - EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; - EXTI_InitStruct->EXTI_LineCmd = DISABLE; -} - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param EXTI_Line: specifies the EXTI line on which the software interrupt - * will be generated. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->SWIER |= EXTI_Line; -} - -/** - * @} - */ - -/** @defgroup EXTI_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param EXTI_Line: specifies the EXTI line flag to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the EXTI's line pending flags. - * @param EXTI_Line: specifies the EXTI lines flags to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearFlag(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param EXTI_Line: specifies the EXTI line to check. - * This parameter can be EXTI_Linex where x can be(0..22) - * @retval The new state of EXTI_Line (SET or RESET). - */ -ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_GET_EXTI_LINE(EXTI_Line)); - - if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; - -} - -/** - * @brief Clears the EXTI's line pending bits. - * @param EXTI_Line: specifies the EXTI lines to clear. - * This parameter can be any combination of EXTI_Linex where x can be (0..22) - * @retval None - */ -void EXTI_ClearITPendingBit(uint32_t EXTI_Line) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(EXTI_Line)); - - EXTI->PR = EXTI_Line; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c deleted file mode 100644 index 17f897715..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c +++ /dev/null @@ -1,1619 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the FLASH peripheral: - * + FLASH Interface configuration - * + FLASH Memory Programming - * + Option Bytes Programming - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the FLASH memory - of all STM32F4xx devices. These functions are split in 4 groups: - - (#) FLASH Interface configuration functions: this group includes the - management of the following features: - (++) Set the latency - (++) Enable/Disable the prefetch buffer - (++) Enable/Disable the Instruction cache and the Data cache - (++) Reset the Instruction cache and the Data cache - - (#) FLASH Memory Programming functions: this group includes all needed - functions to erase and program the main memory: - (++) Lock and Unlock the FLASH interface - (++) Erase function: Erase sector, erase all sectors - (++) Program functions: byte, half word, word and double word - - (#) Option Bytes Programming functions: this group includes all needed - functions to manage the Option Bytes: - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - (++) Launch the Option Bytes loader - - (#) Interrupts and flags management functions: this group - includes all needed functions to: - (++) Enable/Disable the FLASH interrupt sources - (++) Get flags status - (++) Clear flags - (++) Get FLASH operation status - (++) Wait for last FLASH operation - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH - * @brief FLASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_Private_Functions - * @{ - */ - -/** @defgroup FLASH_Group1 FLASH Interface configuration functions - * @brief FLASH Interface configuration functions - * - -@verbatim - =============================================================================== - ##### FLASH Interface configuration functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_SetLatency(uint32_t FLASH_Latency) - To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. - [..] - For STM32F405xx/07xx and STM32F415xx/17xx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - - [..] - For STM32F42xxx/43xxx devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - [..] - For STM32F401x devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - [..] - For STM32F410xx/STM32F411xE devices - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | - +-------------------------------------------------------------------------------------+ - - [..] - +-------------------------------------------------------------------------------------------------------------------+ - | | voltage range | voltage range | voltage range | voltage range | voltage range 2.7 V - 3.6 V | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | with External Vpp = 9V | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |Max Parallelism| x32 | x16 | x8 | x64 | - |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| - |PSIZE[1:0] | 10 | 01 | 00 | 11 | - +-------------------------------------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0' Scale 2 mode, the maximum value of fHCLK = 144MHz. - (++) when VOS = '1' Scale 1 mode, the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 144MHz if OverDrive OFF and 168MHz if OverDrive ON. - (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 168MHz if OverDrive OFF and 180MHz if OverDrive ON. - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. - [..] - On STM32F410xx/STM32F411xE devices: - (++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz. - (++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz. - - For more details please refer product DataSheet - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - - (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheCmd(FunctionalState NewState) - (+) void FLASH_DataCacheCmd(FunctionalState NewState) - (+) void FLASH_InstructionCacheReset(void) - (+) void FLASH_DataCacheReset(void) - - [..] - The unlock sequence is not needed for these functions. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the code latency value. - * @param FLASH_Latency: specifies the FLASH Latency value. - * This parameter can be one of the following values: - * @arg FLASH_Latency_0: FLASH Zero Latency cycle - * @arg FLASH_Latency_1: FLASH One Latency cycle - * @arg FLASH_Latency_2: FLASH Two Latency cycles - * @arg FLASH_Latency_3: FLASH Three Latency cycles - * @arg FLASH_Latency_4: FLASH Four Latency cycles - * @arg FLASH_Latency_5: FLASH Five Latency cycles - * @arg FLASH_Latency_6: FLASH Six Latency cycles - * @arg FLASH_Latency_7: FLASH Seven Latency cycles - * @arg FLASH_Latency_8: FLASH Eight Latency cycles - * @arg FLASH_Latency_9: FLASH Nine Latency cycles - * @arg FLASH_Latency_10: FLASH Teen Latency cycles - * @arg FLASH_Latency_11: FLASH Eleven Latency cycles - * @arg FLASH_Latency_12: FLASH Twelve Latency cycles - * @arg FLASH_Latency_13: FLASH Thirteen Latency cycles - * @arg FLASH_Latency_14: FLASH Fourteen Latency cycles - * @arg FLASH_Latency_15: FLASH Fifteen Latency cycles - * - * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE/STM32F412xG and STM32F413_423xx devices - * this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7. - * - * @note For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Latency_0 and FLASH_Latency_15. - * - * @retval None - */ -void FLASH_SetLatency(uint32_t FLASH_Latency) -{ - /* Check the parameters */ - assert_param(IS_FLASH_LATENCY(FLASH_Latency)); - - /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */ - *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency; -} - -/** - * @brief Enables or disables the Prefetch Buffer. - * @param NewState: new state of the Prefetch Buffer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_PrefetchBufferCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Enable or disable the Prefetch Buffer */ - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_PRFTEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_PRFTEN); - } -} - -/** - * @brief Enables or disables the Instruction Cache feature. - * @param NewState: new state of the Instruction Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_InstructionCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_ICEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_ICEN); - } -} - -/** - * @brief Enables or disables the Data Cache feature. - * @param NewState: new state of the Data Cache. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_DataCacheCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - FLASH->ACR |= FLASH_ACR_DCEN; - } - else - { - FLASH->ACR &= (~FLASH_ACR_DCEN); - } -} - -/** - * @brief Resets the Instruction Cache. - * @note This function must be used only when the Instruction Cache is disabled. - * @param None - * @retval None - */ -void FLASH_InstructionCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_ICRST; -} - -/** - * @brief Resets the Data Cache. - * @note This function must be used only when the Data Cache is disabled. - * @param None - * @retval None - */ -void FLASH_DataCacheReset(void) -{ - FLASH->ACR |= FLASH_ACR_DCRST; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group2 FLASH Memory Programming functions - * @brief FLASH Memory Programming functions - * -@verbatim - =============================================================================== - ##### FLASH Memory Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_Unlock(void) - (+) void FLASH_Lock(void) - (+) FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) - (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) - (+) FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) - The following functions can be used only for STM32F42xxx/43xxx devices. - (+) FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) - (+) FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_Unlock() function to enable the FLASH control register access - - (#) Call the desired function to erase sector(s) or program data - - (#) Call the FLASH_Lock() function to disable the FLASH control register access - (recommended to protect the FLASH memory against possible unwanted operation) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Unlock(void) -{ - if((FLASH->CR & FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - FLASH->KEYR = FLASH_KEY1; - FLASH->KEYR = FLASH_KEY2; - } -} - -/** - * @brief Locks the FLASH control register access - * @param None - * @retval None - */ -void FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; -} - -/** - * @brief Erases a specified FLASH Sector. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param FLASH_Sector: The Sector number to be erased. - * - * @note For STM32F405xx/407xx and STM32F415xx/417xx devices this parameter can - * be a value between FLASH_Sector_0 and FLASH_Sector_11. - * - * For STM32F42xxx/43xxx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_23. - * - * For STM32F401xx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_5. - * - * For STM32F411xE and STM32F412xG devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_7. - * - * For STM32F410xx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_4. - * - * For STM32F413_423xx devices this parameter can be a value between - * FLASH_Sector_0 and FLASH_Sector_15. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(FLASH_Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | FLASH_Sector; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2); - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2); -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER); -#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx || STM32F446xx */ - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Erases all FLASH Sectors in Bank 1. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank1Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER1; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER1); - - } - /* Return the Erase Status */ - return status; -} - - -/** - * @brief Erases all FLASH Sectors in Bank 2. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param VoltageRange: The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0x0; - FLASH_Status status = FLASH_COMPLETE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == VoltageRange_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == VoltageRange_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == VoltageRange_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR |= FLASH_CR_MER2; - FLASH->CR |= FLASH_CR_STRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_CR_MER2); - - } - /* Return the Erase Status */ - return status; -} - -/** - * @brief Programs a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint64_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a word (32-bit) at a specified address. - * - * @note This function must be used when the device voltage range is from 2.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a half word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from 2.1V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - /* Return the Program Status */ - return status; -} - -/** - * @brief Programs a byte (8-bit) at a specified address. - * @note This function can be used within all the device supply voltage ranges. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address: specifies the address to be programmed. - * This parameter can be any address in Program memory zone or in OTP zone. - * @param Data: specifies the data to be programmed. - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - /* if the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - /* if the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Return the Program Status */ - return status; -} - -/** - * @} - */ - -/** @defgroup FLASH_Group3 Option Bytes Programming functions - * @brief Option Bytes Programming functions - * -@verbatim - =============================================================================== - ##### Option Bytes Programming functions ##### - =============================================================================== - [..] - This group includes the following functions: - (+) void FLASH_OB_Unlock(void) - (+) void FLASH_OB_Lock(void) - (+) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) - (+) void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PCROPSelect) - (+) void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) - (+) void FLASH_OB_RDPConfig(uint8_t OB_RDP) - (+) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - (+) void FLASH_OB_BORConfig(uint8_t OB_BOR) - (+) FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data) - (+) FLASH_Status FLASH_OB_Launch(void) - (+) uint32_t FLASH_OB_GetUser(void) - (+) uint8_t FLASH_OB_GetWRP(void) - (+) uint8_t FLASH_OB_GetWRP1(void) - (+) uint8_t FLASH_OB_GetPCROP(void) - (+) uint8_t FLASH_OB_GetPCROP1(void) - (+) uint8_t FLASH_OB_GetRDP(void) - (+) uint8_t FLASH_OB_GetBOR(void) - [..] - The following function can be used only for STM32F42xxx/43xxx devices. - (+) void FLASH_OB_BootConfig(uint8_t OB_BOOT) - [..] - Any operation of erase or program should follow these steps: - (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control - register access - - (#) Call one or several functions to program the desired Option Bytes: - (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) - => to Enable/Disable the desired sector write protection - (++) void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read - Protection Level - (++) void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) - => to configure the user Option Bytes. - (++) void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level - - (#) Once all needed Option Bytes to be programmed are correctly written, - call the FLASH_OB_Launch() function to launch the Option Bytes - programming process. - - -@- When changing the IWDG mode from HW to SW or from SW to HW, a system - reset is needed to make the change effective. - - (#) Call the FLASH_OB_Lock() function to disable the FLASH option control - register access (recommended to protect the Option Bytes against - possible unwanted operations) - -@endverbatim - * @{ - */ - -/** - * @brief Unlocks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } -} - -/** - * @brief Locks the FLASH Option Control Registers access. - * @param None - * @retval None - */ -void FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the first - * 1 Mb of the Flash - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Enables or disables the write protection of the desired sectors, for the second - * 1 Mb of the Flash - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @note When the memory read out protection is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * - * @param OB_WRP: specifies the sector(s) to be write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_WRP: A value between OB_WRP_Sector12 and OB_WRP_Sector23 - * @arg OB_WRP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_WRP1Config(uint32_t OB_WRP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_WRP); - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_WRP; - } - } -} - -/** - * @brief Select the Protection Mode (SPRMOD). - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * - * @note After PCROP activation, Option Byte modification is not possible. - * Exception made for the global Read Out Protection modification level (level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible - * - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * - * @note Some Precautions should be taken when activating the PCROP feature : - * The active value of nWRPi bits is inverted when PCROP mode is active, this means if SPRMOD = 1 - * and WRPi = 1 (default value), then the user sector i is read/write protected. - * In order to avoid activation of PCROP Mode for undesired sectors, please follow the - * below safety sequence : - * - Disable PCROP for all Sectors using FLASH_OB_PCROPConfig(OB_PCROP_Sector_All, DISABLE) function - * for Bank1 or FLASH_OB_PCROP1Config(OB_PCROP_Sector_All, DISABLE) function for Bank2 - * - Enable PCROP for the desired Sector i using FLASH_OB_PCROPConfig(Sector i, ENABLE) function - * - Activate the PCROP Mode FLASH_OB_PCROPSelectionConfig() function. - * - * @param OB_PCROP: Select the Protection Mode of nWPRi bits - * This parameter can be one of the following values: - * @arg OB_PcROP_Disable: nWRPi control the write protection of respective user sectors. - * @arg OB_PcROP_Enable: nWRPi control the read&write protection (PCROP) of respective user sectors. - * @retval None - */ -void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP) -{ - uint8_t optiontmp = 0xFF; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); - - /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PcROP | optiontmp); - -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors, for the first 1 MB of the Flash. - * - * @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE - * STM32F412xG and STM32F413_423xx devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector11 for - * STM32F42xxx/43xxx devices and between OB_PCROP_Sector0 and - * OB_PCROP_Sector5 for STM32F401xx/411xE devices. - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROPConfig(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - -/** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected. - * This parameter can be one of the following values: - * @arg OB_PCROP: A value between OB_PCROP_Sector12 and OB_PCROP_Sector23 - * @arg OB_PCROP_Sector_All - * @param Newstate: new state of the Write Protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FLASH_OB_PCROP1Config(uint32_t OB_PCROP, FunctionalState NewState) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_PCROP(OB_PCROP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - if(NewState != DISABLE) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)OB_PCROP; - } - else - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~OB_PCROP); - } - } -} - - -/** - * @brief Sets the read protection level. - * @param OB_RDP: specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Full chip protection - * - * /!\ Warning /!\ When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval None - */ -void FLASH_OB_RDPConfig(uint8_t OB_RDP) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP; - - } -} - -/** - * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param OB_IWDG: Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param OB_STOP: Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NoRST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param OB_STDBY: Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval None - */ -void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) -{ - uint8_t optiontmp = 0xFF; - FLASH_Status status = FLASH_COMPLETE; - - /* Check the parameters */ - assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); - assert_param(IS_OB_STOP_SOURCE(OB_STOP)); - assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - if(status == FLASH_COMPLETE) - { -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) - /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx) - /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); -#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */ - - /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); - } -} - -/** - * @brief Configure the Dual Bank Boot. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param OB_BOOT: specifies the Dual Bank Boot Option byte. - * This parameter can be one of the following values: - * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable - * @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled - * @retval None - */ -void FLASH_OB_BootConfig(uint8_t OB_BOOT) -{ - /* Check the parameters */ - assert_param(IS_OB_BOOT(OB_BOOT)); - - /* Set Dual Bank Boot */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOOT; - -} - -/** - * @brief Sets the BOR Level. - * @param OB_BOR: specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval None - */ -void FLASH_OB_BORConfig(uint8_t OB_BOR) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR(OB_BOR)); - - /* Set the BOR Level */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR; - -} - -/** - * @brief Launch the option byte loading. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_OB_Launch(void) -{ - FLASH_Status status = FLASH_COMPLETE; - - /* Set the OPTSTRT bit in OPTCR register */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(); - - return status; -} - -/** - * @brief Returns the FLASH User Option Bytes values. - * @param None - * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1) - * and RST_STDBY(Bit2). - */ -uint8_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return (uint8_t)(FLASH->OPTCR >> 5); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetWRP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices and STM32F401xx/411xE devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP(void) -{ - /* Return the FLASH PC Read/write protection Register value */ - return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH PC Read/Write Protection Option Bytes value. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param None - * @retval The FLASH PC Read/Write Protection Option Bytes value - */ -uint16_t FLASH_OB_GetPCROP1(void) -{ - /* Return the FLASH write protection Register value */ - return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); -} - -/** - * @brief Returns the FLASH Read Protection level. - * @param None - * @retval FLASH ReadOut Protection Status: - * - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set - * - RESET, when OB_RDP_Level_0 is set - */ -FlagStatus FLASH_OB_GetRDP(void) -{ - FlagStatus readstatus = RESET; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0)) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @param None - * @retval The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -uint8_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C); -} - -/** - * @} - */ - -/** @defgroup FLASH_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FLASH interrupts. - * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FLASH_IT_ERR: FLASH Error Interrupt - * @arg FLASH_IT_EOP: FLASH end of operation Interrupt - * @retval None - */ -void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FLASH_IT(FLASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if(NewState != DISABLE) - { - /* Enable the interrupt sources */ - FLASH->CR |= FLASH_IT; - } - else - { - /* Disable the interrupt sources */ - FLASH->CR &= ~(uint32_t)FLASH_IT; - } -} - -/** - * @brief Checks whether the specified FLASH flag is set or not. - * @param FLASH_FLAG: specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH (PCROP) Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) - * @arg FLASH_FLAG_BSY: FLASH Busy flag - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); - - if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the new state of FLASH_FLAG (SET or RESET) */ - return bitstatus; -} - -/** - * @brief Clears the FLASH's pending flags. - * @param FLASH_FLAG: specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag - * @arg FLASH_FLAG_RDERR: FLASH Read Protection error flag (STM32F42xx/43xxx and STM32F401xx/411xE devices) - * @retval None - */ -void FLASH_ClearFlag(uint32_t FLASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); - - /* Clear the flags */ - FLASH->SR = FLASH_FLAG; -} - -/** - * @brief Returns the FLASH Status. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_RD, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_GetStatus(void) -{ - FLASH_Status flashstatus = FLASH_COMPLETE; - - if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) - { - flashstatus = FLASH_BUSY; - } - else - { - if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_WRP; - } - else - { - if((FLASH->SR & FLASH_FLAG_RDERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_RD; - } - else - { - if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_PROGRAM; - } - else - { - if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00) - { - flashstatus = FLASH_ERROR_OPERATION; - } - else - { - flashstatus = FLASH_COMPLETE; - } - } - } - } - } - /* Return the FLASH Status */ - return flashstatus; -} - -/** - * @brief Waits for a FLASH operation to complete. - * @param None - * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM, - * FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE. - */ -FLASH_Status FLASH_WaitForLastOperation(void) -{ - __IO FLASH_Status status = FLASH_COMPLETE; - - /* Check for the FLASH Status */ - status = FLASH_GetStatus(); - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - while(status == FLASH_BUSY) - { - status = FLASH_GetStatus(); - } - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c deleted file mode 100644 index 2b02dfccb..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c +++ /dev/null @@ -1,158 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_flash_ramfunc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief FLASH RAMFUNC module driver. - * This file provides a FLASH firmware functions which should be - * executed from internal SRAM - * + Stop/Start the flash interface while System Run - * + Enable/Disable the flash sleep while System Run - * - @verbatim - ============================================================================== - ##### APIs executed from Internal RAM ##### - ============================================================================== - [..] - *** ARM Compiler *** - -------------------- - [..] RAM functions are defined using the toolchain options. - Functions that are be executed in RAM should reside in a separate - source module. Using the 'Options for File' dialog you can simply change - the 'Code / Const' area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the - Options for Target' dialog. - - *** ICCARM Compiler *** - ----------------------- - [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". - - *** GNU Compiler *** - -------------------- - [..] RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_flash_ramfunc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FLASH RAMFUNC - * @brief FLASH RAMFUNC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FLASH_RAMFUNC_Private_Functions - * @{ - */ - -/** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### ramfunc functions ##### - =============================================================================== - [..] - This subsection provides a set of functions that should be executed from RAM - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start/Stop the flash interface while System Run - * @note This mode is only available for STM32F411xx devices. - * @note This mode could n't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -__RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - /* Start the flash interface while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FISSR); - } - else - { - /* Stop the flash interface while System Run */ - SET_BIT(PWR->CR, PWR_CR_FISSR); - } -} - -/** - * @brief Enable/Disable the flash sleep while System Run - * @note This mode is only available for STM32F411xx devices. - * @note This mode could n't be set while executing with the flash itself. - * It should be done with specific routine executed from RAM. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -__RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState) -{ - if (NewState != DISABLE) - { - /* Enable the flash sleep while System Run */ - SET_BIT(PWR->CR, PWR_CR_FMSSR); - } - else - { - /* Disable the flash sleep while System Run */ - CLEAR_BIT(PWR->CR, PWR_CR_FMSSR); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c deleted file mode 100644 index 1b68c106d..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c +++ /dev/null @@ -1,1506 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fmc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the FMC peripheral: - * + Interface with SRAM, PSRAM, NOR and OneNAND memories - * + Interface with NAND memories - * + Interface with 16-bit PC Card compatible memories - * + Interface with SDRAM memories - * + Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FMC - * @brief FMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -const FMC_NORSRAMTimingInitTypeDef FMC_DefaultTimingStruct = {0x0F, /* FMC_AddressSetupTime */ - 0x0F, /* FMC_AddressHoldTime */ - 0xFF, /* FMC_DataSetupTime */ - 0x0F, /* FMC_BusTurnAroundDuration */ - 0x0F, /* FMC_CLKDivision */ - 0x0F, /* FMC_DataLatency */ - FMC_AccessMode_A /* FMC_AccessMode */ - }; -/* --------------------- FMC registers bit mask ---------------------------- */ -/* FMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* FMC SDCRx write protection Mask*/ -#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF) - -/* FMC SDCMR Mask*/ -#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF) -#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7) -#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FMC_Private_Functions - * @{ - */ - -/** @defgroup FMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - ##### NOR and SRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_NORSRAMInitTypeDef structure, for example: - FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure; - and fill the FMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NOR/SRAM Controller by calling the function - FMC_NORSRAMInit(&FMC_NORSRAMInitStructure); - - (#) Then enable the NOR/SRAM Bank, for example: - FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC NOR/SRAM Banks registers to their default - * reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 - * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 - * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 - * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 - * @retval None - */ -void FMC_NORSRAMDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); - - /* FMC_Bank1_NORSRAM1 */ - if(FMC_Bank == FMC_Bank1_NORSRAM1) - { - FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB; - } - /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */ - else - { - FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2; - } - FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF; - FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FMC NOR/SRAM Banks according to the specified - * parameters in the FMC_NORSRAMInitStruct. - * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) -{ - uint32_t tmpr = 0, tmpbcr = 0, tmpbwr = 0; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank)); - assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux)); - assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity)); - assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode)); - - /* Get the BTCR register value */ - tmpbcr = FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank]; - - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ - tmpbcr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT| FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN)); - - /* NOR/SRAM Bank control register configuration */ - tmpbcr |= (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux | - FMC_NORSRAMInitStruct->FMC_MemoryType | - FMC_NORSRAMInitStruct->FMC_MemoryDataWidth | - FMC_NORSRAMInitStruct->FMC_BurstAccessMode | - FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity | - FMC_NORSRAMInitStruct->FMC_WrapMode | - FMC_NORSRAMInitStruct->FMC_WaitSignalActive | - FMC_NORSRAMInitStruct->FMC_WriteOperation | - FMC_NORSRAMInitStruct->FMC_WaitSignal | - FMC_NORSRAMInitStruct->FMC_ExtendedMode | - FMC_NORSRAMInitStruct->FMC_AsynchronousWait | - FMC_NORSRAMInitStruct->FMC_WriteBurst | - FMC_NORSRAMInitStruct->FMC_ContinousClock; - - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = tmpbcr; - - if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR) - { - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - - /* Configure Continuous clock feature when bank2..4 is used */ - if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1)) - { - tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20)); - - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock; - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable; - FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20)); - } - - /* NOR/SRAM Bank timing register configuration */ - FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] = - (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision << 20) | - (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency << 24) | - FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode; - - /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */ - if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable) - { - assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration)); - assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode)); - - /* Get the BWTR register value */ - tmpbwr = FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpbwr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ - FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); - - tmpbwr |= (uint32_t)(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime | - (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4)| - (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) | - (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration << 16) | - FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode); - - FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = tmpbwr; - } - else - { - FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF; - } - -} - -/** - * @brief Fills each FMC_NORSRAMInitStruct member with its default value. - * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1; - FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable; - FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM; - FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b; - FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable; - FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable; - FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low; - FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable; - FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState; - FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable; - FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable; - FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable; - FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable; - FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly; - - FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FMC_DefaultTimingStruct); - FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FMC_DefaultTimingStruct); -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1 - * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2 - * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3 - * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - ##### NAND Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with 8-bit or 16-bit NAND memory connected to the NAND Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_NANDInitTypeDef structure, for example: - FMC_NANDInitTypeDef FMC_NANDInitStructure; - and fill the FMC_NANDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NAND Controller by calling the function - FMC_NANDInit(&FMC_NANDInitStructure); - - (#) Then enable the NAND Bank, for example: - FMC_NANDCmd(FMC_Bank3_NAND, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NAND Bank. - - [..] - (@) To enable the Error Correction Code (ECC), you have to use the function - FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE); - [..] - (@) and to get the current ECC value you have to use the function - ECCval = FMC_GetECC(FMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC NAND Banks registers to their default reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @retval None - */ -void FMC_NANDDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - /* Set the FMC_Bank2 registers to their reset values */ - FMC_Bank2->PCR2 = 0x00000018; - FMC_Bank2->SR2 = 0x00000040; - FMC_Bank2->PMEM2 = 0xFCFCFCFC; - FMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FMC_Bank3_NAND */ - else - { - /* Set the FMC_Bank3 registers to their reset values */ - FMC_Bank3->PCR3 = 0x00000018; - FMC_Bank3->SR3 = 0x00000040; - FMC_Bank3->PMEM3 = 0xFCFCFCFC; - FMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FMC NAND Banks according to the specified parameters - * in the FMC_NANDInitStruct. - * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that - * contains the configuration information for the FMC NAND specified Banks. - * @retval None - */ -void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank)); - assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC)); - assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); - - if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppcr = FMC_Bank2->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppcr = FMC_Bank3->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmppcr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ - FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ - FMC_PCR2_TAR | FMC_PCR2_ECCPS)); - - /* Set the tmppcr value according to FMC_NANDInitStruct parameters */ - tmppcr |= (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FMC_NANDInitStruct->FMC_MemoryDataWidth | - FMC_NANDInitStruct->FMC_ECC | - FMC_NANDInitStruct->FMC_ECCPageSize | - (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )| - (FMC_NANDInitStruct->FMC_TARSetupTime << 13); - - if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppmem = FMC_Bank2->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppmem = FMC_Bank3->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmppmem &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ - FMC_PMEM2_MEMHIZ2)); - - /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */ - tmppmem |= (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); - - if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppatt = FMC_Bank2->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppatt = FMC_Bank3->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmppatt &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ - FMC_PATT2_ATTHIZ2)); - - /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */ - tmppatt |= (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); - - if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND) - { - /* FMC_Bank2_NAND registers configuration */ - FMC_Bank2->PCR2 = tmppcr; - FMC_Bank2->PMEM2 = tmppmem; - FMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FMC_Bank3_NAND registers configuration */ - FMC_Bank3->PCR3 = tmppcr; - FMC_Bank3->PMEM3 = tmppmem; - FMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FMC_NANDInitStruct member with its default value. - * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND; - FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; - FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b; - FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable; - FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes; - FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0; - FMC_NANDInitStruct->FMC_TARSetupTime = 0x0; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FMC NAND ECC feature. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @param NewState: new state of the FMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FMC_NAND_BANK(FMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FMC_GetECC(uint32_t FMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FMC_Bank == FMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - ##### PCCARD Controller functions ##### - =============================================================================== - - [..] he following sequence should be followed to configure the FMC to interface - with 16-bit PC Card compatible memory connected to the PCCARD Bank: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_PCCARDInitTypeDef structure, for example: - FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure; - and fill the FMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the PCCARD Controller by calling the function - FMC_PCCARDInit(&FMC_PCCARDInitStructure); - - (#) Then enable the PCCARD Bank: - FMC_PCCARDCmd(ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FMC_PCCARDDeInit(void) -{ - /* Set the FMC_Bank4 registers to their reset values */ - FMC_Bank4->PCR4 = 0x00000018; - FMC_Bank4->SR4 = 0x00000000; - FMC_Bank4->PMEM4 = 0xFCFCFCFC; - FMC_Bank4->PATT4 = 0xFCFCFCFC; - FMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FMC PCCARD Bank according to the specified parameters - * in the FMC_PCCARDInitStruct. - * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FMC PCCARD Bank. - * @retval None - */ -void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) -{ - /* temporary registers */ - uint32_t tmppcr = 0, tmpmem = 0, tmppatt = 0, tmppio = 0; - - /* Check the parameters */ - assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature)); - assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime)); - - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime)); - - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime)); - assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime)); - assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime)); - - /* Get PCCARD control register value */ - tmppcr = FMC_Bank4->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmppcr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ - FMC_PCR4_PWID)); - - /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */ - tmppcr |= (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature | - FMC_NAND_MemoryDataWidth_16b | - (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) | - (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13); - - FMC_Bank4->PCR4 = tmppcr; - - /* Get PCCARD common space timing register value */ - tmpmem = FMC_Bank4->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpmem &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ - FMC_PMEM4_MEMHIZ4)); - - /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */ - tmpmem |= (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24); - - FMC_Bank4->PMEM4 = tmpmem; - - /* Get PCCARD timing parameters */ - tmppatt = FMC_Bank4->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmppatt &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ - FMC_PATT4_ATTHIZ4)); - - /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */ - tmppatt |= (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24); - - FMC_Bank4->PATT4 = tmppatt; - - /* Get FMC_PCCARD device timing parameters */ - tmppio = FMC_Bank4->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmppio &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ - FMC_PIO4_IOHIZ4)); - - /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */ - tmppio |= (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime | - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) | - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)| - (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24); - - FMC_Bank4->PIO4 = tmppio; -} - -/** - * @brief Fills each FMC_PCCARDInitStruct member with its default value. - * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable; - FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0; - FMC_PCCARDInitStruct->FMC_TARSetupTime = 0; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252; - FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} - -/** - * @} - */ - -/** @defgroup FMC_Group4 SDRAM Controller functions - * @brief SDRAM Controller functions - * -@verbatim - =============================================================================== - ##### SDRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FMC to interface - with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2: - - (#) Enable the clock for the FMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FMC pins configuration - (++) Connect the involved FMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC); - (++) Configure these FMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FMC_SDRAMInitTypeDef structure, for example: - FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure; - and fill the FMC_SDRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the SDRAM Controller by calling the function - FMC_SDRAMInit(&FMC_SDRAMInitStructure); - - (#) Declare a FMC_SDRAMCommandTypeDef structure, for example: - FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure; - and fill the FMC_SDRAMCommandStructure variable with the allowed values of - the structure member. - - (#) Configure the SDCMR register with the desired command parameters by calling - the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure); - - (#) At this stage, the SDRAM memory is ready for any valid command. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FMC SDRAM Banks registers to their default - * reset values. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @retval None - */ -void FMC_SDRAMDeInit(uint32_t FMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FMC_SDRAM_BANK(FMC_Bank)); - - FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0; - FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF; - FMC_Bank5_6->SDCMR = 0x00000000; - FMC_Bank5_6->SDRTR = 0x00000000; - FMC_Bank5_6->SDSR = 0x00000000; -} - -/** - * @brief Initializes the FMC SDRAM Banks according to the specified - * parameters in the FMC_SDRAMInitStruct. - * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure - * that contains the configuration information for the FMC SDRAM - * specified Banks. - * @retval None - */ -void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) -{ - /* temporary registers */ - uint32_t tmpr1 = 0, tmpr2 = 0, tmpr3 = 0, tmpr4 = 0; - - /* Check the parameters */ - - /* Control parameters */ - assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank)); - assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber)); - assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber)); - assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth)); - assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber)); - assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency)); - assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection)); - assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod)); - assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay)); - - /* Timing parameters */ - assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)); - assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)); - assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)); - assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)); - assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)); - assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)); - assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)); - - /* Get SDRAM register value */ - tmpr1 = FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - /* SDRAM bank control register configuration */ - tmpr1 |= (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber | - FMC_SDRAMInitStruct->FMC_RowBitsNumber | - FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth | - FMC_SDRAMInitStruct->FMC_InternalBankNumber | - FMC_SDRAMInitStruct->FMC_CASLatency | - FMC_SDRAMInitStruct->FMC_WriteProtection | - FMC_SDRAMInitStruct->FMC_SDClockPeriod | - FMC_SDRAMInitStruct->FMC_ReadBurst | - FMC_SDRAMInitStruct->FMC_ReadPipeDelay; - - if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) - { - FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; - } - else /* SDCR2 "don't care" bits configuration */ - { - /* Get SDCR register value */ - tmpr3 = FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr3 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr3 |= (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod | - FMC_SDRAMInitStruct->FMC_ReadBurst | - FMC_SDRAMInitStruct->FMC_ReadPipeDelay; - - FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3; - FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1; - } - /* SDRAM bank timing register configuration */ - if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM ) - { - /* Get SDTR register value */ - tmpr2 = FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr2 |= (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24); - - FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; - } - else /* SDTR "don't care bits configuration */ - { - /* Get SDTR register value */ - tmpr2 = FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr2 |= (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16); - - /* Get SDTR register value */ - tmpr4 = FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr4 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr4 |= (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) | - (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20); - - FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4; - FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2; - } - -} - -/** - * @brief Fills each FMC_SDRAMInitStruct member with its default value. - * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct) -{ - /* Reset SDRAM Init structure parameters values */ - FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM; - FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b; - FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b; - FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b; - FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4; - FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1; - FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable; - FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable; - FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable; - FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0; - - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16; - FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16; - -} - -/** - * @brief Configures the SDRAM memory command issued when the device is accessed. - * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure - * which will be configured. - * @retval None - */ -void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct) -{ - uint32_t tmpr = 0x0; - - /* check parameters */ - assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode)); - assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)); - - tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode | - FMC_SDRAMCommandStruct->FMC_CommandTarget | - (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) | - ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9)); - - FMC_Bank5_6->SDCMR = tmpr; - -} - - -/** - * @brief Returns the indicated FMC SDRAM bank mode status. - * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @retval The FMC SDRAM bank mode status - */ -uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank) -{ - uint32_t tmpreg = 0; - - /* Check the parameter */ - assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); - - /* Get the busy flag status */ - if(SDRAM_Bank == FMC_Bank1_SDRAM) - { - tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1); - } - else - { - tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2); - } - - /* Return the mode status */ - return tmpreg; -} - -/** - * @brief defines the SDRAM Memory Refresh rate. - * @param FMC_Count: specifies the Refresh timer count. - * @retval None - */ -void FMC_SetRefreshCount(uint32_t FMC_Count) -{ - /* check the parameters */ - assert_param(IS_FMC_REFRESH_COUNT(FMC_Count)); - - FMC_Bank5_6->SDRTR |= (FMC_Count<<1); - -} - -/** - * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param FMC_Number: specifies the auto Refresh number. - * @retval None - */ -void FMC_SetAutoRefresh_Number(uint32_t FMC_Number) -{ - /* check the parameters */ - assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number)); - - FMC_Bank5_6->SDCMR |= (FMC_Number << 5); -} - -/** - * @brief Enables or disables write protection to the specified FMC SDRAM Bank. - * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @param NewState: new state of the write protection flag. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState) -{ - /* Check the parameter */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank)); - - if (NewState != DISABLE) - { - FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable; - } - else - { - FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET; - } - -} - -/** - * @} - */ - -/** @defgroup FMC_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FMC interrupts. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @param NewState: new state of the specified FMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState) -{ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_IT(FMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FMC_Bank2 interrupts */ - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 |= FMC_IT; - } - /* Enable the selected FMC_Bank3 interrupts */ - else if (FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 |= FMC_IT; - } - /* Enable the selected FMC_Bank4 interrupts */ - else if (FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 |= FMC_IT; - } - /* Enable the selected FMC_Bank5_6 interrupt */ - else - { - /* Enables the interrupt if the refresh error flag is set */ - FMC_Bank5_6->SDRTR |= FMC_IT; - } - } - else - { - /* Disable the selected FMC_Bank2 interrupts */ - if(FMC_Bank == FMC_Bank2_NAND) - { - - FMC_Bank2->SR2 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank3 interrupts */ - else if (FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank4 interrupts */ - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= (uint32_t)~FMC_IT; - } - /* Disable the selected FMC_Bank5_6 interrupt */ - else - { - /* Disables the interrupt if the refresh error flag is not set */ - FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FMC flag is set or not. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM - * @param FMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FMC_FLAG_Level: Level detection Flag. - * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FMC_FLAG_FEMPT: Fifo empty Flag. - * @arg FMC_FLAG_Refresh: Refresh error Flag. - * @arg FMC_FLAG_Busy: Busy status Flag. - * @retval The new state of FMC_FLAG (SET or RESET). - */ -FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); - assert_param(IS_FMC_GET_FLAG(FMC_FLAG)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - tmpsr = FMC_Bank2->SR2; - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - tmpsr = FMC_Bank3->SR3; - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - tmpsr = FMC_Bank4->SR4; - } - else - { - tmpsr = FMC_Bank5_6->SDSR; - } - - /* Get the flag status */ - if ((tmpsr & FMC_FLAG) != FMC_FLAG ) - { - bitstatus = RESET; - } - else - { - bitstatus = SET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FMC's pending flags. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FMC_FLAG_Level: Level detection Flag. - * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FMC_FLAG_Refresh: Refresh error Flag. - * @retval None - */ -void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank)); - assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ; - - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 &= (~FMC_FLAG); - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= (~FMC_FLAG); - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= (~FMC_FLAG); - } - /* FMC_Bank5_6 SDRAM*/ - else - { - FMC_Bank5_6->SDRTR &= (~FMC_FLAG); - } - -} - -/** - * @brief Checks whether the specified FMC interrupt has occurred or not. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the FMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @retval The new state of FMC_IT (SET or RESET). - */ -ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0; - uint32_t tmpsr2 = 0x0; - uint32_t itstatus = 0x0; - uint32_t itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_GET_IT(FMC_IT)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - tmpsr = FMC_Bank2->SR2; - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - tmpsr = FMC_Bank3->SR3; - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - tmpsr = FMC_Bank4->SR4; - } - /* FMC_Bank5_6 SDRAM*/ - else - { - tmpsr = FMC_Bank5_6->SDRTR; - tmpsr2 = FMC_Bank5_6->SDSR; - } - - /* get the IT enable bit status*/ - itenable = tmpsr & FMC_IT; - - /* get the corresponding IT Flag status*/ - if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM)) - { - itstatus = tmpsr2 & FMC_SDSR_RE; - } - else - { - itstatus = tmpsr & (FMC_IT >> 3); - } - - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FMC's interrupt pending bits. - * @param FMC_Bank: specifies the FMC Bank to be used - * This parameter can be one of the following values: - * @arg FMC_Bank2_NAND: FMC Bank2 NAND - * @arg FMC_Bank3_NAND: FMC Bank3 NAND - * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD - * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM - * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM - * @param FMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FMC_IT_Level: Level edge detection interrupt. - * @arg FMC_IT_FallingEdge: Falling edge detection interrupt. - * @arg FMC_IT_Refresh: Refresh error detection interrupt. - * @retval None - */ -void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FMC_IT_BANK(FMC_Bank)); - assert_param(IS_FMC_IT(FMC_IT)); - - if(FMC_Bank == FMC_Bank2_NAND) - { - FMC_Bank2->SR2 &= ~(FMC_IT >> 3); - } - else if(FMC_Bank == FMC_Bank3_NAND) - { - FMC_Bank3->SR3 &= ~(FMC_IT >> 3); - } - else if(FMC_Bank == FMC_Bank4_PCCARD) - { - FMC_Bank4->SR4 &= ~(FMC_IT >> 3); - } - /* FMC_Bank5_6 SDRAM*/ - else - { - FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c deleted file mode 100644 index 32612ba0f..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c +++ /dev/null @@ -1,1100 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_fsmc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the FSMC peripheral: - * + Interface with SRAM, PSRAM, NOR and OneNAND memories - * + Interface with NAND memories - * + Interface with 16-bit PC Card compatible memories - * + Interrupts and flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_fsmc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup FSMC - * @brief FSMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -const FSMC_NORSRAMTimingInitTypeDef FSMC_DefaultTimingStruct = {0x0F, /* FSMC_AddressSetupTime */ - 0x0F, /* FSMC_AddressHoldTime */ - 0xFF, /* FSMC_DataSetupTime */ - 0x0F, /* FSMC_BusTurnAroundDuration */ - 0x0F, /* FSMC_CLKDivision */ - 0x0F, /* FSMC_DataLatency */ - FSMC_AccessMode_A /* FSMC_AccessMode */ - }; -/* Private define ------------------------------------------------------------*/ - -/* --------------------- FSMC registers bit mask ---------------------------- */ -/* FSMC BCRx Mask */ -#define BCR_MBKEN_SET ((uint32_t)0x00000001) -#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE) -#define BCR_FACCEN_SET ((uint32_t)0x00000040) - -/* FSMC PCRx Mask */ -#define PCR_PBKEN_SET ((uint32_t)0x00000004) -#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB) -#define PCR_ECCEN_SET ((uint32_t)0x00000040) -#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF) -#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup FSMC_Private_Functions - * @{ - */ - -/** @defgroup FSMC_Group1 NOR/SRAM Controller functions - * @brief NOR/SRAM Controller functions - * -@verbatim - =============================================================================== - ##### NOR and SRAM Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FSMC to interface - with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_NORSRAMInitTypeDef structure, for example: - FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; - and fill the FSMC_NORSRAMInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NOR/SRAM Controller by calling the function - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - (#) Then enable the NOR/SRAM Bank, for example: - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC NOR/SRAM Banks registers to their default - * reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @retval None - */ -void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - - /* FSMC_Bank1_NORSRAM1 */ - if(FSMC_Bank == FSMC_Bank1_NORSRAM1) - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; - } - /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */ - else - { - FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; - } - FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; - FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; -} - -/** - * @brief Initializes the FSMC NOR/SRAM Banks according to the specified - * parameters in the FSMC_NORSRAMInitStruct. - * @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure - * that contains the configuration information for the FSMC NOR/SRAM - * specified Banks. - * @retval None - */ -void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - uint32_t tmpbcr = 0, tmpbtr = 0, tmpbwr = 0; - - /* Check the parameters */ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank)); - assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux)); - assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType)); - assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth)); - assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode)); - assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait)); - assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity)); - assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode)); - assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive)); - assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation)); - assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal)); - assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode)); - assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst)); - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision)); - assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); - - /* Get the BTCR register value */ - tmpbcr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank]; - - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ - tmpbcr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ - FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ - FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW)); - - /* Bank1 NOR/SRAM control register configuration */ - tmpbcr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | - FSMC_NORSRAMInitStruct->FSMC_MemoryType | - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | - FSMC_NORSRAMInitStruct->FSMC_WrapMode | - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | - FSMC_NORSRAMInitStruct->FSMC_WriteOperation | - FSMC_NORSRAMInitStruct->FSMC_WaitSignal | - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | - FSMC_NORSRAMInitStruct->FSMC_WriteBurst; - - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbcr; - - if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) - { - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET; - } - - /* Get the BTCR register value */ - tmpbtr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpbtr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ - FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ - FSMC_BTR1_ACCMOD)); - - /* Bank1 NOR/SRAM timing register configuration */ - tmpbtr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | - (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; - - FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = tmpbtr; - - /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */ - if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) - { - assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime)); - assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime)); - assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime)); - assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration)); - assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode)); - - /* Get the BWTR register value */ - tmpbwr = FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, and ACCMOD bits */ - tmpbwr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ - FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); - - tmpbwr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )| - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | - (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; - - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbwr; - } - else - { - FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; - } -} - -/** - * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. - * @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct) -{ - /* Reset NOR/SRAM Init structure parameters values */ - FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; - FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; - FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; - FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct); - FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct); -} - -/** - * @brief Enables or disables the specified NOR/SRAM Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1 - * @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 - * @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 - * @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET; - } - else - { - /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */ - FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group2 NAND Controller functions - * @brief NAND Controller functions - * -@verbatim - =============================================================================== - ##### NAND Controller functions ##### - =============================================================================== - - [..] The following sequence should be followed to configure the FSMC to interface - with 8-bit or 16-bit NAND memory connected to the NAND Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_NANDInitTypeDef structure, for example: - FSMC_NANDInitTypeDef FSMC_NANDInitStructure; - and fill the FSMC_NANDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the NAND Controller by calling the function - FSMC_NANDInit(&FSMC_NANDInitStructure); - - (#) Then enable the NAND Bank, for example: - FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the NAND Bank. - - [..] - (@) To enable the Error Correction Code (ECC), you have to use the function - FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE); - [..] - (@) and to get the current ECC value you have to use the function - ECCval = FSMC_GetECC(FSMC_Bank3_NAND); - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC NAND Banks registers to their default reset values. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval None - */ -void FSMC_NANDDeInit(uint32_t FSMC_Bank) -{ - /* Check the parameter */ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Set the FSMC_Bank2 registers to their reset values */ - FSMC_Bank2->PCR2 = 0x00000018; - FSMC_Bank2->SR2 = 0x00000040; - FSMC_Bank2->PMEM2 = 0xFCFCFCFC; - FSMC_Bank2->PATT2 = 0xFCFCFCFC; - } - /* FSMC_Bank3_NAND */ - else - { - /* Set the FSMC_Bank3 registers to their reset values */ - FSMC_Bank3->PCR3 = 0x00000018; - FSMC_Bank3->SR3 = 0x00000040; - FSMC_Bank3->PMEM3 = 0xFCFCFCFC; - FSMC_Bank3->PATT3 = 0xFCFCFCFC; - } -} - -/** - * @brief Initializes the FSMC NAND Banks according to the specified parameters - * in the FSMC_NANDInitStruct. - * @param FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that - * contains the configuration information for the FSMC NAND specified Banks. - * @retval None - */ -void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; - - /* Check the parameters */ - assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank)); - assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature)); - assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth)); - assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC)); - assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize)); - assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime)); - assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppcr = FSMC_Bank2->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppcr = FSMC_Bank3->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmppcr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ - FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ - FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); - - /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */ - tmppcr |= (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | - PCR_MEMORYTYPE_NAND | - FSMC_NANDInitStruct->FSMC_MemoryDataWidth | - FSMC_NANDInitStruct->FSMC_ECC | - FSMC_NANDInitStruct->FSMC_ECCPageSize | - (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )| - (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppmem = FSMC_Bank2->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppmem = FSMC_Bank3->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmppmem &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ - FSMC_PMEM2_MEMHIZ2)); - - /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem |= (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the NAND bank 2 register value */ - tmppatt = FSMC_Bank2->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmppatt = FSMC_Bank2->PATT2; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmppatt &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ - FSMC_PATT2_ATTHIZ2)); - - /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt |= (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) - { - /* FSMC_Bank2_NAND registers configuration */ - FSMC_Bank2->PCR2 = tmppcr; - FSMC_Bank2->PMEM2 = tmppmem; - FSMC_Bank2->PATT2 = tmppatt; - } - else - { - /* FSMC_Bank3_NAND registers configuration */ - FSMC_Bank3->PCR3 = tmppcr; - FSMC_Bank3->PMEM3 = tmppmem; - FSMC_Bank3->PATT3 = tmppatt; - } -} - - -/** - * @brief Fills each FSMC_NANDInitStruct member with its default value. - * @param FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which - * will be initialized. - * @retval None - */ -void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct) -{ - /* Reset NAND Init structure parameters values */ - FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; - FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; - FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; - FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; - FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the specified NAND Memory Bank. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_PBKEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_PBKEN_SET; - } - } - else - { - /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET; - } - } -} -/** - * @brief Enables or disables the FSMC NAND ECC feature. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @param NewState: new state of the FSMC NAND ECC feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) -{ - assert_param(IS_FSMC_NAND_BANK(FSMC_Bank)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 |= PCR_ECCEN_SET; - } - else - { - FSMC_Bank3->PCR3 |= PCR_ECCEN_SET; - } - } - else - { - /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET; - } - else - { - FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET; - } - } -} - -/** - * @brief Returns the error correction code register value. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @retval The Error Correction Code (ECC) value. - */ -uint32_t FSMC_GetECC(uint32_t FSMC_Bank) -{ - uint32_t eccval = 0x00000000; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - /* Get the ECCR2 register value */ - eccval = FSMC_Bank2->ECCR2; - } - else - { - /* Get the ECCR3 register value */ - eccval = FSMC_Bank3->ECCR3; - } - /* Return the error correction code value */ - return(eccval); -} -/** - * @} - */ - -/** @defgroup FSMC_Group3 PCCARD Controller functions - * @brief PCCARD Controller functions - * -@verbatim - =============================================================================== - ##### PCCARD Controller functions ##### - =============================================================================== - - [..] he following sequence should be followed to configure the FSMC to interface - with 16-bit PC Card compatible memory connected to the PCCARD Bank: - - (#) Enable the clock for the FSMC and associated GPIOs using the following functions: - (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE); - (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) FSMC pins configuration - (++) Connect the involved FSMC pins to AF12 using the following function - GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); - (++) Configure these FSMC pins in alternate function mode by calling the function - GPIO_Init(); - - (#) Declare a FSMC_PCCARDInitTypeDef structure, for example: - FSMC_PCCARDInitTypeDef FSMC_PCCARDInitStructure; - and fill the FSMC_PCCARDInitStructure variable with the allowed values of - the structure member. - - (#) Initialize the PCCARD Controller by calling the function - FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); - - (#) Then enable the PCCARD Bank: - FSMC_PCCARDCmd(ENABLE); - - (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank. - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the FSMC PCCARD Bank registers to their default reset values. - * @param None - * @retval None - */ -void FSMC_PCCARDDeInit(void) -{ - /* Set the FSMC_Bank4 registers to their reset values */ - FSMC_Bank4->PCR4 = 0x00000018; - FSMC_Bank4->SR4 = 0x00000000; - FSMC_Bank4->PMEM4 = 0xFCFCFCFC; - FSMC_Bank4->PATT4 = 0xFCFCFCFC; - FSMC_Bank4->PIO4 = 0xFCFCFCFC; -} - -/** - * @brief Initializes the FSMC PCCARD Bank according to the specified parameters - * in the FSMC_PCCARDInitStruct. - * @param FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure - * that contains the configuration information for the FSMC PCCARD Bank. - * @retval None - */ -void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - uint32_t tmppcr4 = 0, tmppmem4 = 0, tmppatt4 = 0, tmppio4 = 0; - - /* Check the parameters */ - assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature)); - assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime)); - - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime)); - assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime)); - assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime)); - assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime)); - assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime)); - - /* Get PCCARD control register value */ - tmppcr4 = FSMC_Bank4->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmppcr4 &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID)); - - /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */ - tmppcr4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature | - FSMC_MemoryDataWidth_16b | - (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) | - (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13); - - FSMC_Bank4->PCR4 = tmppcr4; - - /* Get PCCARD common space timing register value */ - tmppmem4 = FSMC_Bank4->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmppmem4 &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ - FSMC_PMEM4_MEMHIZ4)); - - /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */ - tmppmem4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - FSMC_Bank4->PMEM4 = tmppmem4; - - /* Get PCCARD timing parameters */ - tmppatt4 = FSMC_Bank4->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmppatt4 &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ - FSMC_PATT4_ATTHIZ4)); - - /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */ - tmppatt4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - FSMC_Bank4->PATT4 = tmppatt4; - - /* Get FSMC_PCCARD device timing parameters */ - tmppio4 = FSMC_Bank4->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmppio4 &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ - FSMC_PIO4_IOHIZ4)); - - /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */ - tmppio4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) | - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)| - (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24); - - FSMC_Bank4->PIO4 = tmppio4; -} - -/** - * @brief Fills each FSMC_PCCARDInitStruct member with its default value. - * @param FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure - * which will be initialized. - * @retval None - */ -void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct) -{ - /* Reset PCCARD Init structure parameters values */ - FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; - FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; - FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; -} - -/** - * @brief Enables or disables the PCCARD Memory Bank. - * @param NewState: new state of the PCCARD Memory Bank. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_PCCARDCmd(FunctionalState NewState) -{ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 |= PCR_PBKEN_SET; - } - else - { - /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */ - FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET; - } -} -/** - * @} - */ - -/** @defgroup FSMC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified FSMC interrupts. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @param NewState: new state of the specified FSMC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState) -{ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 |= FSMC_IT; - } - /* Enable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 |= FSMC_IT; - } - } - else - { - /* Disable the selected FSMC_Bank2 interrupts */ - if(FSMC_Bank == FSMC_Bank2_NAND) - { - - FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank3 interrupts */ - else if (FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT; - } - /* Disable the selected FSMC_Bank4 interrupts */ - else - { - FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT; - } - } -} - -/** - * @brief Checks whether the specified FSMC flag is set or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @arg FSMC_FLAG_FEMPT: Fifo empty Flag. - * @retval The new state of FSMC_FLAG (SET or RESET). - */ -FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpsr = 0x00000000; - - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - /* Get the flag status */ - if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET ) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the FSMC's pending flags. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag. - * @arg FSMC_FLAG_Level: Level detection Flag. - * @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag. - * @retval None - */ -void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank)); - assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ; - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~FSMC_FLAG; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~FSMC_FLAG; - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~FSMC_FLAG; - } -} - -/** - * @brief Checks whether the specified FSMC interrupt has occurred or not. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the FSMC interrupt source to check. - * This parameter can be one of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval The new state of FSMC_IT (SET or RESET). - */ -ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; - - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_GET_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - tmpsr = FSMC_Bank2->SR2; - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - tmpsr = FSMC_Bank3->SR3; - } - /* FSMC_Bank4_PCCARD*/ - else - { - tmpsr = FSMC_Bank4->SR4; - } - - itstatus = tmpsr & FSMC_IT; - - itenable = tmpsr & (FSMC_IT >> 3); - if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the FSMC's interrupt pending bits. - * @param FSMC_Bank: specifies the FSMC Bank to be used - * This parameter can be one of the following values: - * @arg FSMC_Bank2_NAND: FSMC Bank2 NAND - * @arg FSMC_Bank3_NAND: FSMC Bank3 NAND - * @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD - * @param FSMC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. - * @arg FSMC_IT_Level: Level edge detection interrupt. - * @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. - * @retval None - */ -void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT) -{ - /* Check the parameters */ - assert_param(IS_FSMC_IT_BANK(FSMC_Bank)); - assert_param(IS_FSMC_IT(FSMC_IT)); - - if(FSMC_Bank == FSMC_Bank2_NAND) - { - FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); - } - else if(FSMC_Bank == FSMC_Bank3_NAND) - { - FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3); - } - /* FSMC_Bank4_PCCARD*/ - else - { - FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c deleted file mode 100644 index c3485cc65..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c +++ /dev/null @@ -1,611 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_gpio.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the GPIO peripheral: - * + Initialization and Configuration - * + GPIO Read and Write - * + GPIO Alternate functions configuration - * -@verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function - RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE); - - (#) Configure the GPIO pin(s) using GPIO_Init() - Four possible configuration are available for each pin: - (++) Input: Floating, Pull-up, Pull-down. - (++) Output: Push-Pull (Pull-up, Pull-down or no Pull) - Open Drain (Pull-up, Pull-down or no Pull). In output mode, the speed - is configurable: 2 MHz, 25 MHz, 50 MHz or 100 MHz. - (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull) Open - Drain (Pull-up, Pull-down or no Pull). - (++) Analog: required mode when a pin is to be used as ADC channel or DAC - output. - - (#) Peripherals alternate function: - (++) For ADC and DAC, configure the desired pin in analog mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; - (+++) For other peripherals (TIM, USART...): - (+++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (+++) Configure the desired pin in alternate function mode using - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (+++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (+++) Call GPIO_Init() function - - (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit() - - (#) To set/reset the level of a pin configured in output mode use - GPIO_SetBits()/GPIO_ResetBits() - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_gpio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup GPIO - * @brief GPIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup GPIO_Private_Functions - * @{ - */ - -/** @defgroup GPIO_Group1 Initialization and Configuration - * @brief Initialization and Configuration - * -@verbatim - =============================================================================== - ##### Initialization and Configuration ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @note By default, The GPIO pins are configured in input floating mode (except JTAG pins). - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval None - */ -void GPIO_DeInit(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - if (GPIOx == GPIOA) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); - } - else if (GPIOx == GPIOB) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); - } - else if (GPIOx == GPIOC) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); - } - else if (GPIOx == GPIOD) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); - } - else if (GPIOx == GPIOE) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); - } - else if (GPIOx == GPIOF) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE); - } - else if (GPIOx == GPIOG) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE); - } - else if (GPIOx == GPIOH) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); - } - - else if (GPIOx == GPIOI) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE); - } - else if (GPIOx == GPIOJ) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOJ, DISABLE); - } - else - { - if (GPIOx == GPIOK) - { - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, ENABLE); - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOK, DISABLE); - } - } -} - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) -{ - uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); - assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); - assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); - - /* ------------------------- Configure the port pins ---------------- */ - /*-- GPIO Mode Configuration --*/ - for (pinpos = 0x00; pinpos < 0x10; pinpos++) - { - pos = ((uint32_t)0x01) << pinpos; - /* Get the port pins position */ - currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; - - if (currentpin == pos) - { - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); - GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); - - if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) - { - /* Check Speed mode parameters */ - assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); - - /* Speed mode configuration */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); - GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); - - /* Check Output mode parameters */ - assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); - - /* Output mode configuration*/ - GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; - GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); - } - - /* Pull-up Pull down resistor configuration*/ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); - GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); - } - } -} - -/** - * @brief Fills each GPIO_InitStruct member with its default value. - * @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized. - * @retval None - */ -void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN; - GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; - GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; - GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = 0x00010000; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - tmp |= GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Reset LCKK bit */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKK bit */ - GPIOx->LCKR = tmp; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; - /* Read LCKK bit*/ - tmp = GPIOx->LCKR; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group2 GPIO Read and Write - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### GPIO Read and Write ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The input port pin value. - */ -uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO input data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO input data port value. - */ -uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->IDR); -} - -/** - * @brief Reads the specified output data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_Pin_x where x can be (0..15). - * @retval The output port pin value. - */ -uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - uint8_t bitstatus = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - - if (((GPIOx->ODR) & GPIO_Pin) != (uint32_t)Bit_RESET) - { - bitstatus = (uint8_t)Bit_SET; - } - else - { - bitstatus = (uint8_t)Bit_RESET; - } - return bitstatus; -} - -/** - * @brief Reads the specified GPIO output data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @retval GPIO output data port value. - */ -uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - return ((uint16_t)GPIOx->ODR); -} - -/** - * @brief Sets the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRL = GPIO_Pin; -} - -/** - * @brief Clears the selected data port bits. - * @note This functions uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bits to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - GPIOx->BSRRH = GPIO_Pin; -} - -/** - * @brief Sets or clears the selected data port bit. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_Pin_x where x can be (0..15). - * @param BitVal: specifies the value to be written to the selected bit. - * This parameter can be one of the BitAction enum values: - * @arg Bit_RESET: to clear the port pin - * @arg Bit_SET: to set the port pin - * @retval None - */ -void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_BIT_ACTION(BitVal)); - - if (BitVal != Bit_RESET) - { - GPIOx->BSRRL = GPIO_Pin; - } - else - { - GPIOx->BSRRH = GPIO_Pin ; - } -} - -/** - * @brief Writes data to the specified GPIO data port. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param PortVal: specifies the value to be written to the port output data register. - * @retval None - */ -void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR = PortVal; -} - -/** - * @brief Toggles the specified GPIO pins.. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_Pin: Specifies the pins to be toggled. - * @retval None - */ -void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - - GPIOx->ODR ^= GPIO_Pin; -} - -/** - * @} - */ - -/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function - * @brief GPIO Alternate functions configuration function - * -@verbatim - =============================================================================== - ##### GPIO Alternate functions configuration function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Changes the mapping of the specified pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F405xx/407xx and STM32F415xx/417xx devices - * x can be (A..I) to select the GPIO peripheral for STM32F42xxx/43xxx devices. - * x can be (A, B, C, D and H) to select the GPIO peripheral for STM32F401xx devices. - * @param GPIO_PinSource: specifies the pin for the Alternate function. - * This parameter can be GPIO_PinSourcex where x can be (0..15). - * @param GPIO_AFSelection: selects the pin to used as Alternate function. - * This parameter can be one of the following values: - * @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) - * @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) - * @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) - * @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) - * @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset) - * @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1 - * @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1 - * @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2 - * @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2 - * @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2 - * @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3 - * @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3 - * @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3 - * @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3 - * @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4 - * @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4 - * @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4 - * @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5 - * @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5 - * @arg GPIO_AF_SPI4: Connect SPI4 pins to AF5 - * @arg GPIO_AF_SPI5: Connect SPI5 pins to AF5 - * @arg GPIO_AF_SPI6: Connect SPI6 pins to AF5 - * @arg GPIO_AF_SAI1: Connect SAI1 pins to AF6 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6 - * @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7 - * @arg GPIO_AF_USART1: Connect USART1 pins to AF7 - * @arg GPIO_AF_USART2: Connect USART2 pins to AF7 - * @arg GPIO_AF_USART3: Connect USART3 pins to AF7 - * @arg GPIO_AF_UART4: Connect UART4 pins to AF8 - * @arg GPIO_AF_UART5: Connect UART5 pins to AF8 - * @arg GPIO_AF_USART6: Connect USART6 pins to AF8 - * @arg GPIO_AF_UART7: Connect UART7 pins to AF8 - * @arg GPIO_AF_UART8: Connect UART8 pins to AF8 - * @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9 - * @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9 - * @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9 - * @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9 - * @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9 - * @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10 - * @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10 - * @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11 - * @arg GPIO_AF_FSMC: Connect FSMC pins to AF12 - * @arg GPIO_AF_FMC: Connect FMC pins to AF12 for STM32F42xxx/43xxx devices. - * @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12 - * @arg GPIO_AF_SDIO: Connect SDIO pins to AF12 - * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 - * @arg GPIO_AF_LTDC: Connect LTDC pins to AF14 for STM32F429xx/439xx devices. - * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 - * @retval None - */ -void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) -{ - uint32_t temp = 0x00; - uint32_t temp_2 = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); - assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); - assert_param(IS_GPIO_AF(GPIO_AF)); - - temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; - temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; - GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c deleted file mode 100644 index 0be685d2d..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c +++ /dev/null @@ -1,726 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the HASH / HMAC Processor (HASH) peripheral: - * - Initialization and Configuration functions - * - Message Digest generation functions - * - context swapping functions - * - DMA interface function - * - Interrupts and flags management - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - - *** HASH operation : *** - ======================== - [..] - (#) Enable the HASH controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function. - - (#) Initialize the HASH using HASH_Init() function. - - (#) Reset the HASH processor core, so that the HASH will be ready - to compute he message digest of a new message by using HASH_Reset() function. - - (#) Enable the HASH controller using the HASH_Cmd() function. - - (#) if using DMA for Data input transfer, Activate the DMA Request - using HASH_DMACmd() function - - (#) if DMA is not used for data transfer, use HASH_DataIn() function - to enter data to IN FIFO. - - - (#) Configure the Number of valid bits in last word of the message - using HASH_SetLastWordValidBitsNbr() function. - - (#) if the message length is not an exact multiple of 512 bits, - then the function HASH_StartDigest() must be called to launch the computation - of the final digest. - - (#) Once computed, the digest can be read using HASH_GetDigest() function. - - (#) To control HASH events you can use one of the following wo methods: - (++) Check on HASH flags using the HASH_GetFlagStatus() function. - (++) Use HASH interrupts through the function HASH_ITConfig() at - initialization phase and HASH_GetITStatus() function into - interrupt routines in hashing phase. - After checking on a flag you should clear it using HASH_ClearFlag() - function. And after checking on an interrupt event you should - clear it using HASH_ClearITPendingBit() function. - - (#) Save and restore hash processor context using - HASH_SaveContext() and HASH_RestoreContext() functions. - - - - *** HMAC operation : *** - ======================== - [..] The HMAC algorithm is used for message authentication, by - irreversibly binding the message being processed to a key chosen - by the user. - For HMAC specifications, refer to "HMAC: keyed-hashing for message - authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997" - - [..] Basically, the HMAC algorithm consists of two nested hash operations: - HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)] - where: - (+) "pad" is a sequence of zeroes needed to extend the key to the - length of the underlying hash function data block (that is - 512 bits for both the SHA-1 and MD5 hash algorithms) - (+) "|" represents the concatenation operator - - - [..]To compute the HMAC, four different phases are required: - (#) Initialize the HASH using HASH_Init() function to do HMAC - operation. - - (#) The key (to be used for the inner hash function) is then given to the core. - This operation follows the same mechanism as the one used to send the - message in the hash operation (that is, by HASH_DataIn() function and, - finally, HASH_StartDigest() function. - - (#) Once the last word has been entered and computation has started, - the hash processor elaborates the key. It is then ready to accept the message - text using the same mechanism as the one used to send the message in the - hash operation. - - (#) After the first hash round, the hash processor returns "ready" to indicate - that it is ready to receive the key to be used for the outer hash function - (normally, this key is the same as the one used for the inner hash function). - When the last word of the key is entered and computation starts, the HMAC - result is made available using HASH_GetDigest() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the HASH peripheral - (+) Configure the HASH Processor - (+) MD5/SHA1, - (+) HASH/HMAC, - (+) datatype - (+) HMAC Key (if mode = HMAC) - (+) Reset the HASH Processor - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the HASH peripheral registers to their default reset values - * @param None - * @retval None - */ -void HASH_DeInit(void) -{ - /* Enable HASH reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE); - /* Release HASH from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE); -} - -/** - * @brief Initializes the HASH peripheral according to the specified parameters - * in the HASH_InitStruct structure. - * @note the hash processor is reset when calling this function so that the - * HASH will be ready to compute the message digest of a new message. - * There is no need to call HASH_Reset() function. - * @param HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains - * the configuration information for the HASH peripheral. - * @note The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only - * if the algorithm mode is HMAC. - * @retval None - */ -void HASH_Init(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection)); - assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType)); - assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode)); - - /* Configure the Algorithm used, algorithm mode and the datatype */ - HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE); - HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \ - HASH_InitStruct->HASH_DataType | \ - HASH_InitStruct->HASH_AlgoMode); - - /* if algorithm mode is HMAC, set the Key */ - if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) - { - assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType)); - HASH->CR &= ~HASH_CR_LKEY; - HASH->CR |= HASH_InitStruct->HASH_HMACKeyType; - } - - /* Reset the HASH processor core, so that the HASH will be ready to compute - the message digest of a new message */ - HASH->CR |= HASH_CR_INIT; -} - -/** - * @brief Fills each HASH_InitStruct member with its default value. - * @param HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will - * be initialized. - * @note The default values set are : Processor mode is HASH, Algorithm selected is SHA1, - * Data type selected is 32b and HMAC Key Type is short key. - * @retval None - */ -void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct) -{ - /* Initialize the HASH_AlgoSelection member */ - HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - - /* Initialize the HASH_AlgoMode member */ - HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH; - - /* Initialize the HASH_DataType member */ - HASH_InitStruct->HASH_DataType = HASH_DataType_32b; - - /* Initialize the HASH_HMACKeyType member */ - HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; -} - -/** - * @brief Resets the HASH processor core, so that the HASH will be ready - * to compute the message digest of a new message. - * @note Calling this function will clear the HASH_SR_DCIS (Digest calculation - * completion interrupt status) bit corresponding to HASH_IT_DCI - * interrupt and HASH_FLAG_DCIS flag. - * @param None - * @retval None - */ -void HASH_Reset(void) -{ - /* Reset the HASH processor core */ - HASH->CR |= HASH_CR_INIT; -} -/** - * @} - */ - -/** @defgroup HASH_Group2 Message Digest generation functions - * @brief Message Digest generation functions - * -@verbatim - =============================================================================== - ##### Message Digest generation functions ##### - =============================================================================== - [..] This section provides functions allowing the generation of message digest: - (+) Push data in the IN FIFO : using HASH_DataIn() - (+) Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr() - (+) set the last word valid bits number using HASH_SetLastWordValidBitsNbr() - (+) start digest calculation : using HASH_StartDigest() - (+) Get the Digest message : using HASH_GetDigest() - -@endverbatim - * @{ - */ - - -/** - * @brief Configure the Number of valid bits in last word of the message - * @param ValidNumber: Number of valid bits in last word of the message. - * This parameter must be a number between 0 and 0x1F. - * - 0x00: All 32 bits of the last data written are valid - * - 0x01: Only bit [0] of the last data written is valid - * - 0x02: Only bits[1:0] of the last data written are valid - * - 0x03: Only bits[2:0] of the last data written are valid - * - ... - * - 0x1F: Only bits[30:0] of the last data written are valid - * @note The Number of valid bits must be set before to start the message - * digest competition (in Hash and HMAC) and key treatment(in HMAC). - * @retval None - */ -void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber) -{ - /* Check the parameters */ - assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber)); - - /* Configure the Number of valid bits in last word of the message */ - HASH->STR &= ~(HASH_STR_NBW); - HASH->STR |= ValidNumber; -} - -/** - * @brief Writes data in the Data Input FIFO - * @param Data: new data of the message to be processed. - * @retval None - */ -void HASH_DataIn(uint32_t Data) -{ - /* Write in the DIN register a new data */ - HASH->DIN = Data; -} - -/** - * @brief Returns the number of words already pushed into the IN FIFO. - * @param None - * @retval The value of words already pushed into the IN FIFO. - */ -uint8_t HASH_GetInFIFOWordsNbr(void) -{ - /* Return the value of NBW bits */ - return ((HASH->CR & HASH_CR_NBW) >> 8); -} - -/** - * @brief Provides the message digest result. - * @note In MD5 mode, Data[7] to Data[4] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * In SHA-1 mode, Data[7] to Data[5] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * In SHA-224 mode, Data[7] filed of HASH_MsgDigest structure is not used - * and is read as zero. - * @param HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will - * hold the message digest result - * @retval None - */ -void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest) -{ - /* Get the data field */ - HASH_MessageDigest->Data[0] = HASH->HR[0]; - HASH_MessageDigest->Data[1] = HASH->HR[1]; - HASH_MessageDigest->Data[2] = HASH->HR[2]; - HASH_MessageDigest->Data[3] = HASH->HR[3]; - HASH_MessageDigest->Data[4] = HASH->HR[4]; - HASH_MessageDigest->Data[5] = HASH_DIGEST->HR[5]; - HASH_MessageDigest->Data[6] = HASH_DIGEST->HR[6]; - HASH_MessageDigest->Data[7] = HASH_DIGEST->HR[7]; -} - -/** - * @brief Starts the message padding and calculation of the final message - * @param None - * @retval None - */ -void HASH_StartDigest(void) -{ - /* Start the Digest calculation */ - HASH->STR |= HASH_STR_DCAL; -} -/** - * @} - */ - -/** @defgroup HASH_Group3 Context swapping functions - * @brief Context swapping functions - * -@verbatim - =============================================================================== - ##### Context swapping functions ##### - =============================================================================== - - [..] This section provides functions allowing to save and store HASH Context - - [..] It is possible to interrupt a HASH/HMAC process to perform another processing - with a higher priority, and to complete the interrupted process later on, when - the higher priority task is complete. To do so, the context of the interrupted - task must be saved from the HASH registers to memory, and then be restored - from memory to the HASH registers. - - (#) To save the current context, use HASH_SaveContext() function - (#) To restore the saved context, use HASH_RestoreContext() function - - -@endverbatim - * @{ - */ - -/** - * @brief Save the Hash peripheral Context. - * @note The context can be saved only when no block is currently being - * processed. So user must wait for DINIS = 1 (the last block has been - * processed and the input FIFO is empty) or NBW != 0 (the FIFO is not - * full and no processing is ongoing). - * @param HASH_ContextSave: pointer to a HASH_Context structure that contains - * the repository for current context. - * @retval None - */ -void HASH_SaveContext(HASH_Context* HASH_ContextSave) -{ - uint8_t i = 0; - - /* save context registers */ - HASH_ContextSave->HASH_IMR = HASH->IMR; - HASH_ContextSave->HASH_STR = HASH->STR; - HASH_ContextSave->HASH_CR = HASH->CR; - for(i=0; i<=53;i++) - { - HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i]; - } -} - -/** - * @brief Restore the Hash peripheral Context. - * @note After calling this function, user can restart the processing from the - * point where it has been interrupted. - * @param HASH_ContextRestore: pointer to a HASH_Context structure that contains - * the repository for saved context. - * @retval None - */ -void HASH_RestoreContext(HASH_Context* HASH_ContextRestore) -{ - uint8_t i = 0; - - /* restore context registers */ - HASH->IMR = HASH_ContextRestore->HASH_IMR; - HASH->STR = HASH_ContextRestore->HASH_STR; - HASH->CR = HASH_ContextRestore->HASH_CR; - - /* Initialize the hash processor */ - HASH->CR |= HASH_CR_INIT; - - /* continue restoring context registers */ - for(i=0; i<=53;i++) - { - HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i]; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group4 HASH's DMA interface Configuration function - * @brief HASH's DMA interface Configuration function - * -@verbatim - =============================================================================== - ##### HASH's DMA interface Configuration function ##### - =============================================================================== - - [..] This section provides functions allowing to configure the DMA interface for - HASH/ HMAC data input transfer. - - [..] When the DMA mode is enabled (using the HASH_DMACmd() function), data can be - sent to the IN FIFO using the DMA peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables auto-start message padding and - * calculation of the final message digest at the end of DMA transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_AutoStartDigest(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the auto start of the final message digest at the end of DMA transfer */ - HASH->CR &= ~HASH_CR_MDMAT; - } - else - { - /* Disable the auto start of the final message digest at the end of DMA transfer */ - HASH->CR |= HASH_CR_MDMAT; - } -} - -/** - * @brief Enables or disables the HASH DMA interface. - * @note The DMA is disabled by hardware after the end of transfer. - * @param NewState: new state of the selected HASH DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the HASH DMA request */ - HASH->CR |= HASH_CR_DMAE; - } - else - { - /* Disable the HASH DMA request */ - HASH->CR &= ~HASH_CR_DMAE; - } -} -/** - * @} - */ - -/** @defgroup HASH_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the HASH Interrupts and - to get the status and clear flags and Interrupts pending bits. - - [..] The HASH provides 2 Interrupts sources and 5 Flags: - - *** Flags : *** - =============== - [..] - (#) HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO - which means that a new block (512 bit) can be entered into the input buffer. - - (#) HASH_FLAG_DCIS : set when Digest calculation is complete - - (#) HASH_FLAG_DMAS : set when HASH's DMA interface is enabled (DMAE=1) or - a transfer is ongoing. This Flag is cleared only by hardware. - - (#) HASH_FLAG_BUSY : set when The hash core is processing a block of data - This Flag is cleared only by hardware. - - (#) HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that - the Data IN FIFO contains at least one word of data. This Flag is cleared - only by hardware. - - *** Interrupts : *** - ==================== - [..] - (#) HASH_IT_DINI : if enabled, this interrupt source is pending when 16 - locations are free in the Data IN FIFO which means that a new block (512 bit) - can be entered into the input buffer. This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DINI) function. - - (#) HASH_IT_DCI : if enabled, this interrupt source is pending when Digest - calculation is complete. This interrupt source is cleared using - HASH_ClearITPendingBit(HASH_IT_DCI) function. - - *** Managing the HASH controller events : *** - ============================================= - [..] The user should identify which mode will be used in his application to manage - the HASH controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) HASH_GetFlagStatus() : to check if flags events occur. - (++) HASH_ClearFlag() : to clear the flags events. - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) HASH_ITConfig() : to enable or disable the interrupt source. - (++) HASH_GetITStatus() : to check if Interrupt occurs. - (++) HASH_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified HASH interrupts. - * @param HASH_IT: specifies the HASH interrupt source to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @param NewState: new state of the specified HASH interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected HASH interrupt */ - HASH->IMR |= HASH_IT; - } - else - { - /* Disable the selected HASH interrupt */ - HASH->IMR &= (uint32_t)(~HASH_IT); - } -} - -/** - * @brief Checks whether the specified HASH flag is set or not. - * @param HASH_FLAG: specifies the HASH flag to check. - * This parameter can be one of the following values: - * @arg HASH_FLAG_DINIS: Data input interrupt status flag - * @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag - * @arg HASH_FLAG_BUSY: Busy flag - * @arg HASH_FLAG_DMAS: DMAS Status flag - * @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag - * @retval The new state of HASH_FLAG (SET or RESET) - */ -FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tempreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_FLAG(HASH_FLAG)); - - /* check if the FLAG is in CR register */ - if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint32_t)RESET ) - { - tempreg = HASH->CR; - } - else /* The FLAG is in SR register */ - { - tempreg = HASH->SR; - } - - /* Check the status of the specified HASH flag */ - if ((tempreg & HASH_FLAG) != (uint32_t)RESET) - { - /* HASH is set */ - bitstatus = SET; - } - else - { - /* HASH_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the HASH_FLAG status */ - return bitstatus; -} -/** - * @brief Clears the HASH flags. - * @param HASH_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg HASH_FLAG_DINIS: Data Input Flag - * @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag - * @retval None - */ -void HASH_ClearFlag(uint32_t HASH_FLAG) -{ - /* Check the parameters */ - assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG)); - - /* Clear the selected HASH flags */ - HASH->SR = ~(uint32_t)HASH_FLAG; -} -/** - * @brief Checks whether the specified HASH interrupt has occurred or not. - * @param HASH_IT: specifies the HASH interrupt source to check. - * This parameter can be one of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval The new state of HASH_IT (SET or RESET). - */ -ITStatus HASH_GetITStatus(uint32_t HASH_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_HASH_GET_IT(HASH_IT)); - - - /* Check the status of the specified HASH interrupt */ - tmpreg = HASH->SR; - - if (((HASH->IMR & tmpreg) & HASH_IT) != RESET) - { - /* HASH_IT is set */ - bitstatus = SET; - } - else - { - /* HASH_IT is reset */ - bitstatus = RESET; - } - /* Return the HASH_IT status */ - return bitstatus; -} - -/** - * @brief Clears the HASH interrupt pending bit(s). - * @param HASH_IT: specifies the HASH interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg HASH_IT_DINI: Data Input interrupt - * @arg HASH_IT_DCI: Digest Calculation Completion Interrupt - * @retval None - */ -void HASH_ClearITPendingBit(uint32_t HASH_IT) -{ - /* Check the parameters */ - assert_param(IS_HASH_IT(HASH_IT)); - - /* Clear the selected HASH interrupt pending bit */ - HASH->SR = (uint32_t)(~HASH_IT); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c deleted file mode 100644 index ab374a0fe..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c +++ /dev/null @@ -1,320 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_hash_md5.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides high level functions to compute the HASH MD5 and - * HMAC MD5 Digest of an input message. - * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH - * peripheral. - * -@verbatim - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The HASH controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function. - - (#) Calculate the HASH MD5 Digest using HASH_MD5() function. - - (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function. - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group7 High Level MD5 functions - * @brief High Level MD5 Hash and HMAC functions - * -@verbatim - =============================================================================== - ##### High Level MD5 Hash and HMAC functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH MD5 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]) -{ - HASH_InitTypeDef MD5_HASH_InitStructure; - HASH_MsgDigest MD5_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5; - MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&MD5_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; i
© COPYRIGHT 2016 STMicroelectronics
- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_hash.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup HASH - * @brief HASH driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HASH_Private_Functions - * @{ - */ - -/** @defgroup HASH_Group6 High Level SHA1 functions - * @brief High Level SHA1 Hash and HMAC functions - * -@verbatim - =============================================================================== - ##### High Level SHA1 Hash and HMAC functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Compute the HASH SHA1 digest. - * @param Input: pointer to the Input buffer to be treated. - * @param Ilen: length of the Input buffer. - * @param Output: the returned digest - * @retval An ErrorStatus enumeration value: - * - SUCCESS: digest computation done - * - ERROR: digest computation failed - */ -ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]) -{ - HASH_InitTypeDef SHA1_HASH_InitStructure; - HASH_MsgDigest SHA1_MessageDigest; - __IO uint16_t nbvalidbitsdata = 0; - uint32_t i = 0; - __IO uint32_t counter = 0; - uint32_t busystatus = 0; - ErrorStatus status = SUCCESS; - uint32_t inputaddr = (uint32_t)Input; - uint32_t outputaddr = (uint32_t)Output; - - /* Number of valid bits in last word of the Input data */ - nbvalidbitsdata = 8 * (Ilen % 4); - - /* HASH peripheral initialization */ - HASH_DeInit(); - - /* HASH Configuration */ - SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1; - SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH; - SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b; - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the data */ - HASH_SetLastWordValidBitsNbr(nbvalidbitsdata); - - /* Write the Input block in the IN FIFO */ - for(i=0; i 64) - { - /* HMAC long Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey; - } - else - { - /* HMAC short Key */ - SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey; - } - HASH_Init(&SHA1_HASH_InitStructure); - - /* Configure the number of valid bits in last word of the Key */ - HASH_SetLastWordValidBitsNbr(nbvalidbitskey); - - /* Write the Key */ - for(i=0; iGPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - Recommended configuration is Push-Pull, Pull-up, Open-Drain. - Add an external pull up if necessary (typically 4.7 KOhm). - - (#) Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged - Address using the I2C_Init() function. - - (#) Optionally you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again I2C_Init() function): - (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function - (++) Enable the dual addressing mode using I2C_DualAddressCmd() function - (++) Enable the general call using the I2C_GeneralCallCmd() function - (++) Enable the clock stretching using I2C_StretchClockCmd() function - (++) Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig() - function. - (++) Configure the NACK position for Master Receiver mode in case of - 2 bytes reception using the function I2C_NACKPositionConfig(). - (++) Enable the PEC Calculation using I2C_CalculatePEC() function - (++) For SMBus Mode: - (+++) Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function - (+++) Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function - - (#) Enable the NVIC and the corresponding interrupt using the function - I2C_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using I2C_DMACmd() or - I2C_DMALastTransferCmd() function. - -@@- When using DMA mode, I2C interrupts may be used at the same time to - control the communication flow (Start/Stop/Ack... events and errors). - - (#) Enable the I2C using the I2C_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the - transfers. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_i2c.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup I2C - * @brief I2C driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -#define CR1_CLEAR_MASK ((uint16_t)0xFBF5) /*I2C_ClockSpeed)); - assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle)); - assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); - assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack)); - assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); - -/*---------------------------- I2Cx CR2 Configuration ------------------------*/ - /* Get the I2Cx CR2 value */ - tmpreg = I2Cx->CR2; - /* Clear frequency FREQ[5:0] bits */ - tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ); - /* Get pclk1 frequency value */ - RCC_GetClocksFreq(&rcc_clocks); - pclk1 = rcc_clocks.PCLK1_Frequency; - /* Set frequency bits depending on pclk1 value */ - freqrange = (uint16_t)(pclk1 / 1000000); - tmpreg |= freqrange; - /* Write to I2Cx CR2 */ - I2Cx->CR2 = tmpreg; - -/*---------------------------- I2Cx CCR Configuration ------------------------*/ - /* Disable the selected I2C peripheral to configure TRISE */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - /* Reset tmpreg value */ - /* Clear F/S, DUTY and CCR[11:0] bits */ - tmpreg = 0; - - /* Configure speed in standard mode */ - if (I2C_InitStruct->I2C_ClockSpeed <= 100000) - { - /* Standard mode speed calculate */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); - /* Test if CCR value is under 0x4*/ - if (result < 0x04) - { - /* Set minimum allowed value */ - result = 0x04; - } - /* Set speed value for standard mode */ - tmpreg |= result; - /* Set Maximum Rise Time for standard mode */ - I2Cx->TRISE = freqrange + 1; - } - /* Configure speed in fast mode */ - /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral - input clock) must be a multiple of 10 MHz */ - else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/ - { - if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) - { - /* Fast mode speed calculate: Tlow/Thigh = 2 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); - } - else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/ - { - /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ - result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); - /* Set DUTY bit */ - result |= I2C_DutyCycle_16_9; - } - - /* Test if CCR value is under 0x1*/ - if ((result & I2C_CCR_CCR) == 0) - { - /* Set minimum allowed value */ - result |= (uint16_t)0x0001; - } - /* Set speed value and set F/S bit for fast mode */ - tmpreg |= (uint16_t)(result | I2C_CCR_FS); - /* Set Maximum Rise Time for fast mode */ - I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); - } - - /* Write to I2Cx CCR */ - I2Cx->CCR = tmpreg; - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - -/*---------------------------- I2Cx CR1 Configuration ------------------------*/ - /* Get the I2Cx CR1 value */ - tmpreg = I2Cx->CR1; - /* Clear ACK, SMBTYPE and SMBUS bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure I2Cx: mode and acknowledgement */ - /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */ - /* Set ACK bit according to I2C_Ack value */ - tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); - /* Write to I2Cx CR1 */ - I2Cx->CR1 = tmpreg; - -/*---------------------------- I2Cx OAR1 Configuration -----------------------*/ - /* Set I2Cx Own Address1 and acknowledged address */ - I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); -} - -/** - * @brief Fills each I2C_InitStruct member with its default value. - * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) -{ -/*---------------- Reset I2C init structure parameters values ----------------*/ - /* initialize the I2C_ClockSpeed member */ - I2C_InitStruct->I2C_ClockSpeed = 5000; - /* Initialize the I2C_Mode member */ - I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; - /* Initialize the I2C_DutyCycle member */ - I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; - /* Initialize the I2C_OwnAddress1 member */ - I2C_InitStruct->I2C_OwnAddress1 = 0; - /* Initialize the I2C_Ack member */ - I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; - /* Initialize the I2C_AcknowledgedAddress member */ - I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; -} - -/** - * @brief Enables or disables the specified I2C peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C peripheral */ - I2Cx->CR1 |= I2C_CR1_PE; - } - else - { - /* Disable the selected I2C peripheral */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE); - } -} - -/** - * @brief Enables or disables the Analog filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the Analog filter. - * This parameter can be: ENABLE or DISABLE. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the analog filter */ - I2Cx->FLTR &= (uint16_t)~((uint16_t)I2C_FLTR_ANOFF); - } - else - { - /* Disable the analog filter */ - I2Cx->FLTR |= I2C_FLTR_ANOFF; - } -} - -/** - * @brief Configures the Digital noise filter of I2C peripheral. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices. - * - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DigitalFilter: Coefficient of digital noise filter. - * This parameter can be a number between 0x00 and 0x0F. - * @note This function should be called before initializing and enabling - the I2C Peripheral. - * @retval None - */ -void I2C_DigitalFilterConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DigitalFilter) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIGITAL_FILTER(I2C_DigitalFilter)); - - /* Get the old register value */ - tmpreg = I2Cx->FLTR; - - /* Reset I2Cx DNF bit [3:0] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_FLTR_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= (uint16_t)((uint16_t)I2C_DigitalFilter & I2C_FLTR_DNF); - - /* Store the new register value */ - I2Cx->FLTR = tmpreg; -} - -/** - * @brief Generates I2Cx communication START condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C START condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a START condition */ - I2Cx->CR1 |= I2C_CR1_START; - } - else - { - /* Disable the START condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START); - } -} - -/** - * @brief Generates I2Cx communication STOP condition. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C STOP condition generation. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Generate a STOP condition */ - I2Cx->CR1 |= I2C_CR1_STOP; - } - else - { - /* Disable the STOP condition generation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP); - } -} - -/** - * @brief Transmits the address byte to select the slave device. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the slave address which will be transmitted - * @param I2C_Direction: specifies whether the I2C device will be a Transmitter - * or a Receiver. - * This parameter can be one of the following values - * @arg I2C_Direction_Transmitter: Transmitter mode - * @arg I2C_Direction_Receiver: Receiver mode - * @retval None. - */ -void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DIRECTION(I2C_Direction)); - /* Test on the direction to set/reset the read/write bit */ - if (I2C_Direction != I2C_Direction_Transmitter) - { - /* Set the address bit0 for read */ - Address |= I2C_OAR1_ADD0; - } - else - { - /* Reset the address bit0 for write */ - Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0); - } - /* Send the address */ - I2Cx->DR = Address; -} - -/** - * @brief Enables or disables the specified I2C acknowledge feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C Acknowledgement. - * This parameter can be: ENABLE or DISABLE. - * @retval None. - */ -void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the acknowledgement */ - I2Cx->CR1 |= I2C_CR1_ACK; - } - else - { - /* Disable the acknowledgement */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK); - } -} - -/** - * @brief Configures the specified I2C own address2. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Address: specifies the 7bit I2C own address2. - * @retval None. - */ -void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address) -{ - uint16_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Get the old register value */ - tmpreg = I2Cx->OAR2; - - /* Reset I2Cx Own address2 bit [7:1] */ - tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2); - - /* Set I2Cx Own address2 */ - tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); - - /* Store the new register value */ - I2Cx->OAR2 = tmpreg; -} - -/** - * @brief Enables or disables the specified I2C dual addressing mode. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C dual addressing mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable dual addressing mode */ - I2Cx->OAR2 |= I2C_OAR2_ENDUAL; - } - else - { - /* Disable dual addressing mode */ - I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL); - } -} - -/** - * @brief Enables or disables the specified I2C general call feature. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C General call. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable general call */ - I2Cx->CR1 |= I2C_CR1_ENGC; - } - else - { - /* Disable general call */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC); - } -} - -/** - * @brief Enables or disables the specified I2C software reset. - * @note When software reset is enabled, the I2C IOs are released (this can - * be useful to recover from bus errors). - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C software reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Peripheral under reset */ - I2Cx->CR1 |= I2C_CR1_SWRST; - } - else - { - /* Peripheral not under reset */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST); - } -} - -/** - * @brief Enables or disables the specified I2C Clock stretching. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx Clock stretching. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState == DISABLE) - { - /* Enable the selected I2C Clock stretching */ - I2Cx->CR1 |= I2C_CR1_NOSTRETCH; - } - else - { - /* Disable the selected I2C Clock stretching */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH); - } -} - -/** - * @brief Selects the specified I2C fast mode duty cycle. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_DutyCycle: specifies the fast mode duty cycle. - * This parameter can be one of the following values: - * @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2 - * @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9 - * @retval None - */ -void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle)); - if (I2C_DutyCycle != I2C_DutyCycle_16_9) - { - /* I2C fast mode Tlow/Thigh=2 */ - I2Cx->CCR &= I2C_DutyCycle_2; - } - else - { - /* I2C fast mode Tlow/Thigh=16/9 */ - I2Cx->CCR |= I2C_DutyCycle_16_9; - } -} - -/** - * @brief Selects the specified I2C NACK position in master receiver mode. - * @note This function is useful in I2C Master Receiver mode when the number - * of data to be received is equal to 2. In this case, this function - * should be called (with parameter I2C_NACKPosition_Next) before data - * reception starts,as described in the 2-byte reception procedure - * recommended in Reference Manual in Section: Master receiver. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_NACKPosition: specifies the NACK position. - * This parameter can be one of the following values: - * @arg I2C_NACKPosition_Next: indicates that the next byte will be the last - * received byte. - * @arg I2C_NACKPosition_Current: indicates that current byte is the last - * received byte. - * - * @note This function configures the same bit (POS) as I2C_PECPositionConfig() - * but is intended to be used in I2C mode while I2C_PECPositionConfig() - * is intended to used in SMBUS mode. - * - * @retval None - */ -void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition)); - - /* Check the input parameter */ - if (I2C_NACKPosition == I2C_NACKPosition_Next) - { - /* Next byte in shift register is the last received byte */ - I2Cx->CR1 |= I2C_NACKPosition_Next; - } - else - { - /* Current byte in shift register is the last received byte */ - I2Cx->CR1 &= I2C_NACKPosition_Current; - } -} - -/** - * @brief Drives the SMBusAlert pin high or low for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_SMBusAlert: specifies SMBAlert pin level. - * This parameter can be one of the following values: - * @arg I2C_SMBusAlert_Low: SMBAlert pin driven low - * @arg I2C_SMBusAlert_High: SMBAlert pin driven high - * @retval None - */ -void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert)); - if (I2C_SMBusAlert == I2C_SMBusAlert_Low) - { - /* Drive the SMBusAlert pin Low */ - I2Cx->CR1 |= I2C_SMBusAlert_Low; - } - else - { - /* Drive the SMBusAlert pin High */ - I2Cx->CR1 &= I2C_SMBusAlert_High; - } -} - -/** - * @brief Enables or disables the specified I2C ARP. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx ARP. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C ARP */ - I2Cx->CR1 |= I2C_CR1_ENARP; - } - else - { - /* Disable the selected I2C ARP */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP); - } -} -/** - * @} - */ - -/** @defgroup I2C_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Sends a data byte through the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param Data: Byte to be transmitted.. - * @retval None - */ -void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Write in the DR register the data to be sent */ - I2Cx->DR = Data; -} - -/** - * @brief Returns the most recent received data by the I2Cx peripheral. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The value of the received data. - */ -uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the data in the DR register */ - return (uint8_t)I2Cx->DR; -} - -/** - * @} - */ - -/** @defgroup I2C_Group3 PEC management functions - * @brief PEC management functions - * -@verbatim - =============================================================================== - ##### PEC management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C PEC transfer. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C PEC transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC transmission */ - I2Cx->CR1 |= I2C_CR1_PEC; - } - else - { - /* Disable the selected I2C PEC transmission */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC); - } -} - -/** - * @brief Selects the specified I2C PEC position. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_PECPosition: specifies the PEC position. - * This parameter can be one of the following values: - * @arg I2C_PECPosition_Next: indicates that the next byte is PEC - * @arg I2C_PECPosition_Current: indicates that current byte is PEC - * - * @note This function configures the same bit (POS) as I2C_NACKPositionConfig() - * but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() - * is intended to used in I2C mode. - * - * @retval None - */ -void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition)); - if (I2C_PECPosition == I2C_PECPosition_Next) - { - /* Next byte in shift register is PEC */ - I2Cx->CR1 |= I2C_PECPosition_Next; - } - else - { - /* Current byte in shift register is PEC */ - I2Cx->CR1 &= I2C_PECPosition_Current; - } -} - -/** - * @brief Enables or disables the PEC value calculation of the transferred bytes. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2Cx PEC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C PEC calculation */ - I2Cx->CR1 |= I2C_CR1_ENPEC; - } - else - { - /* Disable the selected I2C PEC calculation */ - I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC); - } -} - -/** - * @brief Returns the PEC value for the specified I2C. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @retval The PEC value. - */ -uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - /* Return the selected I2C PEC value */ - return ((I2Cx->SR2) >> 8); -} - -/** - * @} - */ - -/** @defgroup I2C_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - This section provides functions allowing to configure the I2C DMA channels - requests. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified I2C DMA requests. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected I2C DMA requests */ - I2Cx->CR2 |= I2C_CR2_DMAEN; - } - else - { - /* Disable the selected I2C DMA requests */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN); - } -} - -/** - * @brief Specifies that the next DMA transfer is the last one. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param NewState: new state of the I2C DMA last transfer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Next DMA transfer is the last transfer */ - I2Cx->CR2 |= I2C_CR2_LAST; - } - else - { - /* Next DMA transfer is not the last transfer */ - I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST); - } -} - -/** - * @} - */ - -/** @defgroup I2C_Group5 Interrupts events and flags management functions - * @brief Interrupts, events and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, events and flags management functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the I2C Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - - ##### I2C State Monitoring Functions ##### - =============================================================================== - [..] - This I2C driver provides three different ways for I2C state monitoring - depending on the application requirements and constraints: - - - (#) Basic state monitoring (Using I2C_CheckEvent() function) - - It compares the status registers (SR1 and SR2) content to a given event - (can be the combination of one or more flags). - It returns SUCCESS if the current status includes the given flags - and returns ERROR if one or more flags are missing in the current status. - - (++) When to use - (+++) This function is suitable for most applications as well as for startup - activity since the events are fully described in the product reference - manual (RM0090). - (+++) It is also suitable for users who need to define their own events. - - (++) Limitations - If an error occurs (ie. error flags are set besides to the monitored - flags), the I2C_CheckEvent() function may return SUCCESS despite - the communication hold or corrupted real state. - In this case, it is advised to use error interrupts to monitor - the error events and handle them in the interrupt IRQ handler. - - -@@- For error management, it is advised to use the following functions: - (+@@) I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR). - (+@@) I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. - Where x is the peripheral instance (I2C1, I2C2 ...) - (+@@) I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the - I2Cx_ER_IRQHandler() function in order to determine which error occurred. - (+@@) I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() - and/or I2C_GenerateStop() in order to clear the error flag and source - and return to correct communication status. - - - (#) Advanced state monitoring (Using the function I2C_GetLastEvent()) - - Using the function I2C_GetLastEvent() which returns the image of both status - registers in a single word (uint32_t) (Status Register 2 value is shifted left - by 16 bits and concatenated to Status Register 1). - - (++) When to use - (+++) This function is suitable for the same applications above but it - allows to overcome the mentioned limitation of I2C_GetFlagStatus() - function. - (+++) The returned value could be compared to events already defined in - the library (stm32f4xx_i2c.h) or to custom values defined by user. - This function is suitable when multiple flags are monitored at the - same time. - (+++) At the opposite of I2C_CheckEvent() function, this function allows - user to choose when an event is accepted (when all events flags are - set and no other flags are set or just when the needed flags are set - like I2C_CheckEvent() function. - - (++) Limitations - (+++) User may need to define his own events. - (+++) Same remark concerning the error management is applicable for this - function if user decides to check only regular communication flags - (and ignores error flags). - - - (#) Flag-based state monitoring (Using the function I2C_GetFlagStatus()) - - Using the function I2C_GetFlagStatus() which simply returns the status of - one single flag (ie. I2C_FLAG_RXNE ...). - - (++) When to use - (+++) This function could be used for specific applications or in debug - phase. - (+++) It is suitable when only one flag checking is needed (most I2C - events are monitored through multiple flags). - (++) Limitations: - (+++) When calling this function, the Status register is accessed. - Some flags are cleared when the status register is accessed. - So checking the status of one Flag, may clear other ones. - (+++) Function may need to be called twice or more in order to monitor - one single event. - - For detailed description of Events, please refer to section I2C_Events in - stm32f4xx_i2c.h file. - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified I2C register and returns its value. - * @param I2C_Register: specifies the register to read. - * This parameter can be one of the following values: - * @arg I2C_Register_CR1: CR1 register. - * @arg I2C_Register_CR2: CR2 register. - * @arg I2C_Register_OAR1: OAR1 register. - * @arg I2C_Register_OAR2: OAR2 register. - * @arg I2C_Register_DR: DR register. - * @arg I2C_Register_SR1: SR1 register. - * @arg I2C_Register_SR2: SR2 register. - * @arg I2C_Register_CCR: CCR register. - * @arg I2C_Register_TRISE: TRISE register. - * @retval The value of the read register. - */ -uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_REGISTER(I2C_Register)); - - tmp = (uint32_t) I2Cx; - tmp += I2C_Register; - - /* Return the selected register value */ - return (*(__IO uint16_t *) tmp); -} - -/** - * @brief Enables or disables the specified I2C interrupts. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg I2C_IT_BUF: Buffer interrupt mask - * @arg I2C_IT_EVT: Event interrupt mask - * @arg I2C_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified I2C interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_I2C_CONFIG_IT(I2C_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected I2C interrupts */ - I2Cx->CR2 |= I2C_IT; - } - else - { - /* Disable the selected I2C interrupts */ - I2Cx->CR2 &= (uint16_t)~I2C_IT; - } -} - -/* - =============================================================================== - 1. Basic state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the last I2Cx Event is equal to the one passed - * as parameter. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_EVENT: specifies the event to be checked. - * This parameter can be one of the following values: - * @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1 - * @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2 - * @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2 - * @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3 - * @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3 - * @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2 - * @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4 - * @arg I2C_EVENT_MASTER_MODE_SELECT: EV5 - * @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6 - * @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8 - * @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2 - * @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9 - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Last event is equal to the I2C_EVENT - * - ERROR: Last event is different from the I2C_EVENT - */ -ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_EVENT(I2C_EVENT)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Check whether the last event contains the I2C_EVENT */ - if ((lastevent & I2C_EVENT) == I2C_EVENT) - { - /* SUCCESS: last event is equal to I2C_EVENT */ - status = SUCCESS; - } - else - { - /* ERROR: last event is different from I2C_EVENT */ - status = ERROR; - } - /* Return status */ - return status; -} - -/* - =============================================================================== - 2. Advanced state monitoring - =============================================================================== - */ - -/** - * @brief Returns the last I2Cx Event. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * - * @note For detailed description of Events, please refer to section I2C_Events - * in stm32f4xx_i2c.h file. - * - * @retval The last event - */ -uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx) -{ - uint32_t lastevent = 0; - uint32_t flag1 = 0, flag2 = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - - /* Read the I2Cx status register */ - flag1 = I2Cx->SR1; - flag2 = I2Cx->SR2; - flag2 = flag2 << 16; - - /* Get the last event value from I2C status register */ - lastevent = (flag1 | flag2) & FLAG_MASK; - - /* Return status */ - return lastevent; -} - -/* - =============================================================================== - 3. Flag-based state monitoring - =============================================================================== - */ - -/** - * @brief Checks whether the specified I2C flag is set or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2C_FLAG_DUALF: Dual flag (Slave mode) - * @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode) - * @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode) - * @arg I2C_FLAG_GENCALL: General call header flag (Slave mode) - * @arg I2C_FLAG_TRA: Transmitter/Receiver flag - * @arg I2C_FLAG_BUSY: Bus busy flag - * @arg I2C_FLAG_MSL: Master/Slave flag - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * @arg I2C_FLAG_TXE: Data register empty flag (Transmitter) - * @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag - * @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode) - * @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_FLAG_BTF: Byte transfer finished flag - * @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_FLAG_SB: Start bit flag (Master mode) - * @retval The new state of I2C_FLAG (SET or RESET). - */ -FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - FlagStatus bitstatus = RESET; - __IO uint32_t i2creg = 0, i2cxbase = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); - - /* Get the I2Cx peripheral base address */ - i2cxbase = (uint32_t)I2Cx; - - /* Read flag register index */ - i2creg = I2C_FLAG >> 28; - - /* Get bit[23:0] of the flag */ - I2C_FLAG &= FLAG_MASK; - - if(i2creg != 0) - { - /* Get the I2Cx SR1 register address */ - i2cxbase += 0x14; - } - else - { - /* Flag in I2Cx SR2 Register */ - I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); - /* Get the I2Cx SR2 register address */ - i2cxbase += 0x18; - } - - if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) - { - /* I2C_FLAG is set */ - bitstatus = SET; - } - else - { - /* I2C_FLAG is reset */ - bitstatus = RESET; - } - - /* Return the I2C_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's pending flags. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg I2C_FLAG_SMBALERT: SMBus Alert flag - * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_FLAG_PECERR: PEC error in reception flag - * @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_FLAG_AF: Acknowledge failure flag - * @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_FLAG_BERR: Bus error flag - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation - * to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the - * second byte of the address in DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1 - * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR - * register (I2C_SendData()). - * - * @retval None - */ -void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); - /* Get the I2C flag position */ - flagpos = I2C_FLAG & FLAG_MASK; - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @brief Checks whether the specified I2C interrupt has occurred or not. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt source to check. - * This parameter can be one of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert flag - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag - * @arg I2C_IT_PECERR: PEC error in reception flag - * @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure flag - * @arg I2C_IT_ARLO: Arbitration lost flag (Master mode) - * @arg I2C_IT_BERR: Bus error flag - * @arg I2C_IT_TXE: Data register empty flag (Transmitter) - * @arg I2C_IT_RXNE: Data register not empty (Receiver) flag - * @arg I2C_IT_STOPF: Stop detection flag (Slave mode) - * @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode) - * @arg I2C_IT_BTF: Byte transfer finished flag - * @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL" - * Address matched flag (Slave mode)"ENDAD" - * @arg I2C_IT_SB: Start bit flag (Master mode) - * @retval The new state of I2C_IT (SET or RESET). - */ -ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_GET_IT(I2C_IT)); - - /* Check if the interrupt source is enabled or not */ - enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ; - - /* Get bit[23:0] of the flag */ - I2C_IT &= FLAG_MASK; - - /* Check the status of the specified I2C flag */ - if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) - { - /* I2C_IT is set */ - bitstatus = SET; - } - else - { - /* I2C_IT is reset */ - bitstatus = RESET; - } - /* Return the I2C_IT status */ - return bitstatus; -} - -/** - * @brief Clears the I2Cx's interrupt pending bits. - * @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral. - * @param I2C_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg I2C_IT_SMBALERT: SMBus Alert interrupt - * @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt - * @arg I2C_IT_PECERR: PEC error in reception interrupt - * @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode) - * @arg I2C_IT_AF: Acknowledge failure interrupt - * @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode) - * @arg I2C_IT_BERR: Bus error interrupt - * - * @note STOPF (STOP detection) is cleared by software sequence: a read operation - * to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral). - * @note ADD10 (10-bit header sent) is cleared by software sequence: a read - * operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second - * byte of the address in I2C_DR register. - * @note BTF (Byte Transfer Finished) is cleared by software sequence: a read - * operation to I2C_SR1 register (I2C_GetITStatus()) followed by a - * read/write to I2C_DR register (I2C_SendData()). - * @note ADDR (Address sent) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to - * I2C_SR2 register ((void)(I2Cx->SR2)). - * @note SB (Start Bit) is cleared by software sequence: a read operation to - * I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to - * I2C_DR register (I2C_SendData()). - * @retval None - */ -void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) -{ - uint32_t flagpos = 0; - /* Check the parameters */ - assert_param(IS_I2C_ALL_PERIPH(I2Cx)); - assert_param(IS_I2C_CLEAR_IT(I2C_IT)); - - /* Get the I2C flag position */ - flagpos = I2C_IT & FLAG_MASK; - - /* Clear the selected I2C flag */ - I2Cx->SR1 = (uint16_t)~flagpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c deleted file mode 100644 index 7d131c645..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c +++ /dev/null @@ -1,266 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_iwdg.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Independent watchdog (IWDG) peripheral: - * + Prescaler and Counter configuration - * + IWDG activation - * + Flag management - * - @verbatim - =============================================================================== - ##### IWDG features ##### - =============================================================================== - [..] - The IWDG can be started by either software or hardware (configurable - through option byte). - - The IWDG is clocked by its own dedicated low-speed clock (LSI) and - thus stays active even if the main clock fails. - Once the IWDG is started, the LSI is forced ON and cannot be disabled - (LSI cannot be disabled too), and the counter starts counting down from - the reset value of 0xFFF. When it reaches the end of count value (0x000) - a system reset is generated. - The IWDG counter should be reloaded at regular intervals to prevent - an MCU reset. - - The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). - - IWDGRST flag in RCC_CSR register can be used to inform when a IWDG - reset occurs. - - Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx - devices provide the capability to measure the LSI frequency (LSI clock - connected internally to TIM5 CH4 input capture). The measured value - can be used to have an IWDG timeout with an acceptable accuracy. - For more information, please refer to the STM32F4xx Reference manual - - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable write access to IWDG_PR and IWDG_RLR registers using - IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function - - (#) Configure the IWDG prescaler using IWDG_SetPrescaler() function - - (#) Configure the IWDG counter value using IWDG_SetReload() function. - This value will be loaded in the IWDG counter each time the counter - is reloaded, then the IWDG will start counting down from this value. - - (#) Start the IWDG using IWDG_Enable() function, when the IWDG is used - in software mode (no need to enable the LSI, it will be enabled - by hardware) - - (#) Then the application program must reload the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - IWDG_ReloadCounter() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_iwdg.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup IWDG - * @brief IWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* KR register bit mask */ -#define KR_KEY_RELOAD ((uint16_t)0xAAAA) -#define KR_KEY_ENABLE ((uint16_t)0xCCCC) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup IWDG_Private_Functions - * @{ - */ - -/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions - * @brief Prescaler and Counter configuration functions - * -@verbatim - =============================================================================== - ##### Prescaler and Counter configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. - * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. - * This parameter can be one of the following values: - * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers - * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers - * @retval None - */ -void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) -{ - /* Check the parameters */ - assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); - IWDG->KR = IWDG_WriteAccess; -} - -/** - * @brief Sets IWDG Prescaler value. - * @param IWDG_Prescaler: specifies the IWDG Prescaler value. - * This parameter can be one of the following values: - * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 - * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 - * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 - * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 - * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 - * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 - * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 - * @retval None - */ -void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); - IWDG->PR = IWDG_Prescaler; -} - -/** - * @brief Sets IWDG Reload value. - * @param Reload: specifies the IWDG Reload value. - * This parameter must be a number between 0 and 0x0FFF. - * @retval None - */ -void IWDG_SetReload(uint16_t Reload) -{ - /* Check the parameters */ - assert_param(IS_IWDG_RELOAD(Reload)); - IWDG->RLR = Reload; -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_ReloadCounter(void) -{ - IWDG->KR = KR_KEY_RELOAD; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group2 IWDG activation function - * @brief IWDG activation function - * -@verbatim - =============================================================================== - ##### IWDG activation function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param None - * @retval None - */ -void IWDG_Enable(void) -{ - IWDG->KR = KR_KEY_ENABLE; -} - -/** - * @} - */ - -/** @defgroup IWDG_Group3 Flag management function - * @brief Flag management function - * -@verbatim - =============================================================================== - ##### Flag management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified IWDG flag is set or not. - * @param IWDG_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg IWDG_FLAG_PVU: Prescaler Value Update on going - * @arg IWDG_FLAG_RVU: Reload Value Update on going - * @retval The new state of IWDG_FLAG (SET or RESET). - */ -FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_IWDG_FLAG(IWDG_FLAG)); - if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c deleted file mode 100644 index 490860450..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c +++ /dev/null @@ -1,1110 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_ltdc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the LTDC controller (LTDC) peripheral: - * + Initialization and configuration - * + Interrupts and flags management - * - * @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable LTDC clock using - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE) function. - (#) Configures LTDC - (++) Configure the required Pixel clock following the panel datasheet - (++) Configure the Synchronous timings: VSYNC, HSYNC, Vertical and - Horizontal back proch, active data area and the front proch - timings - (++) Configure the synchronous signals and clock polarity in the - LTDC_GCR register - (#) Configures Layer1/2 parameters - (++) The Layer window horizontal and vertical position in the LTDC_LxWHPCR and - LTDC_WVPCR registers. The layer window must be in the active data area. - (++) The pixel input format in the LTDC_LxPFCR register - (++) The color frame buffer start address in the LTDC_LxCFBAR register - (++) The line length and pitch of the color frame buffer in the - LTDC_LxCFBLR register - (++) The number of lines of the color frame buffer in - the LTDC_LxCFBLNR register - (++) if needed, load the CLUT with the RGB values and the address - in the LTDC_LxCLUTWR register - (++) If needed, configure the default color and the blending factors - respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers - - (++) If needed, Dithering and color keying can be enabled respectively - in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled - on the fly. - (#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register - - (#) Reload the shadow registers to active register through - the LTDC_SRCR register. - -@- All layer parameters can be modified on the fly except the CLUT. - The new configuration has to be either reloaded immediately - or during vertical blanking period by configuring the LTDC_SRCR register. - (#) Call the LTDC_Cmd() to enable the LTDC controller. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_ltdc.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup LTDC - * @brief LTDC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#define GCR_MASK ((uint32_t)0x0FFE888F) /* LTDC GCR Mask */ - - -/** @defgroup LTDC_Private_Functions - * @{ - */ - -/** @defgroup LTDC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - (+) Enable or Disable Dither - (+) Define the position of the line interrupt - (+) reload layers registers with new parameters - (+) Initialize and configure layer1 and layer2 - (+) Set and configure the color keying functionality - (+) Configure and Enables or disables CLUT - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the LTDC peripheral registers to their default reset - * values. - * @param None - * @retval None - */ - -void LTDC_DeInit(void) -{ - /* Enable LTDC reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, ENABLE); - /* Release LTDC from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_LTDC, DISABLE); -} - -/** - * @brief Initializes the LTDC peripheral according to the specified parameters - * in the LTDC_InitStruct. - * @note This function can be used only when the LTDC is disabled. - * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure that contains - * the configuration information for the specified LTDC peripheral. - * @retval None - */ - -void LTDC_Init(LTDC_InitTypeDef* LTDC_InitStruct) -{ - uint32_t horizontalsync = 0; - uint32_t accumulatedHBP = 0; - uint32_t accumulatedactiveW = 0; - uint32_t totalwidth = 0; - uint32_t backgreen = 0; - uint32_t backred = 0; - - /* Check function parameters */ - assert_param(IS_LTDC_HSYNC(LTDC_InitStruct->LTDC_HorizontalSync)); - assert_param(IS_LTDC_VSYNC(LTDC_InitStruct->LTDC_VerticalSync)); - assert_param(IS_LTDC_AHBP(LTDC_InitStruct->LTDC_AccumulatedHBP)); - assert_param(IS_LTDC_AVBP(LTDC_InitStruct->LTDC_AccumulatedVBP)); - assert_param(IS_LTDC_AAH(LTDC_InitStruct->LTDC_AccumulatedActiveH)); - assert_param(IS_LTDC_AAW(LTDC_InitStruct->LTDC_AccumulatedActiveW)); - assert_param(IS_LTDC_TOTALH(LTDC_InitStruct->LTDC_TotalHeigh)); - assert_param(IS_LTDC_TOTALW(LTDC_InitStruct->LTDC_TotalWidth)); - assert_param(IS_LTDC_HSPOL(LTDC_InitStruct->LTDC_HSPolarity)); - assert_param(IS_LTDC_VSPOL(LTDC_InitStruct->LTDC_VSPolarity)); - assert_param(IS_LTDC_DEPOL(LTDC_InitStruct->LTDC_DEPolarity)); - assert_param(IS_LTDC_PCPOL(LTDC_InitStruct->LTDC_PCPolarity)); - assert_param(IS_LTDC_BackBlueValue(LTDC_InitStruct->LTDC_BackgroundBlueValue)); - assert_param(IS_LTDC_BackGreenValue(LTDC_InitStruct->LTDC_BackgroundGreenValue)); - assert_param(IS_LTDC_BackRedValue(LTDC_InitStruct->LTDC_BackgroundRedValue)); - - /* Sets Synchronization size */ - LTDC->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - horizontalsync = (LTDC_InitStruct->LTDC_HorizontalSync << 16); - LTDC->SSCR |= (horizontalsync | LTDC_InitStruct->LTDC_VerticalSync); - - /* Sets Accumulated Back porch */ - LTDC->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - accumulatedHBP = (LTDC_InitStruct->LTDC_AccumulatedHBP << 16); - LTDC->BPCR |= (accumulatedHBP | LTDC_InitStruct->LTDC_AccumulatedVBP); - - /* Sets Accumulated Active Width */ - LTDC->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - accumulatedactiveW = (LTDC_InitStruct->LTDC_AccumulatedActiveW << 16); - LTDC->AWCR |= (accumulatedactiveW | LTDC_InitStruct->LTDC_AccumulatedActiveH); - - /* Sets Total Width */ - LTDC->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - totalwidth = (LTDC_InitStruct->LTDC_TotalWidth << 16); - LTDC->TWCR |= (totalwidth | LTDC_InitStruct->LTDC_TotalHeigh); - - LTDC->GCR &= (uint32_t)GCR_MASK; - LTDC->GCR |= (uint32_t)(LTDC_InitStruct->LTDC_HSPolarity | LTDC_InitStruct->LTDC_VSPolarity | \ - LTDC_InitStruct->LTDC_DEPolarity | LTDC_InitStruct->LTDC_PCPolarity); - - /* sets the background color value */ - backgreen = (LTDC_InitStruct->LTDC_BackgroundGreenValue << 8); - backred = (LTDC_InitStruct->LTDC_BackgroundRedValue << 16); - - LTDC->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); - LTDC->BCCR |= (backred | backgreen | LTDC_InitStruct->LTDC_BackgroundBlueValue); -} - -/** - * @brief Fills each LTDC_InitStruct member with its default value. - * @param LTDC_InitStruct: pointer to a LTDC_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_StructInit(LTDC_InitTypeDef* LTDC_InitStruct) -{ - /*--------------- Reset LTDC init structure parameters values ----------------*/ - LTDC_InitStruct->LTDC_HSPolarity = LTDC_HSPolarity_AL; /*!< Initialize the LTDC_HSPolarity member */ - LTDC_InitStruct->LTDC_VSPolarity = LTDC_VSPolarity_AL; /*!< Initialize the LTDC_VSPolarity member */ - LTDC_InitStruct->LTDC_DEPolarity = LTDC_DEPolarity_AL; /*!< Initialize the LTDC_DEPolarity member */ - LTDC_InitStruct->LTDC_PCPolarity = LTDC_PCPolarity_IPC; /*!< Initialize the LTDC_PCPolarity member */ - LTDC_InitStruct->LTDC_HorizontalSync = 0x00; /*!< Initialize the LTDC_HorizontalSync member */ - LTDC_InitStruct->LTDC_VerticalSync = 0x00; /*!< Initialize the LTDC_VerticalSync member */ - LTDC_InitStruct->LTDC_AccumulatedHBP = 0x00; /*!< Initialize the LTDC_AccumulatedHBP member */ - LTDC_InitStruct->LTDC_AccumulatedVBP = 0x00; /*!< Initialize the LTDC_AccumulatedVBP member */ - LTDC_InitStruct->LTDC_AccumulatedActiveW = 0x00; /*!< Initialize the LTDC_AccumulatedActiveW member */ - LTDC_InitStruct->LTDC_AccumulatedActiveH = 0x00; /*!< Initialize the LTDC_AccumulatedActiveH member */ - LTDC_InitStruct->LTDC_TotalWidth = 0x00; /*!< Initialize the LTDC_TotalWidth member */ - LTDC_InitStruct->LTDC_TotalHeigh = 0x00; /*!< Initialize the LTDC_TotalHeigh member */ - LTDC_InitStruct->LTDC_BackgroundRedValue = 0x00; /*!< Initialize the LTDC_BackgroundRedValue member */ - LTDC_InitStruct->LTDC_BackgroundGreenValue = 0x00; /*!< Initialize the LTDC_BackgroundGreenValue member */ - LTDC_InitStruct->LTDC_BackgroundBlueValue = 0x00; /*!< Initialize the LTDC_BackgroundBlueValue member */ -} - -/** - * @brief Enables or disables the LTDC Controller. - * @param NewState: new state of the LTDC peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable LTDC by setting LTDCEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_LTDCEN; - } - else - { - /* Disable LTDC by clearing LTDCEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_LTDCEN; - } -} - -/** - * @brief Enables or disables Dither. - * @param NewState: new state of the Dither. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_DitherCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable Dither by setting DTEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN; - } - else - { - /* Disable Dither by clearing DTEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN; - } -} - -/** - * @brief Get the dither RGB width. - * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure that contains - * the Dither RGB width. - * @retval None - */ - -LTDC_RGBTypeDef LTDC_GetRGBWidth(void) -{ - LTDC_RGBTypeDef LTDC_RGB_InitStruct; - - LTDC->GCR &= (uint32_t)GCR_MASK; - - LTDC_RGB_InitStruct.LTDC_BlueWidth = (uint32_t)((LTDC->GCR >> 4) & 0x7); - LTDC_RGB_InitStruct.LTDC_GreenWidth = (uint32_t)((LTDC->GCR >> 8) & 0x7); - LTDC_RGB_InitStruct.LTDC_RedWidth = (uint32_t)((LTDC->GCR >> 12) & 0x7); - - return LTDC_RGB_InitStruct; -} - -/** - * @brief Fills each LTDC_RGBStruct member with its default value. - * @param LTDC_RGB_InitStruct: pointer to a LTDC_RGBTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_RGBStructInit(LTDC_RGBTypeDef* LTDC_RGB_InitStruct) -{ - LTDC_RGB_InitStruct->LTDC_BlueWidth = 0x02; - LTDC_RGB_InitStruct->LTDC_GreenWidth = 0x02; - LTDC_RGB_InitStruct->LTDC_RedWidth = 0x02; -} - - -/** - * @brief Define the position of the line interrupt . - * @param LTDC_LIPositionConfig: Line Interrupt Position. - * @retval None - */ - -void LTDC_LIPConfig(uint32_t LTDC_LIPositionConfig) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LIPOS(LTDC_LIPositionConfig)); - - /* Sets the Line Interrupt position */ - LTDC->LIPCR = (uint32_t)LTDC_LIPositionConfig; -} - -/** - * @brief reload layers registers with new parameters - * @param LTDC_Reload: specifies the type of reload. - * This parameter can be one of the following values: - * @arg LTDC_IMReload: Vertical blanking reload. - * @arg LTDC_VBReload: Immediate reload. - * @retval None - */ - -void LTDC_ReloadConfig(uint32_t LTDC_Reload) -{ - /* Check the parameters */ - assert_param(IS_LTDC_RELOAD(LTDC_Reload)); - - /* Sets the Reload type */ - LTDC->SRCR = (uint32_t)LTDC_Reload; -} - - -/** - * @brief Initializes the LTDC Layer according to the specified parameters - * in the LTDC_LayerStruct. - * @note This function can be used only when the LTDC is disabled. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @param LTDC_LayerStruct: pointer to a LTDC_LayerTypeDef structure that contains - * the configuration information for the specified LTDC peripheral. - * @retval None - */ - -void LTDC_LayerInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_Layer_InitTypeDef* LTDC_Layer_InitStruct) -{ - - uint32_t whsppos = 0; - uint32_t wvsppos = 0; - uint32_t dcgreen = 0; - uint32_t dcred = 0; - uint32_t dcalpha = 0; - uint32_t cfbp = 0; - -/* Check the parameters */ - assert_param(IS_LTDC_Pixelformat(LTDC_Layer_InitStruct->LTDC_PixelFormat)); - assert_param(IS_LTDC_BlendingFactor1(LTDC_Layer_InitStruct->LTDC_BlendingFactor_1)); - assert_param(IS_LTDC_BlendingFactor2(LTDC_Layer_InitStruct->LTDC_BlendingFactor_2)); - assert_param(IS_LTDC_HCONFIGST(LTDC_Layer_InitStruct->LTDC_HorizontalStart)); - assert_param(IS_LTDC_HCONFIGSP(LTDC_Layer_InitStruct->LTDC_HorizontalStop)); - assert_param(IS_LTDC_VCONFIGST(LTDC_Layer_InitStruct->LTDC_VerticalStart)); - assert_param(IS_LTDC_VCONFIGSP(LTDC_Layer_InitStruct->LTDC_VerticalStop)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorBlue)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorGreen)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorRed)); - assert_param(IS_LTDC_DEFAULTCOLOR(LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha)); - assert_param(IS_LTDC_CFBP(LTDC_Layer_InitStruct->LTDC_CFBPitch)); - assert_param(IS_LTDC_CFBLL(LTDC_Layer_InitStruct->LTDC_CFBLineLength)); - assert_param(IS_LTDC_CFBLNBR(LTDC_Layer_InitStruct->LTDC_CFBLineNumber)); - - /* Configures the horizontal start and stop position */ - whsppos = LTDC_Layer_InitStruct->LTDC_HorizontalStop << 16; - LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_Layerx->WHPCR = (LTDC_Layer_InitStruct->LTDC_HorizontalStart | whsppos); - - /* Configures the vertical start and stop position */ - wvsppos = LTDC_Layer_InitStruct->LTDC_VerticalStop << 16; - LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_Layerx->WVPCR = (LTDC_Layer_InitStruct->LTDC_VerticalStart | wvsppos); - - /* Specifies the pixel format */ - LTDC_Layerx->PFCR &= ~(LTDC_LxPFCR_PF); - LTDC_Layerx->PFCR = (LTDC_Layer_InitStruct->LTDC_PixelFormat); - - /* Configures the default color values */ - dcgreen = (LTDC_Layer_InitStruct->LTDC_DefaultColorGreen << 8); - dcred = (LTDC_Layer_InitStruct->LTDC_DefaultColorRed << 16); - dcalpha = (LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha << 24); - LTDC_Layerx->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); - LTDC_Layerx->DCCR = (LTDC_Layer_InitStruct->LTDC_DefaultColorBlue | dcgreen | \ - dcred | dcalpha); - - /* Specifies the constant alpha value */ - LTDC_Layerx->CACR &= ~(LTDC_LxCACR_CONSTA); - LTDC_Layerx->CACR = (LTDC_Layer_InitStruct->LTDC_ConstantAlpha); - - /* Specifies the blending factors */ - LTDC_Layerx->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); - LTDC_Layerx->BFCR = (LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 | LTDC_Layer_InitStruct->LTDC_BlendingFactor_2); - - /* Configures the color frame buffer start address */ - LTDC_Layerx->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_Layerx->CFBAR = (LTDC_Layer_InitStruct->LTDC_CFBStartAdress); - - /* Configures the color frame buffer pitch in byte */ - cfbp = (LTDC_Layer_InitStruct->LTDC_CFBPitch << 16); - LTDC_Layerx->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_Layerx->CFBLR = (LTDC_Layer_InitStruct->LTDC_CFBLineLength | cfbp); - - /* Configures the frame buffer line number */ - LTDC_Layerx->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); - LTDC_Layerx->CFBLNR = (LTDC_Layer_InitStruct->LTDC_CFBLineNumber); - -} - -/** - * @brief Fills each LTDC_Layer_InitStruct member with its default value. - * @param LTDC_Layer_InitStruct: pointer to a LTDC_LayerTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_LayerStructInit(LTDC_Layer_InitTypeDef * LTDC_Layer_InitStruct) -{ - /*--------------- Reset Layer structure parameters values -------------------*/ - - /*!< Initialize the horizontal limit member */ - LTDC_Layer_InitStruct->LTDC_HorizontalStart = 0x00; - LTDC_Layer_InitStruct->LTDC_HorizontalStop = 0x00; - - /*!< Initialize the vertical limit member */ - LTDC_Layer_InitStruct->LTDC_VerticalStart = 0x00; - LTDC_Layer_InitStruct->LTDC_VerticalStop = 0x00; - - /*!< Initialize the pixel format member */ - LTDC_Layer_InitStruct->LTDC_PixelFormat = LTDC_Pixelformat_ARGB8888; - - /*!< Initialize the constant alpha value */ - LTDC_Layer_InitStruct->LTDC_ConstantAlpha = 0xFF; - - /*!< Initialize the default color values */ - LTDC_Layer_InitStruct->LTDC_DefaultColorBlue = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorGreen = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorRed = 0x00; - LTDC_Layer_InitStruct->LTDC_DefaultColorAlpha = 0x00; - - /*!< Initialize the blending factors */ - LTDC_Layer_InitStruct->LTDC_BlendingFactor_1 = LTDC_BlendingFactor1_PAxCA; - LTDC_Layer_InitStruct->LTDC_BlendingFactor_2 = LTDC_BlendingFactor2_PAxCA; - - /*!< Initialize the frame buffer start address */ - LTDC_Layer_InitStruct->LTDC_CFBStartAdress = 0x00; - - /*!< Initialize the frame buffer pitch and line length */ - LTDC_Layer_InitStruct->LTDC_CFBLineLength = 0x00; - LTDC_Layer_InitStruct->LTDC_CFBPitch = 0x00; - - /*!< Initialize the frame buffer line number */ - LTDC_Layer_InitStruct->LTDC_CFBLineNumber = 0x00; -} - - -/** - * @brief Enables or disables the LTDC_Layer Controller. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @param NewState: new state of the LTDC_Layer peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_LayerCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable LTDC_Layer by setting LEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_LEN; - } - else - { - /* Disable LTDC_Layer by clearing LEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_LEN; - } -} - - -/** - * @brief Get the current position. - * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure that contains - * the current position. - * @retval None - */ - -LTDC_PosTypeDef LTDC_GetPosStatus(void) -{ - LTDC_PosTypeDef LTDC_Pos_InitStruct; - - LTDC->CPSR &= ~(LTDC_CPSR_CYPOS | LTDC_CPSR_CXPOS); - - LTDC_Pos_InitStruct.LTDC_POSX = (uint32_t)(LTDC->CPSR >> 16); - LTDC_Pos_InitStruct.LTDC_POSY = (uint32_t)(LTDC->CPSR & 0xFFFF); - - return LTDC_Pos_InitStruct; -} - -/** - * @brief Fills each LTDC_Pos_InitStruct member with its default value. - * @param LTDC_Pos_InitStruct: pointer to a LTDC_PosTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_PosStructInit(LTDC_PosTypeDef* LTDC_Pos_InitStruct) -{ - LTDC_Pos_InitStruct->LTDC_POSX = 0x00; - LTDC_Pos_InitStruct->LTDC_POSY = 0x00; -} - -/** - * @brief Checks whether the specified LTDC's flag is set or not. - * @param LTDC_CD: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LTDC_CD_VDES: vertical data enable current status. - * @arg LTDC_CD_HDES: horizontal data enable current status. - * @arg LTDC_CD_VSYNC: Vertical Synchronization current status. - * @arg LTDC_CD_HSYNC: Horizontal Synchronization current status. - * @retval The new state of LTDC_CD (SET or RESET). - */ - -FlagStatus LTDC_GetCDStatus(uint32_t LTDC_CD) -{ - FlagStatus bitstatus; - - /* Check the parameters */ - assert_param(IS_LTDC_GET_CD(LTDC_CD)); - - if ((LTDC->CDSR & LTDC_CD) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Set and configure the color keying. - * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef - * structure that contains the color keying configuration. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval None - */ - -void LTDC_ColorKeyingConfig(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct, FunctionalState NewState) -{ - uint32_t ckgreen = 0; - uint32_t ckred = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen)); - assert_param(IS_LTDC_CKEYING(LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed)); - - if (NewState != DISABLE) - { - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Sets the color keying values */ - ckgreen = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen << 8); - ckred = (LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed << 16); - LTDC_Layerx->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_Layerx->CKCR |= (LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue | ckgreen | ckred); - } - else - { - /* Disable LTDC color keying by clearing COLKEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - } - - /* Reload shadow register */ - LTDC->SRCR = LTDC_IMReload; -} - -/** - * @brief Fills each LTDC_colorkeying_InitStruct member with its default value. - * @param LTDC_colorkeying_InitStruct: pointer to a LTDC_ColorKeying_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_ColorKeyingStructInit(LTDC_ColorKeying_InitTypeDef* LTDC_colorkeying_InitStruct) -{ - /*!< Initialize the color keying values */ - LTDC_colorkeying_InitStruct->LTDC_ColorKeyBlue = 0x00; - LTDC_colorkeying_InitStruct->LTDC_ColorKeyGreen = 0x00; - LTDC_colorkeying_InitStruct->LTDC_ColorKeyRed = 0x00; -} - - -/** - * @brief Enables or disables CLUT. - * @param NewState: new state of CLUT. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ - -void LTDC_CLUTCmd(LTDC_Layer_TypeDef* LTDC_Layerx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable CLUT by setting CLUTEN bit */ - LTDC_Layerx->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - } - else - { - /* Disable CLUT by clearing CLUTEN bit */ - LTDC_Layerx->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - } - - /* Reload shadow register */ - LTDC->SRCR = LTDC_IMReload; -} - -/** - * @brief configure the CLUT. - * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure that contains - * the CLUT configuration. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval None - */ - -void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) -{ - uint32_t green = 0; - uint32_t red = 0; - uint32_t clutadd = 0; - - /* Check the parameters */ - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_CLUTAdress)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_RedValue)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_GreenValue)); - assert_param(IS_LTDC_CLUTWR(LTDC_CLUT_InitStruct->LTDC_BlueValue)); - - /* Specifies the CLUT address and RGB value */ - green = (LTDC_CLUT_InitStruct->LTDC_GreenValue << 8); - red = (LTDC_CLUT_InitStruct->LTDC_RedValue << 16); - clutadd = (LTDC_CLUT_InitStruct->LTDC_CLUTAdress << 24); - LTDC_Layerx->CLUTWR = (clutadd | LTDC_CLUT_InitStruct->LTDC_BlueValue | \ - green | red); -} - -/** - * @brief Fills each LTDC_CLUT_InitStruct member with its default value. - * @param LTDC_CLUT_InitStruct: pointer to a LTDC_CLUT_InitTypeDef structure which will - * be initialized. - * @retval None - */ - -void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct) -{ - /*!< Initialize the CLUT address and RGB values */ - LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00; - LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00; - LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00; - LTDC_CLUT_InitStruct->LTDC_RedValue = 0x00; -} - - -/** - * @brief reconfigure the layer position. - * @param OffsetX: horizontal offset from start active width . - * @param OffsetY: vertical offset from start active height. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * position reconfiguration. - */ - -void LTDC_LayerPosition(LTDC_Layer_TypeDef* LTDC_Layerx, uint16_t OffsetX, uint16_t OffsetY) -{ - - uint32_t tempreg, temp; - uint32_t horizontal_start; - uint32_t horizontal_stop; - uint32_t vertical_start; - uint32_t vertical_stop; - - LTDC_Layerx->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_Layerx->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - - /* Reconfigures the horizontal and vertical start position */ - tempreg = LTDC->BPCR; - horizontal_start = (tempreg >> 16) + 1 + OffsetX; - vertical_start = (tempreg & 0xFFFF) + 1 + OffsetY; - - /* Reconfigures the horizontal and vertical stop position */ - /* Get the number of byte per pixel */ - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || - (tempreg == LTDC_Pixelformat_RGB565) || - (tempreg == LTDC_Pixelformat_ARGB1555) || - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - tempreg = LTDC_Layerx->CFBLR; - horizontal_stop = (((tempreg & 0x1FFF) - 3)/temp) + horizontal_start - 1; - - tempreg = LTDC_Layerx->CFBLNR; - vertical_stop = (tempreg & 0x7FF) + vertical_start - 1; - - LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); - LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); -} - -/** - * @brief reconfigure constant alpha. - * @param ConstantAlpha: constant alpha value. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after constant - * alpha reconfiguration. - */ - -void LTDC_LayerAlpha(LTDC_Layer_TypeDef* LTDC_Layerx, uint8_t ConstantAlpha) -{ - /* reconfigure the constant alpha value */ - LTDC_Layerx->CACR = ConstantAlpha; -} - -/** - * @brief reconfigure layer address. - * @param Address: The color frame buffer start address. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * address reconfiguration. - */ - -void LTDC_LayerAddress(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Address) -{ - /* Reconfigures the color frame buffer start address */ - LTDC_Layerx->CFBAR = Address; -} - -/** - * @brief reconfigure layer size. - * @param Width: layer window width. - * @param Height: layer window height. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * size reconfiguration. - */ - -void LTDC_LayerSize(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t Width, uint32_t Height) -{ - - uint8_t temp; - uint32_t tempreg; - uint32_t horizontal_start; - uint32_t horizontal_stop; - uint32_t vertical_start; - uint32_t vertical_stop; - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ - (tempreg == LTDC_Pixelformat_RGB565) || \ - (tempreg == LTDC_Pixelformat_ARGB1555) || \ - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - /* update horizontal and vertical stop */ - tempreg = LTDC_Layerx->WHPCR; - horizontal_start = (tempreg & 0x1FFF); - horizontal_stop = Width + horizontal_start - 1; - - tempreg = LTDC_Layerx->WVPCR; - vertical_start = (tempreg & 0x1FFF); - vertical_stop = Height + vertical_start - 1; - - LTDC_Layerx->WHPCR = horizontal_start | (horizontal_stop << 16); - LTDC_Layerx->WVPCR = vertical_start | (vertical_stop << 16); - - /* Reconfigures the color frame buffer pitch in byte */ - LTDC_Layerx->CFBLR = ((Width * temp) << 16) | ((Width * temp) + 3); - - /* Reconfigures the frame buffer line number */ - LTDC_Layerx->CFBLNR = Height; - -} - -/** - * @brief reconfigure layer pixel format. - * @param PixelFormat: reconfigure the pixel format, this parameter can be - * one of the following values:@ref LTDC_Pixelformat. - * @param LTDC_layerx: Select the layer to be configured, this parameter can be - * one of the following values: LTDC_Layer1, LTDC_Layer2 - * @retval Reload of the shadow registers values must be applied after layer - * pixel format reconfiguration. - */ - -void LTDC_LayerPixelFormat(LTDC_Layer_TypeDef* LTDC_Layerx, uint32_t PixelFormat) -{ - - uint8_t temp; - uint32_t tempreg; - - tempreg = LTDC_Layerx->PFCR; - - if (tempreg == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (tempreg == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((tempreg == LTDC_Pixelformat_ARGB4444) || \ - (tempreg == LTDC_Pixelformat_RGB565) || \ - (tempreg == LTDC_Pixelformat_ARGB1555) || \ - (tempreg == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - tempreg = (LTDC_Layerx->CFBLR >> 16); - tempreg = (tempreg / temp); - - if (PixelFormat == LTDC_Pixelformat_ARGB8888) - { - temp = 4; - } - else if (PixelFormat == LTDC_Pixelformat_RGB888) - { - temp = 3; - } - else if ((PixelFormat == LTDC_Pixelformat_ARGB4444) || \ - (PixelFormat == LTDC_Pixelformat_RGB565) || \ - (PixelFormat == LTDC_Pixelformat_ARGB1555) || \ - (PixelFormat == LTDC_Pixelformat_AL88)) - { - temp = 2; - } - else - { - temp = 1; - } - - /* Reconfigures the color frame buffer pitch in byte */ - LTDC_Layerx->CFBLR = ((tempreg * temp) << 16) | ((tempreg * temp) + 3); - - /* Reconfigures the color frame buffer start address */ - LTDC_Layerx->PFCR = PixelFormat; - -} - -/** - * @} - */ - -/** @defgroup LTDC_Group2 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the LTDC Interrupts - and to get the status and clear flags and Interrupts pending bits. - - [..] The LTDC provides 4 Interrupts sources and 4 Flags - - *** Flags *** - ============= - [..] - (+) LTDC_FLAG_LI: Line Interrupt flag. - (+) LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - (+) LTDC_FLAG_TERR: Transfer Error Interrupt flag. - (+) LTDC_FLAG_RR: Register Reload interrupt flag. - - *** Interrupts *** - ================== - [..] - (+) LTDC_IT_LI: Line Interrupt is generated when a programmed line - is reached. The line interrupt position is programmed in - the LTDC_LIPR register. - (+) LTDC_IT_FU: FIFO Underrun interrupt is generated when a pixel is requested - from an empty layer FIFO - (+) LTDC_IT_TERR: Transfer Error interrupt is generated when an AHB bus - error occurs during data transfer. - (+) LTDC_IT_RR: Register Reload interrupt is generated when the shadow - registers reload was performed during the vertical blanking - period. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified LTDC's interrupts. - * @param LTDC_IT: specifies the LTDC interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt Enable. - * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. - * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. - * @arg LTDC_IT_RR: Register Reload interrupt enable. - * @param NewState: new state of the specified LTDC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void LTDC_ITConfig(uint32_t LTDC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - LTDC->IER |= LTDC_IT; - } - else - { - LTDC->IER &= (uint32_t)~LTDC_IT; - } -} - -/** - * @brief Checks whether the specified LTDC's flag is set or not. - * @param LTDC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag. - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. - * @arg LTDC_FLAG_RR: Register Reload interrupt flag. - * @retval The new state of LTDC_FLAG (SET or RESET). - */ -FlagStatus LTDC_GetFlagStatus(uint32_t LTDC_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LTDC_FLAG(LTDC_FLAG)); - - if ((LTDC->ISR & LTDC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the LTDC's pending flags. - * @param LTDC_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag. - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag. - * @arg LTDC_FLAG_TERR: Transfer Error Interrupt flag. - * @arg LTDC_FLAG_RR: Register Reload interrupt flag. - * @retval None - */ -void LTDC_ClearFlag(uint32_t LTDC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_LTDC_FLAG(LTDC_FLAG)); - - /* Clear the corresponding LTDC flag */ - LTDC->ICR = (uint32_t)LTDC_FLAG; -} - -/** - * @brief Checks whether the specified LTDC's interrupt has occurred or not. - * @param LTDC_IT: specifies the LTDC interrupts sources to check. - * This parameter can be one of the following values: - * @arg LTDC_IT_LI: Line Interrupt Enable. - * @arg LTDC_IT_FU: FIFO Underrun Interrupt Enable. - * @arg LTDC_IT_TERR: Transfer Error Interrupt Enable. - * @arg LTDC_IT_RR: Register Reload interrupt Enable. - * @retval The new state of the LTDC_IT (SET or RESET). - */ -ITStatus LTDC_GetITStatus(uint32_t LTDC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - - if ((LTDC->ISR & LTDC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - if (((LTDC->IER & LTDC_IT) != (uint32_t)RESET) && (bitstatus != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - - -/** - * @brief Clears the LTDC's interrupt pending bits. - * @param LTDC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LIE: Line Interrupt. - * @arg LTDC_IT_FUIE: FIFO Underrun Interrupt. - * @arg LTDC_IT_TERRIE: Transfer Error Interrupt. - * @arg LTDC_IT_RRIE: Register Reload interrupt. - * @retval None - */ -void LTDC_ClearITPendingBit(uint32_t LTDC_IT) -{ - /* Check the parameters */ - assert_param(IS_LTDC_IT(LTDC_IT)); - - /* Clear the corresponding LTDC Interrupt */ - LTDC->ICR = (uint32_t)LTDC_IT; -} -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c deleted file mode 100644 index 8201cb10d..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c +++ /dev/null @@ -1,1053 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_pwr.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Backup Domain Access - * + PVD configuration - * + WakeUp pin configuration - * + Main and Backup Regulators configuration - * + FLASH Power Down configuration - * + Low Power modes configuration - * + Flags management - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_pwr.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup PWR - * @brief PWR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* --------- PWR registers bit address in the alias region ---------- */ -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) - -/* --- CR Register ---*/ - -/* Alias word address of DBP bit */ -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) - -/* Alias word address of PVDE bit */ -#define PVDE_BitNumber 0x04 -#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) - -/* Alias word address of FPDS bit */ -#define FPDS_BitNumber 0x09 -#define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4)) - -/* Alias word address of PMODE bit */ -#define PMODE_BitNumber 0x0E -#define CR_PMODE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4)) - -/* Alias word address of ODEN bit */ -#define ODEN_BitNumber 0x10 -#define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4)) - -/* Alias word address of ODSWEN bit */ -#define ODSWEN_BitNumber 0x11 -#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4)) - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) -/* Alias word address of MRUDS bit */ -#define MRUDS_BitNumber 0x0B -#define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4)) - -/* Alias word address of LPUDS bit */ -#define LPUDS_BitNumber 0x0A -#define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4)) -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */ - -#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) -/* Alias word address of MRLVDS bit */ -#define MRLVDS_BitNumber 0x0B -#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4)) - -/* Alias word address of LPLVDS bit */ -#define LPLVDS_BitNumber 0x0A -#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4)) -#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */ - -/* --- CSR Register ---*/ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx) -/* Alias word address of EWUP bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP_BitNumber 0x08 -#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */ - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/* Alias word address of EWUP2 bit */ -#define CSR_OFFSET (PWR_OFFSET + 0x04) -#define EWUP1_BitNumber 0x08 -#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4)) -#define EWUP2_BitNumber 0x07 -#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4)) -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -#define EWUP3_BitNumber 0x06 -#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4)) -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/* Alias word address of BRE bit */ -#define BRE_BitNumber 0x09 -#define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4)) - -/* ------------------ PWR registers bit mask ------------------------ */ - -/* CR register bit mask */ -#define CR_DS_MASK ((uint32_t)0xFFFFF3FC) -#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) -#define CR_VOS_MASK ((uint32_t)0xFFFF3FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Private_Functions - * @{ - */ - -/** @defgroup PWR_Group1 Backup Domain Access function - * @brief Backup Domain Access function - * -@verbatim - =============================================================================== - ##### Backup Domain Access function ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the PWR peripheral registers to their default reset values. - * @param None - * @retval None - */ -void PWR_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); -} - -/** - * @brief Enables or disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param NewState: new state of the access to the backup domain. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupAccessCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group2 PVD configuration functions - * @brief PVD configuration functions - * -@verbatim - =============================================================================== - ##### PVD configuration functions ##### - =============================================================================== - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled through the EXTI registers. - (+) The PVD is stopped in Standby mode. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param PWR_PVDLevel: specifies the PVD detection level - * This parameter can be one of the following values: - * @arg PWR_PVDLevel_0 - * @arg PWR_PVDLevel_1 - * @arg PWR_PVDLevel_2 - * @arg PWR_PVDLevel_3 - * @arg PWR_PVDLevel_4 - * @arg PWR_PVDLevel_5 - * @arg PWR_PVDLevel_6 - * @arg PWR_PVDLevel_7 - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= CR_PLS_MASK; - - /* Set PLS[7:5] bits according to PWR_PVDLevel value */ - tmpreg |= PWR_PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Power Voltage Detector(PVD). - * @param NewState: new state of the PVD. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_PVDCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group3 WakeUp pin configuration functions - * @brief WakeUp pin configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp pin configuration functions ##### - =============================================================================== - [..] - (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is - forced in input pull down configuration and is active on rising edges. - (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. - (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 - (++) For STM32F410xx/STM32F412xG/STM32F413_423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 -@endverbatim - * @{ - */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; -} -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Enables or disables the WakeUp Pin functionality. - * @param PWR_WakeUpPinx: specifies the WakeUp Pin. - * This parameter can be one of the following values: - * @arg PWR_WakeUp_Pin1: WKUP1 pin is used for wakeup from Standby mode. - * @arg PWR_WakeUp_Pin2: WKUP2 pin is used for wakeup from Standby mode. - * @arg PWR_WakeUp_Pin3: WKUP3 pin is used for wakeup from Standby mode.(only for STM32F410xx, STM32F412xG and STM32F413_423xx Devices) - * @param NewState: new state of the WakeUp Pin functionality. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_PWR_WAKEUP_PIN(NewState)); - if(PWR_WakeUpPinx == PWR_WakeUp_Pin1) /* PWR_WakeUp_Pin1 */ - { - *(__IO uint32_t *) CSR_EWUP1_BB = (uint32_t)NewState; - } -#if defined(STM32F410xx)|| defined(STM32F412xG) || defined(STM32F413_423xx) - else if(PWR_WakeUpPinx == PWR_WakeUp_Pin3) /* PWR_WakeUp_Pin3 */ - { - *(__IO uint32_t *) CSR_EWUP3_BB = (uint32_t)NewState; - } -#endif /* STM32F410xx */ - else /* PWR_WakeUp_Pin2 */ - { - *(__IO uint32_t *) CSR_EWUP2_BB = (uint32_t)NewState; - } -} -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/** - * @} - */ - -/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions - * @brief Main and Backup Regulators configuration functions - * -@verbatim - =============================================================================== - ##### Main and Backup Regulators configuration functions ##### - =============================================================================== - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the PWR_BackupRegulatorCmd() function to - enable the low power backup regulator and use the PWR_GetFlagStatus - (PWR_FLAG_BRR) to check if it is ready or not. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by an tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the reference manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. - (+) For STM32F405xx/407xx and STM32F415xx/417xx Devices, the regulator can be - configured on the fly through PWR_MainRegulatorModeConfig() function which - configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - - (+) For STM32F42xxx/43xxx Devices, the regulator can be configured through - PWR_MainRegulatorModeConfig() function which configure VOS[1:0] bits in - PWR_CR register: - which configure VOS[1:0] bits in PWR_CR register: - (++) When VOS[1:0] = 11 (Regulator voltage output Scale 1 mode selected) - the System frequency can go up to 168 MHz. - (++) When VOS[1:0] = 10 (Regulator voltage output Scale 2 mode selected) - the System frequency can go up to 144 MHz. - (++) When VOS[1:0] = 01 (Regulator voltage output Scale 3 mode selected) - the System frequency can go up to 120 MHz. - - (+) For STM32F42xxx/43xxx Devices, the scale can be modified only when the PLL - is OFF and the HSI or HSE clock source is selected as system clock. - The new value programmed is active only when the PLL is ON. - When the PLL is OFF, the voltage scale 3 is automatically selected. - Refer to the datasheets for more details. - - (+) For STM32F42xxx/43xxx Devices, in Run mode: the main regulator has - 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through PWR_OverDriveCmd() function and - PWR_OverDriveSWCmd() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) For STM32F42xxx/43xxx Devices, in Stop mode: the main regulator or low power regulator - supplies a low power voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - This mode is enabled through PWR_UnderDriveCmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Backup Regulator. - * @param NewState: new state of the Backup Regulator. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_BackupRegulatorCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the main internal regulator output voltage. - * @param PWR_Regulator_Voltage: specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_Regulator_Voltage_Scale1: Regulator voltage output Scale 1 mode, - * System frequency up to 168 MHz. - * @arg PWR_Regulator_Voltage_Scale2: Regulator voltage output Scale 2 mode, - * System frequency up to 144 MHz. - * @arg PWR_Regulator_Voltage_Scale3: Regulator voltage output Scale 3 mode, - * System frequency up to 120 MHz (only for STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_VOLTAGE(PWR_Regulator_Voltage)); - - tmpreg = PWR->CR; - - /* Clear VOS[15:14] bits */ - tmpreg &= CR_VOS_MASK; - - /* Set VOS[15:14] bits according to PWR_Regulator_Voltage value */ - tmpreg |= PWR_Regulator_Voltage; - - /* Store the new value */ - PWR->CR = tmpreg; -} - -/** - * @brief Enables or disables the Over-Drive. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * - * @param NewState: new state of the Over Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODEN bit to enable/disable the Over Drive mode */ - *(__IO uint32_t *) CR_ODEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Over-Drive switching. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * - * @param NewState: new state of the Over Drive switching mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_OverDriveSWCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Set/Reset the ODSWEN bit to enable/disable the Over Drive switching mode */ - *(__IO uint32_t *) CR_ODSWEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Under-Drive mode. - * - * @note This function can be used only for STM32F42xxx/STM3243xxx devices. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @param NewState: new state of the Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_UnderDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the UDEN[1:0] bits to enable the Under Drive mode */ - PWR->CR |= (uint32_t)PWR_CR_UDEN; - } - else - { - /* Reset the UDEN[1:0] bits to disable the Under Drive mode */ - PWR->CR &= (uint32_t)(~PWR_CR_UDEN); - } -} - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) -/** - * @brief Enables or disables the Main Regulator under drive mode. - * - * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices. - * - * @param NewState: new state of the Main Regulator Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)DISABLE; - } -} - -/** - * @brief Enables or disables the Low Power Regulator under drive mode. - * - * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices. - * - * @param NewState: new state of the Low Power Regulator Under Drive mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)DISABLE; - } -} -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */ - -#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) -/** - * @brief Enables or disables the Main Regulator low voltage mode. - * - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices. - * - * @param NewState: new state of the Main Regulator Low Voltage mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; - } -} - -/** - * @brief Enables or disables the Low Power Regulator low voltage mode. - * - * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices. - * - * @param NewState: new state of the Low Power Regulator Low Voltage mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; - } - else - { - *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; - } -} -#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */ - -/** - * @} - */ - -/** @defgroup PWR_Group5 FLASH Power Down configuration functions - * @brief FLASH Power Down configuration functions - * -@verbatim - =============================================================================== - ##### FLASH Power Down configuration functions ##### - =============================================================================== - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - PWR_FlashPowerDownCmd() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the Flash Power Down in STOP mode. - * @param NewState: new state of the Flash power mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void PWR_FlashPowerDownCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup PWR_Group6 Low Power modes configuration functions - * @brief Low Power modes configuration functions - * -@verbatim - =============================================================================== - ##### Low Power modes configuration functions ##### - =============================================================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - (++) The Sleep mode is entered by using the __WFI() or __WFE() functions. - (+) Exit: - (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode. It can be switched on again by software after exiting - the Stop mode using the PWR_FlashPowerDownCmd() function. - - (+) Entry: - (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_MainRegulator_ON) - function with: - (+++) Main regulator ON. - (+++) Low Power regulator ON. - (+) Exit: - (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (+) Entry: - (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function. - (+) Exit: - (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, - tamper event, time-stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event, a time-stamp event, or a comparator event, - without depending on an external interrupt (Auto-wakeup mode). - - (#) RTC auto-wakeup (AWU) from the Stop mode - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to: - (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to: - (+++) Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt - or Event modes) using the EXTI_Init() function. - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - - (#) RTC auto-wakeup (AWU) from the Standby mode - - (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to: - (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() - and RTC_AlarmCmd() functions. - (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it - is necessary to: - (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() - function - (+++) Configure the RTC to detect the tamper or time stamp event using the - RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd() - functions. - (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to: - (+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function - (+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), - RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enters STOP mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_ON: STOP mode with regulator ON - * @arg PWR_LowPowerRegulator_ON: STOP mode with low power regulator ON - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLVDS and LPLVDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode is only available for STM32F42xxx/STM3243xxx devices. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param PWR_Regulator: specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MainRegulator_UnderDrive_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LowPowerRegulator_UnderDrive_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction - * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction - * @retval None - */ -void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(PWR_Regulator)); - assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); - - /* Select the regulator state in STOP mode ---------------------------------*/ - tmpreg = PWR->CR; - /* Clear PDDS and LPDS bits */ - tmpreg &= CR_DS_MASK; - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tmpreg |= PWR_Regulator; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(PWR_STOPEntry == PWR_STOPEntry_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters STANDBY mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pin 1 (PA0) if enabled. - * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function - * @param None - * @retval None - */ -void PWR_EnterSTANDBYMode(void) -{ - /* Select STANDBY mode */ - PWR->CR |= PWR_CR_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM ) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @} - */ - -/** @defgroup PWR_Group7 Flags management functions - * @brief Flags management functions - * -@verbatim - =============================================================================== - ##### Flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the specified PWR flag is set or not. - * @param PWR_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received from the WKUP pin or from the RTC alarm (Alarm A - * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup. - * An additional wakeup event is detected if the WKUP pin is enabled - * (by setting the EWUP bit) when the WKUP pin level is already high. - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the PWR_PVDCmd() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switching is ready (STM32F42xxx/43xxx devices) - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode (STM32F42xxx/43xxx devices) - * @retval The new state of PWR_FLAG (SET or RESET). - */ -FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); - - if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the PWR's pending flags. - * @param PWR_FLAG: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag - * @arg PWR_FLAG_SB: StandBy flag - * @arg PWR_FLAG_UDRDY: Under-drive ready flag (STM32F42xxx/43xxx devices) - * @retval None - */ -void PWR_ClearFlag(uint32_t PWR_FLAG) -{ - /* Check the parameters */ - assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); - -#if defined (STM32F427_437xx) || defined (STM32F429_439xx) - if (PWR_FLAG != PWR_FLAG_UDRDY) - { - PWR->CR |= PWR_FLAG << 2; - } - else - { - PWR->CSR |= PWR_FLAG_UDRDY; - } -#endif /* STM32F427_437xx || STM32F429_439xx */ - -#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) - PWR->CR |= PWR_FLAG << 2; -#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c deleted file mode 100644 index 823c1ba06..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c +++ /dev/null @@ -1,3192 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rcc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Reset and clock control (RCC) peripheral: - * + Internal/external clocks, PLL, CSS and MCO configuration - * + System, AHB and APB busses clocks configuration - * + Peripheral clocks configuration - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### RCC specific features ##### - =============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; - all peripherals mapped on these busses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RCC - * @brief RCC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) -/* --- CR Register ---*/ -/* Alias word address of HSION bit */ -#define CR_OFFSET (RCC_OFFSET + 0x00) -#define HSION_BitNumber 0x00 -#define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) -/* Alias word address of CSSON bit */ -#define CSSON_BitNumber 0x13 -#define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) -/* Alias word address of PLLON bit */ -#define PLLON_BitNumber 0x18 -#define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) -/* Alias word address of PLLI2SON bit */ -#define PLLI2SON_BitNumber 0x1A -#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) - -/* Alias word address of PLLSAION bit */ -#define PLLSAION_BitNumber 0x1C -#define CR_PLLSAION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLSAION_BitNumber * 4)) - -/* --- CFGR Register ---*/ -/* Alias word address of I2SSRC bit */ -#define CFGR_OFFSET (RCC_OFFSET + 0x08) -#define I2SSRC_BitNumber 0x17 -#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) - -/* --- BDCR Register ---*/ -/* Alias word address of RTCEN bit */ -#define BDCR_OFFSET (RCC_OFFSET + 0x70) -#define RTCEN_BitNumber 0x0F -#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) -/* Alias word address of BDRST bit */ -#define BDRST_BitNumber 0x10 -#define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) - -/* --- CSR Register ---*/ -/* Alias word address of LSION bit */ -#define CSR_OFFSET (RCC_OFFSET + 0x74) -#define LSION_BitNumber 0x00 -#define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) - -/* --- DCKCFGR Register ---*/ -/* Alias word address of TIMPRE bit */ -#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C) -#define TIMPRE_BitNumber 0x18 -#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4)) - -/* --- CFGR Register ---*/ -#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08) - #if defined(STM32F410xx) -/* Alias word address of MCO1EN bit */ -#define RCC_MCO1EN_BIT_NUMBER 0x8 -#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4)) - -/* Alias word address of MCO2EN bit */ -#define RCC_MCO2EN_BIT_NUMBER 0x9 -#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4)) -#endif /* STM32F410xx */ -/* ---------------------- RCC registers bit mask ------------------------ */ -/* CFGR register bit mask */ -#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) -#define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) - -/* RCC Flag Mask */ -#define FLAG_MASK ((uint8_t)0x1F) - -/* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) - -/* CIR register byte 2 (Bits[15:8]) base address */ -#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -/* BDCR register base address */ -#define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Private_Functions - * @{ - */ - -/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions - * @brief Internal and external clocks, PLL, CSS and MCO configuration functions - * -@verbatim - =================================================================================== - ##### Internal and external clocks, PLL, CSS and MCO configuration functions ##### - =================================================================================== - [..] - This section provide functions allowing to configure the internal/external clocks, - PLLs, CSS and MCO pins. - - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 168 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve - high-quality audio performance on the I2S interface or SAI interface in case - of STM32F429x/439x devices. - - (#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI - interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - - (#) CSS (Clock security system), once enable and if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - @endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL and PLLI2S OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @param None - * @retval None - */ -void RCC_DeInit(void) -{ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */ - RCC->CR &= (uint32_t)0xEAF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx) - /* Reset PLLI2SCFGR register */ - RCC->PLLI2SCFGR = 0x20003000; -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) - /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */ - RCC->PLLSAICFGR = 0x24003000; -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */ - RCC->DCKCFGR = 0x00000000; - -#if defined(STM32F410xx) || defined(STM32F413_423xx) - /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */ - RCC->DCKCFGR2 = 0x00000000; -#endif /* STM32F410xx || STM32F413_423xx */ -} - -/** - * @brief Configures the External High Speed oscillator (HSE). - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the Clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param RCC_HSE: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator - * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock - * @retval None - */ -void RCC_HSEConfig(uint8_t RCC_HSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_HSE)); - - /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF; - - /* Set the new HSE configuration -------------------------------------------*/ - *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE; -} - -/** - * @brief Waits for HSE start-up. - * @note This functions waits on HSERDY flag to be set and return SUCCESS if - * this flag is set, otherwise returns ERROR if the timeout is reached - * and this flag is not set. The timeout value is defined by the constant - * HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending - * on the HSE crystal used in your application. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: HSE oscillator is stable and ready to use - * - ERROR: HSE oscillator not yet ready - */ -ErrorStatus RCC_WaitForHSEStartUp(void) -{ - __IO uint32_t startupcounter = 0; - ErrorStatus status = ERROR; - FlagStatus hsestatus = RESET; - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); - startupcounter++; - } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET)); - - if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - return (status); -} - -/** - * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param HSICalibrationValue: specifies the calibration trimming value. - * This parameter must be a number between 0 and 0x1F. - * @retval None - */ -void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue)); - - tmpreg = RCC->CR; - - /* Clear HSITRIM[4:0] bits */ - tmpreg &= ~RCC_CR_HSITRIM; - - /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ - tmpreg |= (uint32_t)HSICalibrationValue << 3; - - /* Store the new value */ - RCC->CR = tmpreg; -} - -/** - * @brief Enables or disables the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @param NewState: new state of the HSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -void RCC_HSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState; -} - -/** - * @brief Configures the External Low Speed oscillator (LSE). - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param RCC_LSE: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator - * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock - * @retval None - */ -void RCC_LSEConfig(uint8_t RCC_LSE) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_LSE)); - - /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ - /* Reset LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Reset LSEBYP bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF; - - /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */ - switch (RCC_LSE) - { - case RCC_LSE_ON: - /* Set LSEON bit */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON; - break; - case RCC_LSE_Bypass: - /* Set LSEBYP and LSEON bits */ - *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; - break; - default: - break; - } -} - -/** - * @brief Enables or disables the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @param NewState: new state of the LSI. - * This parameter can be: ENABLE or DISABLE. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -void RCC_LSICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState; -} - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * - * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices - * This parameter must be a number between 2 and 7. - * - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(PLLR)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24) | (PLLR << 28); -} -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -/** - * @brief Configures the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param RCC_PLLSource: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * - * @param PLLM: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 0 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - * @param PLLN: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLP: specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on - * the System clock frequency. - * - * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks - * This parameter must be a number between 4 and 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * - * @retval None - */ -void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(PLLM)); - assert_param(IS_RCC_PLLN_VALUE(PLLN)); - assert_param(IS_RCC_PLLP_VALUE(PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(PLLQ)); - - RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) | - (PLLQ << 24); -} -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -/** - * @brief Enables or disables the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState; -} - -#if defined(STM32F40_41xxx) || defined(STM32F401xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F405xx/407xx, STM32F415xx/417xx - * or STM32F401xx devices. - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28); -} -#endif /* STM32F40_41xxx || STM32F401xx */ - -#if defined(STM32F411xE) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F411xE devices. - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLLI2S jitter. - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM; -} -#endif /* STM32F411xE */ - -#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLI2SQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28); -} -#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -#if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Configures the PLLI2S clock multiplication and division factors. - * - * @note This function can be used only for STM32F446xx devices - * - * @note This function must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLLI2S jitter. - * - * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output - * This parameter must be a number in the range {2, 4, 6, or 8}. - * - * @param PLLI2SQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLI2SR: specifies the division factor for I2S clock - * This parameter must be a number between 2 and 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices. - * - * @retval None - */ -void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM)); - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN)); - assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR)); - - RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28); -} -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - -/** - * @brief Enables or disables the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLI2SCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState; -} - -#if defined(STM32F469_479xx) -/** - * @brief Configures the PLLSAI clock multiplication and division factors. - * - * @note This function can be used only for STM32F469_479xx devices - * - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output - * This parameter must be a number in the range {2, 4, 6, or 8}.. - * - * @param PLLSAIQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLSAIR: specifies the division factor for LTDC clock - * This parameter must be a number between 2 and 7. - * - * @retval None - */ -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); - assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP)); - assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); - - RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28); -} -#endif /* STM32F469_479xx */ - -#if defined(STM32F446xx) -/** - * @brief Configures the PLLSAI clock multiplication and division factors. - * - * @note This function can be used only for STM32F446xx devices - * - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLLSAI jitter. - * - * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output - * This parameter must be a number in the range {2, 4, 6, or 8}. - * - * @param PLLSAIQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @retval None - */ -void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM)); - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); - assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP)); - assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); - - RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24); -} -#endif /* STM32F446xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) -/** - * @brief Configures the PLLSAI clock multiplication and division factors. - * - * @note This function can be used only for STM32F42xxx/43xxx devices - * - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * - * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock - * This parameter must be a number between 50 and 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * - * @param PLLSAIQ: specifies the division factor for SAI1 clock - * This parameter must be a number between 2 and 15. - * - * @param PLLSAIR: specifies the division factor for LTDC clock - * This parameter must be a number between 2 and 7. - * - * @retval None - */ -void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR) -{ - /* Check the parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN)); - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR)); - assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ)); - - RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28); -} -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */ - -/** - * @brief Enables or disables the PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices - * - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - * @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_PLLSAICmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_PLLSAION_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @param NewState: new state of the Clock Security System. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ClockSecuritySystemCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCO1Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source - * @param RCC_MCO1Div: specifies the MCO1 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO1Div_1: no division applied to MCO1 clock - * @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock - * @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock - * @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock - * @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock - * @retval None - */ -void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source)); - assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */ - tmpreg &= CFGR_MCO1_RESET_MASK; - - /* Select MCO1 clock source and prescaler */ - tmpreg |= RCC_MCO1Source | RCC_MCO1Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; - -#if defined(STM32F410xx) - RCC_MCO1Cmd(ENABLE); -#endif /* STM32F410xx */ -} - -/** - * @brief Selects the clock source to output on MCO2 pin(PC9). - * @note PC9 should be configured in alternate function mode. - * @param RCC_MCO2Source: specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx - * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices - * @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCO2Div: specifies the MCO2 prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCO2Div_1: no division applied to MCO2 clock - * @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock - * @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock - * @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock - * @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock - * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have - * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5). - * @retval None - */ -void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source)); - assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div)); - - tmpreg = RCC->CFGR; - - /* Clear MCO2 and MCO2PRE[2:0] bits */ - tmpreg &= CFGR_MCO2_RESET_MASK; - - /* Select MCO2 clock source and prescaler */ - tmpreg |= RCC_MCO2Source | RCC_MCO2Div; - - /* Store the new value */ - RCC->CFGR = tmpreg; - -#if defined(STM32F410xx) - RCC_MCO2Cmd(ENABLE); -#endif /* STM32F410xx */ -} - -/** - * @} - */ - -/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions - * @brief System, AHB and APB busses clocks configuration functions - * -@verbatim - =============================================================================== - ##### System, AHB and APB busses clocks configuration functions ##### - =============================================================================== - [..] - This section provide functions allowing to configure the System, AHB, APB1 and - APB2 busses clocks. - - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use RCC_I2SCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd() - functions to configure this clock. - (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - (+@) IWDG clock which is always the LSI clock. - - (#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency - of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending - on the device voltage range, the maximum frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160| - +---------------|----------------|----------------|-----------------|-----------------+ - (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz, - PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120| - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140| - |---------------|----------------|----------------|-----------------|-----------------| - |7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160| - |---------------|----------------|----------------|-----------------|-----------------| - |8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168| - +-------------------------------------------------------------------------------------+ - - (#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz, - PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 | - +-------------------------------------------------------------------------------------+ - - (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz, - PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum - frequency should be adapted accordingly: - +-------------------------------------------------------------------------------------+ - | Latency | HCLK clock frequency (MHz) | - | |---------------------------------------------------------------------| - | | voltage range | voltage range | voltage range | voltage range | - | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | - |---------------|----------------|----------------|-----------------|-----------------| - |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | - |---------------|----------------|----------------|-----------------|-----------------| - |1WS(2CPU cycle)|30 < HCLK <= 64 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | - |---------------|----------------|----------------|-----------------|-----------------| - |2WS(3CPU cycle)|64 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | - |---------------|----------------|----------------|-----------------|-----------------| - |3WS(4CPU cycle)|90 < HCLK <= 100|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | - |---------------|----------------|----------------|-----------------|-----------------| - |4WS(5CPU cycle)| NA |96 < HCLK <= 100|72 < HCLK <= 90 |64 < HCLK <= 80 | - |---------------|----------------|----------------|-----------------|-----------------| - |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 100 |80 < HCLK <= 96 | - |---------------|----------------|----------------|-----------------|-----------------| - |6WS(7CPU cycle)| NA | NA | NA |96 < HCLK <= 100 | - +-------------------------------------------------------------------------------------+ - - -@- On STM32F405xx/407xx and STM32F415xx/417xx devices: - (++) when VOS = '0', the maximum value of fHCLK = 144MHz. - (++) when VOS = '1', the maximum value of fHCLK = 168MHz. - [..] - On STM32F42xxx/43xxx/469xx/479xx devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz. - (++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz - [..] - On STM32F401x devices: - (++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz. - On STM32F410xx/STM32F411xE devices: - (++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz. - (++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz. - (++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz. - - You can use PWR_MainRegulatorModeConfig() function to control VOS bits. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the system clock (SYSCLK). - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use RCC_GetSYSCLKSource() function to know which clock is - * currently used as system clock source. - * @param RCC_SYSCLKSource: specifies the clock source used as system clock. - * This parameter can be one of the following values: - * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source - * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source - * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices) - * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices - * @retval None - */ -void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); - - tmpreg = RCC->CFGR; - - /* Clear SW[1:0] bits */ - tmpreg &= ~RCC_CFGR_SW; - - /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ - tmpreg |= RCC_SYSCLKSource; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the clock source used as system clock. - * @param None - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - 0x00: HSI used as system clock - * - 0x04: HSE used as system clock - * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices) - * - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices) - */ -uint8_t RCC_GetSYSCLKSource(void) -{ - return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS)); -} - -/** - * @brief Configures the AHB clock (HCLK). - * @note Depending on the device voltage range, the software has to set correctly - * these bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above - * "CPU, AHB and APB busses clocks configuration functions") - * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from - * the system clock (SYSCLK). - * This parameter can be one of the following values: - * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK - * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2 - * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4 - * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8 - * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16 - * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64 - * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128 - * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256 - * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512 - * @retval None - */ -void RCC_HCLKConfig(uint32_t RCC_SYSCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_HCLK(RCC_SYSCLK)); - - tmpreg = RCC->CFGR; - - /* Clear HPRE[3:0] bits */ - tmpreg &= ~RCC_CFGR_HPRE; - - /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ - tmpreg |= RCC_SYSCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the Low Speed APB clock (PCLK1). - * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB1 clock = HCLK - * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK1Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE1[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE1; - - /* Set PPRE1[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Configures the High Speed APB clock (PCLK2). - * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from - * the AHB clock (HCLK). - * This parameter can be one of the following values: - * @arg RCC_HCLK_Div1: APB2 clock = HCLK - * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2 - * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4 - * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8 - * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16 - * @retval None - */ -void RCC_PCLK2Config(uint32_t RCC_HCLK) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PCLK(RCC_HCLK)); - - tmpreg = RCC->CFGR; - - /* Clear PPRE2[2:0] bits */ - tmpreg &= ~RCC_CFGR_PPRE2; - - /* Set PPRE2[2:0] bits according to RCC_HCLK value */ - tmpreg |= RCC_HCLK << 3; - - /* Store the new value */ - RCC->CFGR = tmpreg; -} - -/** - * @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK, - * PCLK1 and PCLK2. - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold - * the clocks frequencies. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update the structure's field. Otherwise, any - * configuration based on this function will be incorrect. - * - * @retval None - */ -void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) -{ - uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) - uint32_t pllr = 2; -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; - break; - case 0x08: /* PLL P used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; - break; - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) - case 0x0C: /* PLL R used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2; - RCC_Clocks->SYSCLK_Frequency = pllvco/pllr; - break; -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - - default: - RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; - break; - } - /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ - - /* Get HCLK prescaler */ - tmp = RCC->CFGR & RCC_CFGR_HPRE; - tmp = tmp >> 4; - presc = APBAHBPrescTable[tmp]; - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; - - /* Get PCLK1 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE1; - tmp = tmp >> 10; - presc = APBAHBPrescTable[tmp]; - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; - - /* Get PCLK2 prescaler */ - tmp = RCC->CFGR & RCC_CFGR_PPRE2; - tmp = tmp >> 13; - presc = APBAHBPrescTable[tmp]; - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; -} - -/** - * @} - */ - -/** @defgroup RCC_Group3 Peripheral clocks configuration functions - * @brief Peripheral clocks configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral clocks configuration functions ##### - =============================================================================== - [..] This section provide functions allowing to configure the Peripheral clocks. - - (#) The RTC clock which is derived from the LSI, LSE or HSE clock divided - by 2 to 31. - - (#) After restart from Reset or wakeup from STANDBY, all peripherals are off - except internal SRAM, Flash and JTAG. Before to start using a peripheral - you have to enable its interface clock. You can do this using - RCC_AHBPeriphClockCmd(), RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions. - - (#) To reset the peripherals configuration (to the default state after device reset) - you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and - RCC_APB1PeriphResetCmd() functions. - - (#) To further reduce power consumption in SLEEP mode the peripheral clocks - can be disabled prior to executing the WFI or WFE instructions. - You can do this using RCC_AHBPeriphClockLPModeCmd(), - RCC_APB2PeriphClockLPModeCmd() and RCC_APB1PeriphClockLPModeCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using PWR_BackupAccessCmd(ENABLE) function before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using RCC_BackupResetCmd() function, or by - * a Power On Reset (POR). - * - * @param RCC_RTCCLKSource: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock - * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock - * @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * - * @retval None - */ -void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); - - if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300) - { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */ - tmpreg = RCC->CFGR; - - /* Clear RTCPRE[4:0] bits */ - tmpreg &= ~RCC_CFGR_RTCPRE; - - /* Configure HSE division factor for RTC clock */ - tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF); - - /* Store the new value */ - RCC->CFGR = tmpreg; - } - - /* Select the RTC clock source */ - RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF); -} - -/** - * @brief Enables or disables the RTC clock. - * @note This function must be used only after the RTC clock source was selected - * using the RCC_RTCCLKConfig function. - * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_RTCCLKCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState; -} - -/** - * @brief Forces or releases the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @param NewState: new state of the Backup domain reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_BackupResetCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState; -} - -#if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * - * @param RCC_I2SAPBx: specifies the APBx I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus - * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source - * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx)); - - if(RCC_I2SAPBx == RCC_I2SBus_APB1) - { - /* Clear APB1 I2Sx clock source selection bits */ - RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC; - /* Set new APB1 I2Sx clock source*/ - RCC->DCKCFGR |= RCC_I2SCLKSource; - } - else - { - /* Clear APB2 I2Sx clock source selection bits */ - RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC; - /* Set new APB2 I2Sx clock source */ - RCC->DCKCFGR |= (RCC_I2SCLKSource << 2); - } -} -#if defined(STM32F446xx) -/** - * @brief Configures the SAIx clock source (SAIxCLK). - * @note This function must be called before enabling the SAIx APB clock. - * - * @param RCC_SAIInstance: specifies the SAIx clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection - * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections - * - * @param RCC_SAICLKSource: specifies the SAI clock source. - * This parameter can be one of the following values: - * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source - * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source - * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source - * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source - * @retval None - */ -void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource)); - assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance)); - - if(RCC_SAIInstance == RCC_SAIInstance_SAI1) - { - /* Clear SAI1 clock source selection bits */ - RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC; - /* Set new SAI1 clock source */ - RCC->DCKCFGR |= RCC_SAICLKSource; - } - else - { - /* Clear SAI2 clock source selection bits */ - RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC; - /* Set new SAI2 clock source */ - RCC->DCKCFGR |= (RCC_SAICLKSource << 2); - } -} -#endif /* STM32F446xx */ - -#if defined(STM32F413_423xx) -/** - * @brief Configures SAI1BlockA clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source - * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source - * @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source - * @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source - * @retval None - */ -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; - - /* Set SAI Block A source selection value */ - tmpreg |= RCC_SAIBlockACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockB clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source - * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source - * @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source - * @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source - * @retval None - */ -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; - - /* Set SAI Block B source selection value */ - tmpreg |= RCC_SAIBlockBCLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */ - -#if defined(STM32F410xx) -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S clock. - * - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR. - * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin. - * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC. - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - /* Clear I2Sx clock source selection bits */ - RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC; - /* Set new I2Sx clock source*/ - RCC->DCKCFGR |= RCC_I2SCLKSource; -} -#endif /* STM32F410xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx) -/** - * @brief Configures the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param RCC_I2SCLKSource: specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source - * @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as I2S clock source - * @retval None - */ -void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource)); - - *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource; -} -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */ - -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -/** - * @brief Configures SAI1BlockA clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block A clock - * @arg RCC_SAIACLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block A clock - * @retval None - */ -void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1ASRC; - - /* Set SAI Block A source selection value */ - tmpreg |= RCC_SAIBlockACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures SAI1BlockB clock source selection. - * - * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. - * - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source. - * This parameter can be one of the following values: - * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 Block B clock - * @arg RCC_SAIBCLKSource_Ext: External clock mapped on the I2S_CKIN pin - * used as SAI1 Block B clock - * @retval None - */ -void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear RCC_DCKCFGR_SAI1BSRC[1:0] bits */ - tmpreg &= ~RCC_DCKCFGR_SAI1BSRC; - - /* Set SAI Block B source selection value */ - tmpreg |= RCC_SAIBlockBCLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ - -/** - * @brief Configures the SAI clock Divider coming from PLLI2S. - * - * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - * - * @note This function must be called before enabling the PLLI2S. - * - * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ - * - * @retval None - */ -void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ); - - /* Set PLLI2SDIVQ values */ - tmpreg |= (RCC_PLLI2SDivQ - 1); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the SAI clock Divider coming from PLLSAI. - * - * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ - * - * @retval None - */ -void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ); - - /* Set PLLSAIDIVQ values */ - tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -#if defined(STM32F413_423xx) -/** - * @brief Configures the SAI clock Divider coming from PLLI2S. - * - * @note This function can be used only for STM32F413_423xx - * - * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock. - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR - * @retval None - */ -void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLI2SDIVR[4:0] bits */ - tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR); - - /* Set PLLI2SDIVR values */ - tmpreg |= (RCC_PLLI2SDivR-1); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the SAI clock Divider coming from PLL. - * - * @note This function can be used only for STM32F413_423xx - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock. - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR - * - * @retval None - */ -void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLDIVR[12:8] */ - tmpreg &= ~(RCC_DCKCFGR_PLLDIVR); - - /* Set PLLDivR values */ - tmpreg |= ((RCC_PLLDivR - 1 ) << 8); - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} -#endif /* STM32F413_423xx */ - -/** - * @brief Configures the LTDC clock Divider coming from PLLSAI. - * - * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices. - * - * @note This function must be called before enabling the PLLSAI. - * - * @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock . - * LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR - * This parameter can be one of the following values: - * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2 - * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4 - * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8 - * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16 - * - * @retval None - */ -void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(RCC_PLLSAIDivR)); - - tmpreg = RCC->DCKCFGR; - - /* Clear PLLSAIDIVR[2:0] bits */ - tmpreg &= ~RCC_DCKCFGR_PLLSAIDIVR; - - /* Set PLLSAIDIVR values */ - tmpreg |= RCC_PLLSAIDivR; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -#if defined(STM32F412xG) || defined(STM32F413_423xx) -/** - * @brief Configures the DFSDM clock source (DFSDMCLK). - * @note This function must be called before enabling the DFSDM APB clock. - * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source. - * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source. - * - * @retval None - */ -void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear CKDFSDM-SEL bit */ - tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL; - - /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */ - tmpreg |= (RCC_DFSDMCLKSource << 31) ; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -/** - * @brief Configures the DFSDM Audio clock source (DFSDMACLK). - * @note This function must be called before enabling the DFSDM APB clock. - * @param RCC_DFSDM1ACLKSource: specifies the DFSDM clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. - * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source. - * - * @retval None - */ -void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear CKDFSDMA SEL bit */ - tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL; - - /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */ - tmpreg |= RCC_DFSDM1ACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} - -#if defined(STM32F413_423xx) -/** - * @brief Configures the DFSDM Audio clock source (DFSDMACLK). - * @note This function must be called before enabling the DFSDM APB clock. - * @param RCC_DFSDM2ACLKSource: specifies the DFSDM clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source. - * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source. - * - * @retval None - */ -void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource)); - - tmpreg = RCC->DCKCFGR; - - /* Clear CKDFSDMA SEL bit */ - tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL; - - /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */ - tmpreg |= RCC_DFSDMACLKSource; - - /* Store the new value */ - RCC->DCKCFGR = tmpreg; -} -#endif /* STM32F413_423xx */ -#endif /* STM32F412xG || STM32F413_423xx */ - -/** - * @brief Configures the Timers clocks prescalers selection. - * - * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices. - * - * @param RCC_TIMCLKPrescaler : specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPrescDesactivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * - * @arg RCC_TIMPrescActivated: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - * @retval None - */ -void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler) -{ - /* Check the parameters */ - assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler)); - - *(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler; -} - -/** - * @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_CCMDATARAMEN CCM data RAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1ENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1ENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2ENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2ENR &= ~RCC_AHB2Periph; - } -} - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: - * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) - * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3ENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3ENR &= ~RCC_AHB3Periph; - } -} -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -/** - * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB1ENR |= RCC_APB1Periph; - } - else - { - RCC->APB1ENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_EXTIT: EXTIIT clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) - * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) - * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) - * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->APB2ENR |= RCC_APB2Periph; - } - else - { - RCC->APB2ENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Forces or releases AHB1 peripheral reset. - * @param RCC_AHB1Periph: specifies the AHB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxxdevices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB1RSTR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1RSTR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Forces or releases AHB2 peripheral reset. - * @param RCC_AHB2Periph: specifies the AHB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB2RSTR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2RSTR &= ~RCC_AHB2Periph; - } -} - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Forces or releases AHB3 peripheral reset. - * @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset. - * This parameter must be: - * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices) - * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - RCC->AHB3RSTR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3RSTR &= ~RCC_AHB3Periph; - } -} -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -/** - * @brief Forces or releases Low Speed APB (APB1) peripheral reset. - * @param RCC_APB1Periph: specifies the APB1 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices) - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1RSTR |= RCC_APB1Periph; - } - else - { - RCC->APB1RSTR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Forces or releases High Speed APB (APB2) peripheral reset. - * @param RCC_APB2Periph: specifies the APB2 peripheral to reset. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) - * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) - * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) - * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices) - * @param NewState: new state of the specified peripheral reset. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2RSTR |= RCC_APB2Periph; - } - else - { - RCC->APB2RSTR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1Periph_GPIOA: GPIOA clock - * @arg RCC_AHB1Periph_GPIOB: GPIOB clock - * @arg RCC_AHB1Periph_GPIOC: GPIOC clock - * @arg RCC_AHB1Periph_GPIOD: GPIOD clock - * @arg RCC_AHB1Periph_GPIOE: GPIOE clock - * @arg RCC_AHB1Periph_GPIOF: GPIOF clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOG: GPIOG clock - * @arg RCC_AHB1Periph_GPIOI: GPIOI clock - * @arg RCC_AHB1Periph_GPIOJ: GPIOJ clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_GPIOK: GPIOK clock (STM32F42xxx/43xxx devices) - * @arg RCC_AHB1Periph_CRC: CRC clock - * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM interface clock - * @arg RCC_AHB1Periph_DMA1: DMA1 clock - * @arg RCC_AHB1Periph_DMA2: DMA2 clock - * @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices) - * @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock - * @arg RCC_AHB1Periph_ETH_MAC_Tx: Ethernet Transmission clock - * @arg RCC_AHB1Periph_ETH_MAC_Rx: Ethernet Reception clock - * @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock - * @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock - * @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB1LPENR |= RCC_AHB1Periph; - } - else - { - RCC->AHB1LPENR &= ~RCC_AHB1Periph; - } -} - -/** - * @brief Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_AHB2Periph_DCMI: DCMI clock - * @arg RCC_AHB2Periph_CRYP: CRYP clock - * @arg RCC_AHB2Periph_HASH: HASH clock - * @arg RCC_AHB2Periph_RNG: RNG clock - * @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB2LPENR |= RCC_AHB2Periph; - } - else - { - RCC->AHB2LPENR &= ~RCC_AHB2Periph; - } -} - -#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock. - * This parameter must be: - * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices) - * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->AHB3LPENR |= RCC_AHB3Periph; - } - else - { - RCC->AHB3LPENR &= ~RCC_AHB3Periph; - } -} -#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */ - -/** - * @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB1Periph_TIM2: TIM2 clock - * @arg RCC_APB1Periph_TIM3: TIM3 clock - * @arg RCC_APB1Periph_TIM4: TIM4 clock - * @arg RCC_APB1Periph_TIM5: TIM5 clock - * @arg RCC_APB1Periph_TIM6: TIM6 clock - * @arg RCC_APB1Periph_TIM7: TIM7 clock - * @arg RCC_APB1Periph_TIM12: TIM12 clock - * @arg RCC_APB1Periph_TIM13: TIM13 clock - * @arg RCC_APB1Periph_TIM14: TIM14 clock - * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices) - * @arg RCC_APB1Periph_WWDG: WWDG clock - * @arg RCC_APB1Periph_SPI2: SPI2 clock - * @arg RCC_APB1Periph_SPI3: SPI3 clock - * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices) - * @arg RCC_APB1Periph_USART2: USART2 clock - * @arg RCC_APB1Periph_USART3: USART3 clock - * @arg RCC_APB1Periph_UART4: UART4 clock - * @arg RCC_APB1Periph_UART5: UART5 clock - * @arg RCC_APB1Periph_I2C1: I2C1 clock - * @arg RCC_APB1Periph_I2C2: I2C2 clock - * @arg RCC_APB1Periph_I2C3: I2C3 clock - * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock - * @arg RCC_APB1Periph_CAN1: CAN1 clock - * @arg RCC_APB1Periph_CAN2: CAN2 clock - * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices) - * @arg RCC_APB1Periph_PWR: PWR clock - * @arg RCC_APB1Periph_DAC: DAC clock - * @arg RCC_APB1Periph_UART7: UART7 clock - * @arg RCC_APB1Periph_UART8: UART8 clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB1LPENR |= RCC_APB1Periph; - } - else - { - RCC->APB1LPENR &= ~RCC_APB1Periph; - } -} - -/** - * @brief Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. - * This parameter can be any combination of the following values: - * @arg RCC_APB2Periph_TIM1: TIM1 clock - * @arg RCC_APB2Periph_TIM8: TIM8 clock - * @arg RCC_APB2Periph_USART1: USART1 clock - * @arg RCC_APB2Periph_USART6: USART6 clock - * @arg RCC_APB2Periph_ADC1: ADC1 clock - * @arg RCC_APB2Periph_ADC2: ADC2 clock - * @arg RCC_APB2Periph_ADC3: ADC3 clock - * @arg RCC_APB2Periph_SDIO: SDIO clock - * @arg RCC_APB2Periph_SPI1: SPI1 clock - * @arg RCC_APB2Periph_SPI4: SPI4 clock - * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock - * @arg RCC_APB2Periph_EXTIT: EXTIIT clock - * @arg RCC_APB2Periph_TIM9: TIM9 clock - * @arg RCC_APB2Periph_TIM10: TIM10 clock - * @arg RCC_APB2Periph_TIM11: TIM11 clock - * @arg RCC_APB2Periph_SPI5: SPI5 clock - * @arg RCC_APB2Periph_SPI6: SPI6 clock - * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices) - * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices) - * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices) - * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices) - * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices) - * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices) - * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices) - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->APB2LPENR |= RCC_APB2Periph; - } - else - { - RCC->APB2LPENR &= ~RCC_APB2Periph; - } -} - -/** - * @brief Configures the External Low Speed oscillator mode (LSE mode). - * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices. - * @param Mode: specifies the LSE mode. - * This parameter can be one of the following values: - * @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode. - * @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode. - * @retval None - */ -void RCC_LSEModeConfig(uint8_t RCC_Mode) -{ - /* Check the parameters */ - assert_param(IS_RCC_LSE_MODE(RCC_Mode)); - - if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE) - { - SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } - else - { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); - } -} - -#if defined(STM32F410xx) || defined(STM32F413_423xx) -/** - * @brief Configures the LPTIM1 clock Source. - * @note This feature is only available for STM32F410xx devices. - * @param RCC_ClockSource: specifies the LPTIM1 clock Source. - * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected. - * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected. - * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected. - * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected. - * @retval None - */ -void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource)); - - /* Clear LPTIM1 clock source selection source bits */ - RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL; - /* Set new LPTIM1 clock source */ - RCC->DCKCFGR2 |= RCC_ClockSource; -} -#endif /* STM32F410xx || STM32F413_423xx */ - -#if defined(STM32F469_479xx) -/** - * @brief Configures the DSI clock Source. - * @note This feature is only available for STM32F469_479xx devices. - * @param RCC_ClockSource: specifies the DSI clock Source. - * This parameter can be one of the following values: - * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case). - * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode). - * @retval None - */ -void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource)); - - if(RCC_ClockSource == RCC_DSICLKSource_PLLR) - { - SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL); - } -} -#endif /* STM32F469_479xx */ - -#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx) -/** - * @brief Configures the 48MHz clock Source. - * @note This feature is only available for STM32F446xx/STM32F469_479xx devices. - * @param RCC_ClockSource: specifies the 48MHz clock Source. - * This parameter can be one of the following values: - * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected. - * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected. - * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ - * @retval None - */ -void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource)); -#if defined(STM32F469_479xx) - if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI) - { - SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL); - } -#elif defined(STM32F446xx) - if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI) - { - SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); - } -#elif defined(STM32F412xG) || defined(STM32F413_423xx) - if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ) - { - SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL); - } -#else -#endif /* STM32F469_479xx */ -} - -/** - * @brief Configures the SDIO clock Source. - * @note This feature is only available for STM32F469_479xx/STM32F446xx devices. - * @param RCC_ClockSource: specifies the SDIO clock Source. - * This parameter can be one of the following values: - * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected. - * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected. - * @retval None - */ -void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource)); -#if defined(STM32F469_479xx) - if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK) - { - SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL); - } -#elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) - if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK) - { - SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL); - } -#else -#endif /* STM32F469_479xx */ -} -#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */ - -#if defined(STM32F446xx) -/** - * @brief Enables or disables the AHB1 clock gating for the specified IPs. - * @note This feature is only available for STM32F446xx devices. - * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating. - * This parameter can be any combination of the following values: - * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock - * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock - * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock - * @arg RCC_AHB1ClockGating_SPARE: Spare clock - * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock - * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock - * @arg RCC_AHB1ClockGating_RCC: RCC clock - * @param NewState: new state of the specified peripheral clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating)); - - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - RCC->CKGATENR &= ~RCC_AHB1ClockGating; - } - else - { - RCC->CKGATENR |= RCC_AHB1ClockGating; - } -} - -/** - * @brief Configures the SPDIFRX clock Source. - * @note This feature is only available for STM32F446xx devices. - * @param RCC_ClockSource: specifies the SPDIFRX clock Source. - * This parameter can be one of the following values: - * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected. - * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected. - * @retval None - */ -void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource)); - - if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP) - { - SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL); - } -} - -/** - * @brief Configures the CEC clock Source. - * @note This feature is only available for STM32F446xx devices. - * @param RCC_ClockSource: specifies the CEC clock Source. - * This parameter can be one of the following values: - * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected. - * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected. - * @retval None - */ -void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource)); - - if(RCC_ClockSource == RCC_CECCLKSource_LSE) - { - SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL); - } - else - { - CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL); - } -} -#endif /* STM32F446xx */ - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Configures the FMPI2C1 clock Source. - * @note This feature is only available for STM32F446xx devices. - * @param RCC_ClockSource: specifies the FMPI2C1 clock Source. - * This parameter can be one of the following values: - * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected. - * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected. - * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected. - * @retval None - */ -void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource) -{ - /* Check the parameters */ - assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource)); - - /* Clear FMPI2C1 clock source selection source bits */ - RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL; - /* Set new FMPI2C1 clock source */ - RCC->DCKCFGR2 |= RCC_ClockSource; -} -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */ -/** - * @} - */ - -#if defined(STM32F410xx) -/** - * @brief Enables or disables the MCO1. - * @param NewState: new state of the MCO1. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_MCO1Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the MCO2. - * @param NewState: new state of the MCO2. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_MCO2Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState; -} -#endif /* STM32F410xx */ - -/** @defgroup RCC_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RCC interrupts. - * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) - * @param NewState: new state of the specified RCC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RCC_IT(RCC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT; - } - else - { - /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */ - *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; - } -} - -/** - * @brief Checks whether the specified RCC flag is set or not. - * @param RCC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready - * @arg RCC_FLAG_PLLRDY: main PLL clock ready - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready - * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset - * @arg RCC_FLAG_PINRST: Pin reset - * @arg RCC_FLAG_PORRST: POR/PDR reset - * @arg RCC_FLAG_SFTRST: Software reset - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset - * @arg RCC_FLAG_LPWRRST: Low Power reset - * @retval The new state of RCC_FLAG (SET or RESET). - */ -FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) -{ - uint32_t tmp = 0; - uint32_t statusreg = 0; - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_FLAG(RCC_FLAG)); - - /* Get the RCC register index */ - tmp = RCC_FLAG >> 5; - if (tmp == 1) /* The flag to check is in CR register */ - { - statusreg = RCC->CR; - } - else if (tmp == 2) /* The flag to check is in BDCR register */ - { - statusreg = RCC->BDCR; - } - else /* The flag to check is in CSR register */ - { - statusreg = RCC->CSR; - } - - /* Get the flag position */ - tmp = RCC_FLAG & FLAG_MASK; - if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the flag status */ - return bitstatus; -} - -/** - * @brief Clears the RCC reset flags. - * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, - * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST - * @param None - * @retval None - */ -void RCC_ClearFlag(void) -{ - /* Set RMVF bit to clear the reset flags */ - RCC->CSR |= RCC_CSR_RMVF; -} - -/** - * @brief Checks whether the specified RCC interrupt has occurred or not. - * @param RCC_IT: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of RCC_IT (SET or RESET). - */ -ITStatus RCC_GetITStatus(uint8_t RCC_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_GET_IT(RCC_IT)); - - /* Check the status of the specified RCC interrupt */ - if ((RCC->CIR & RCC_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - /* Return the RCC_IT status */ - return bitstatus; -} - -/** - * @brief Clears the RCC's interrupt pending bits. - * @param RCC_IT: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt - * @arg RCC_IT_LSERDY: LSE ready interrupt - * @arg RCC_IT_HSIRDY: HSI ready interrupt - * @arg RCC_IT_HSERDY: HSE ready interrupt - * @arg RCC_IT_PLLRDY: main PLL ready interrupt - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt - * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices) - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval None - */ -void RCC_ClearITPendingBit(uint8_t RCC_IT) -{ - /* Check the parameters */ - assert_param(IS_RCC_CLEAR_IT(RCC_IT)); - - /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt - pending bits */ - *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c deleted file mode 100644 index 02ed12413..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c +++ /dev/null @@ -1,406 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rng.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization and Configuration - * + Get 32 bit Random number - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable The RNG controller clock using - RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function. - - (#) Activate the RNG peripheral using RNG_Cmd() function. - - (#) Wait until the 32 bit Random number Generator contains a valid random data - (using polling/interrupt mode). For more details, refer to "Interrupts and - flags management functions" module description. - - (#) Get the 32 bit Random number using RNG_GetRandomNumber() function - - (#) To get another 32 bit Random number, go to step 3. - - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rng.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RNG - * @brief RNG driver modules - * @{ - */ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RNG_Private_Functions - * @{ - */ - -/** @defgroup RNG_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Initialize the RNG peripheral - (+) Enable or disable the RNG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief De-initializes the RNG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void RNG_DeInit(void) -{ -#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx) - /* Enable RNG reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE); -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */ -#if defined(STM32F410xx) - /* Enable RNG reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, ENABLE); - - /* Release RNG from reset state */ - RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, DISABLE); -#endif /* STM32F410xx*/ -} - -/** - * @brief Enables or disables the RNG peripheral. - * @param NewState: new state of the RNG peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG */ - RNG->CR |= RNG_CR_RNGEN; - } - else - { - /* Disable the RNG */ - RNG->CR &= ~RNG_CR_RNGEN; - } -} -/** - * @} - */ - -/** @defgroup RNG_Group2 Get 32 bit Random number function - * @brief Get 32 bit Random number function - * - -@verbatim - =============================================================================== - ##### Get 32 bit Random number function ##### - =============================================================================== - [..] This section provides a function allowing to get the 32 bit Random number - - (@) Before to call this function you have to wait till DRDY flag is set, - using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - -@endverbatim - * @{ - */ - - -/** - * @brief Returns a 32-bit random number. - * - * @note Before to call this function you have to wait till DRDY (data ready) - * flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. - * @note Each time the Random number data is read (using RNG_GetRandomNumber() - * function), the RNG_FLAG_DRDY flag is automatically cleared. - * @note In the case of a seed error, the generation of random numbers is - * interrupted for as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable - * and enable the RNG peripheral (using RNG_Cmd() function) to - * reinitialize and restart the RNG. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User have - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) - * function) . The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * - * @param None - * @retval 32-bit random number. - */ -uint32_t RNG_GetRandomNumber(void) -{ - /* Return the 32 bit random number from the DR register */ - return RNG->DR; -} - - -/** - * @} - */ - -/** @defgroup RNG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure the RNG Interrupts and - to get the status and clear flags and Interrupts pending bits. - - [..] The RNG provides 3 Interrupts sources and 3 Flags: - - *** Flags : *** - =============== - [..] - (#) RNG_FLAG_DRDY : In the case of the RNG_DR register contains valid - random data. it is cleared by reading the valid data(using - RNG_GetRandomNumber() function). - - (#) RNG_FLAG_CECS : In the case of a seed error detection. - - (#) RNG_FLAG_SECS : In the case of a clock error detection. - - *** Interrupts *** - ================== - [..] If enabled, an RNG interrupt is pending : - - (#) In the case of the RNG_DR register contains valid random data. - This interrupt source is cleared once the RNG_DR register has been read - (using RNG_GetRandomNumber() function) until a new valid value is - computed; or - (#) In the case of a seed error : One of the following faulty sequences has - been detected: - (++) More than 64 consecutive bits at the same value (0 or 1) - (++) More than 32 consecutive alternance of 0 and 1 (0101010101...01) - This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI) - function; or - (#) In the case of a clock error : the PLL48CLK (RNG peripheral clock source) - was not correctly detected (fPLL48CLK< fHCLK/16). This interrupt source is - cleared using RNG_ClearITPendingBit(RNG_IT_CEI) function. - -@- note In this case, User have to check that the clock controller is - correctly configured to provide the RNG clock. - - *** Managing the RNG controller events : *** - ============================================ - [..] The user should identify which mode will be used in his application to manage - the RNG controller events: Polling mode or Interrupt mode. - - (#) In the Polling Mode it is advised to use the following functions: - (++) RNG_GetFlagStatus() : to check if flags events occur. - (++) RNG_ClearFlag() : to clear the flags events. - - -@@- RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only - by reading the Random number data. - - (#) In the Interrupt Mode it is advised to use the following functions: - (++) RNG_ITConfig() : to enable or disable the interrupt source. - (++) RNG_GetITStatus() : to check if Interrupt occurs. - (++) RNG_ClearITPendingBit() : to clear the Interrupt pending Bit - (corresponding Flag). - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the RNG interrupt. - * @note The RNG provides 3 interrupt sources, - * - Computed data is ready event (DRDY), and - * - Seed error Interrupt (SEI) and - * - Clock error Interrupt (CEI), - * all these interrupts sources are enabled by setting the IE bit in - * CR register. However, each interrupt have its specific status bit - * (see RNG_GetITStatus() function) and clear bit except the DRDY event - * (see RNG_ClearITPendingBit() function). - * @param NewState: new state of the RNG interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RNG_ITConfig(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the RNG interrupt */ - RNG->CR |= RNG_CR_IE; - } - else - { - /* Disable the RNG interrupt */ - RNG->CR &= ~RNG_CR_IE; - } -} - -/** - * @brief Checks whether the specified RNG flag is set or not. - * @param RNG_FLAG: specifies the RNG flag to check. - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data Ready flag. - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @retval The new state of RNG_FLAG (SET or RESET). - */ -FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_FLAG(RNG_FLAG)); - - /* Check the status of the specified RNG flag */ - if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET) - { - /* RNG_FLAG is set */ - bitstatus = SET; - } - else - { - /* RNG_FLAG is reset */ - bitstatus = RESET; - } - /* Return the RNG_FLAG status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG flags. - * @param RNG_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg RNG_FLAG_CECS: Clock Error Current flag. - * @arg RNG_FLAG_SECS: Seed Error Current flag. - * @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. - * This flag is cleared only by reading the Random number data (using - * RNG_GetRandomNumber() function). - * @retval None - */ -void RNG_ClearFlag(uint8_t RNG_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG)); - /* Clear the selected RNG flags */ - RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); -} - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param RNG_IT: specifies the RNG interrupt source to check. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval The new state of RNG_IT (SET or RESET). - */ -ITStatus RNG_GetITStatus(uint8_t RNG_IT) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_RNG_GET_IT(RNG_IT)); - - /* Check the status of the specified RNG interrupt */ - if ((RNG->SR & RNG_IT) != (uint8_t)RESET) - { - /* RNG_IT is set */ - bitstatus = SET; - } - else - { - /* RNG_IT is reset */ - bitstatus = RESET; - } - /* Return the RNG_IT status */ - return bitstatus; -} - - -/** - * @brief Clears the RNG interrupt pending bit(s). - * @param RNG_IT: specifies the RNG interrupt pending bit(s) to clear. - * This parameter can be any combination of the following values: - * @arg RNG_IT_CEI: Clock Error Interrupt. - * @arg RNG_IT_SEI: Seed Error Interrupt. - * @retval None - */ -void RNG_ClearITPendingBit(uint8_t RNG_IT) -{ - /* Check the parameters */ - assert_param(IS_RNG_IT(RNG_IT)); - - /* Clear the selected RNG interrupt pending bit */ - RNG->SR = (uint8_t)~RNG_IT; -} -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */ -/** - * @} - */ - -/** - * @} - */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c deleted file mode 100644 index ea566ced6..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c +++ /dev/null @@ -1,2765 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_rtc.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization - * + Calendar (Time and Date) configuration - * + Alarms (Alarm A and Alarm B) configuration - * + WakeUp Timer configuration - * + Daylight Saving configuration - * + Output pin Configuration - * + Coarse digital Calibration configuration - * + Smooth digital Calibration configuration - * + TimeStamp configuration - * + Tampers configuration - * + Backup Data Registers configuration - * + Shift control synchronisation - * + RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### Backup Domain Operating Condition ##### - =================================================================== - [..] The real-time clock (RTC), the RTC backup registers, and the backup - SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply - the RTC when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC to operate even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following functions are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - (#) PI8 can be used as a GPIO or as the RTC_AF2 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following functions are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - (#) PI8 can be used as the RTC_AF2 pin - - - ##### Backup Domain Reset ##### - =================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way of resetting the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). You can use the - RCC_BackupResetCmd(). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - - - ##### Backup Domain Access ##### - =================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - RCC_APB1PeriphClockCmd() function. - (+) Enable access to RTC domain using the PWR_BackupAccessCmd() function. - (+) Select the RTC clock source using the RCC_RTCCLKConfig() function. - (+) Enable RTC Clock using the RCC_RTCCLKCmd() function. - - - ##### How to use RTC Driver ##### - =================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above) - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime() - and RTC_SetDate() functions. - (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate() functions. - (+) Use the RTC_DayLightSavingConfig() function to add or sub one - hour to the RTC Calendar. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the RTC_SetAlarm() function. - (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function - (+) To read the RTC Alarm, use the RTC_GetAlarm() function. - (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig() - function. - (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() function - (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function - (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() - function. - - *** Outputs configuration *** - ============================= - [..] The RTC has 2 different outputs: - (+) AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B - and WaKeUp signals. To output the selected RTC signal on RTC_AF1 pin, use the - RTC_OutputConfig() function. - (+) AFO_CALIB: this output is 512Hz signal or 1Hz. To output the RTC Clock on - RTC_AF1 pin, use the RTC_CalibOutputCmd() function. - - *** Smooth digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Original Digital Calibration Value and the corresponding - calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() - function. - - *** Coarse digital Calibration configuration *** - ================================================ - [..] - (+) Configure the RTC Coarse Calibration Value and the corresponding - sign using the RTC_CoarseCalibConfig() function. - (+) Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() function - - *** TimeStamp configuration *** - =============================== - [..] - (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp using the RTC - _TimeStampCmd() function. - (+) To read the RTC TimeStamp Time and Date register, use the RTC_GetTimeStamp() - function. - (+) To read the RTC TimeStamp SubSecond register, use the - RTC_GetTimeStampSubSecond() function. - (+) The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13) - or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in - RTC_TAFCR register. You can use the RTC_TamperPinSelection() function to - select the corresponding pin. - - *** Tamper configuration *** - ============================ - [..] - (+) Enable the RTC Tamper using the RTC_TamperCmd() function. - (+) Configure the Tamper filter count using RTC_TamperFilterConfig() - function. - (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper - filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() - function. - (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig() - function. - (+) Configure the Tamper precharge or discharge duration using - RTC_TamperPinsPrechargeDuration() function. - (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function. - (+) Enable the Time stamp on Tamper detection event using - TC_TSOnTamperDetecCmd() function. - (+) The TIMESTAMP alternate function can be mapped to either RTC_AF1 - or RTC_AF2 depending on the value of the TSINSEL bit in the RTC_TAFCR - register. You can use the RTC_TimeStampPinSelection() function to select - the corresponding pin. - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister() - function. - (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister() - function. - - - ##### RTC and low power modes ##### - =================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC time stamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby lowpower modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and Standby modes is possible only when the RTC clock source - is LSE or LSI. - - - ##### Selection of RTC_AF1 alternate functions ##### - =================================================================== - [..] The RTC_AF1 pin (PC13) can be used for the following purposes: - (+) AFO_ALARM output - (+) AFO_CALIB output - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - - [..] - +-------------------------------------------------------------------------------------------------------------+ - | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | | | selection | selection |Configuration | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output OD | 1 |Don't care|Don't care | Don't care | care | care | 0 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Alarm out | | | | | Don't | Don't | | - | output PP | 1 |Don't care|Don't care | Don't care | care | care | 1 | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Calibration out | | | | | Don't | Don't | | - | output PP | 0 | 1 |Don't care | Don't care | care | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | | | Don't | | - | floating | 0 | 0 | 1 | 0 | 0 | care | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | | | - | TAMPER input | 0 | 0 | 1 | 1 | 0 | 0 | Don't care | - | floating | | | | | | | | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | | | Don't | | | - | floating | 0 | 0 | 0 | 1 | care | 0 | Don't care | - |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | 0 | 0 | Don't care | Don't care | Don't care | - +-------------------------------------------------------------------------------------------------------------+ - - - ##### Selection of RTC_AF2 alternate functions ##### - =================================================================== - [..] The RTC_AF2 pin (PI8) can be used for the following purposes: - (+) AFI_TAMPER - (+) AFI_TIMESTAMP - [..] - +---------------------------------------------------------------------------------------+ - | Pin |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL | TSINSEL |ALARMOUTTYPE | - | configuration | ENABLED | ENABLED |TAMPER1 pin |TIMESTAMP pin | AFO_ALARM | - | and function | | | selection | selection |Configuration | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TAMPER input | | | | Don't | | - | floating | 1 | 0 | 1 | care | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP and | | | | | | - | TAMPER input | 1 | 1 | 1 | 1 | Don't care | - | floating | | | | | | - |-----------------|-----------|--------------|------------|--------------|--------------| - | TIMESTAMP input | | | Don't | | | - | floating | 0 | 1 | care | 1 | Don't care | - |-----------------|-----------|--------------|------------|--------------|--------------| - | Standard GPIO | 0 | 0 | Don't care | Don't care | Don't care | - +---------------------------------------------------------------------------------------+ - - -@endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_rtc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup RTC - * @brief RTC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) - -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000) -#define RECALPF_TIMEOUT ((uint32_t) 0x00020000) -#define SHPF_TIMEOUT ((uint32_t) 0x00001000) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint8_t RTC_ByteToBcd2(uint8_t Value); -static uint8_t RTC_Bcd2ToByte(uint8_t Value); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions - * @{ - */ - -/** @defgroup RTC_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to initialize and configure the RTC - Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers - Write protection, enter and exit the RTC initialization mode, RTC registers - synchronization check and reference clock detection enable. - - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is - split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize consumption. - - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - - (#) To Configure the RTC Calendar, user application should enter initialization - mode. In this mode, the calendar counter is stopped and its value can be - updated. When the initialization sequence is complete, the calendar restarts - counting after 4 RTCCLK cycles. - - (#) To read the calendar through the shadow registers after Calendar initialization, - calendar update or after wakeup from low power modes the software must first - clear the RSF flag. The software must then wait until it is set again before - reading the calendar, which means that the calendar registers have been - correctly copied into the RTC_TR and RTC_DR shadow registers. - The RTC_WaitForSynchro() function implements the above software sequence - (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are deinitialized - * - ERROR: RTC registers are not deinitialized - */ -ErrorStatus RTC_DeInit(void) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Reset TR, DR and CR registers */ - RTC->TR = (uint32_t)0x00000000; - RTC->DR = (uint32_t)0x00002101; - /* Reset All CR bits except CR[2:0] */ - RTC->CR &= (uint32_t)0x00000007; - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - /* Reset all RTC CR register bits */ - RTC->CR &= (uint32_t)0x00000000; - RTC->WUTR = (uint32_t)0x0000FFFF; - RTC->PRER = (uint32_t)0x007F00FF; - RTC->CALIBR = (uint32_t)0x00000000; - RTC->ALRMAR = (uint32_t)0x00000000; - RTC->ALRMBR = (uint32_t)0x00000000; - RTC->SHIFTR = (uint32_t)0x00000000; - RTC->CALR = (uint32_t)0x00000000; - RTC->ALRMASSR = (uint32_t)0x00000000; - RTC->ALRMBSSR = (uint32_t)0x00000000; - - /* Reset ISR register and exit initialization mode */ - RTC->ISR = (uint32_t)0x00000000; - - /* Reset Tamper and alternate functions configuration register */ - RTC->TAFCR = 0x00000000; - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Clear RTC CR FMT Bit */ - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); - - /* Configure the RTC PRER */ - RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); - RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_InitStruct member with its default value. - * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) -{ - /* Initialize the RTC_HourFormat member */ - RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24; - - /* Initialize the RTC_AsynchPrediv member */ - RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; - - /* Initialize the RTC_SynchPrediv member */ - RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; -} - -/** - * @brief Enables or disables the RTC registers write protection. - * @note All the RTC registers are write protected except for RTC_ISR[13:8], - * RTC_TAFCR and RTC_BKPxR. - * @note Writing a wrong key reactivates the write protection. - * @note The protection mechanism is not affected by system reset. - * @param NewState: new state of the write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_WriteProtectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - } - else - { - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - } -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus RTC_EnterInitMode(void) -{ - __IO uint32_t initcounter = 0x00; - ErrorStatus status = ERROR; - uint32_t initstatus = 0x00; - - /* Check if the Initialization mode is set */ - if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do - { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_INITF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - } - else - { - status = SUCCESS; - } - - return (status); -} - -/** - * @brief Exits the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @param None - * @retval None - */ -void RTC_ExitInitMode(void) -{ - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; -} - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * RTC_WriteProtectionCmd(DISABLE) before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param None - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus RTC_WaitForSynchro(void) -{ - __IO uint32_t synchrocounter = 0; - ErrorStatus status = ERROR; - uint32_t synchrostatus = 0x00; - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear RSF flag */ - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - - /* Wait the registers to be synchronised */ - do - { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_RSF) != RESET) - { - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (status); -} - -/** - * @brief Enables or disables the RTC reference clock detection. - * @param NewState: new state of the RTC reference clock. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC reference clock detection is enabled - * - ERROR: RTC reference clock detection is disabled - */ -ErrorStatus RTC_RefClockCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the RTC reference clock detection */ - RTC->CR |= RTC_CR_REFCKON; - } - else - { - /* Disable the RTC reference clock detection */ - RTC->CR &= ~RTC_CR_REFCKON; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or Disables the Bypass Shadow feature. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @param NewState: new state of the Bypass Shadow feature. - * This parameter can be: ENABLE or DISABLE. - * @retval None -*/ -void RTC_BypassShadowCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Set the BYPSHAD bit */ - RTC->CR |= (uint8_t)RTC_CR_BYPSHAD; - } - else - { - /* Reset the BYPSHAD bit */ - RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group2 Time and Date configuration functions - * @brief Time and Date configuration functions - * -@verbatim - =============================================================================== - ##### Time and Date configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Calendar - (Time and Date). - -@endverbatim - * @{ - */ - -/** - * @brief Set the RTC current time. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); - } - else - { - RTC_TimeStruct->RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \ - ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); - } - else - { - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \ - (((uint32_t)RTC_TimeStruct->RTC_H12) << 16)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_TR register */ - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_TimeStruct member with its default value - * (Time = 00h:00min:00sec). - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->RTC_H12 = RTC_H12_AM; - RTC_TimeStruct->RTC_Hours = 0; - RTC_TimeStruct->RTC_Minutes = 0; - RTC_TimeStruct->RTC_Seconds = 0; -} - -/** - * @brief Get the RTC current Time. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contain the returned current time configuration. - * @retval None - */ -void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8); - RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); - RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); - RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); - } -} - -/** - * @brief Gets the RTC current Calendar Sub seconds value. - * @note This function freeze the Time and Date registers after reading the - * SSR register. - * @param None - * @retval RTC current Calendar Sub seconds value. - */ -uint32_t RTC_GetSubSecond(void) -{ - uint32_t tmpreg = 0; - - /* Get sub seconds values from the correspondent registers*/ - tmpreg = (uint32_t)(RTC->SSR); - - /* Read DR register to unfroze calendar registers */ - (void) (RTC->DR); - - return (tmpreg); -} - -/** - * @brief Set the RTC current date. - * @param RTC_Format: specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Date register is configured - * - ERROR: RTC Date register is not configured - */ -ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) - { - RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; - } - if (RTC_Format == RTC_Format_BIN) - { - assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); - assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); - assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - assert_param(IS_RTC_MONTH(tmpreg)); - tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - assert_param(IS_RTC_DATE(tmpreg)); - } - assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ - (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_DateStruct->RTC_Date) | \ - (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ - ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the RTC_DR register */ - RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((RTC->CR & RTC_CR_BYPSHAD) == RESET) - { - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Fills each RTC_DateStruct member with its default value - * (Monday, January 01 xx00). - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be - * initialized. - * @retval None - */ -void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; - RTC_DateStruct->RTC_Date = 1; - RTC_DateStruct->RTC_Month = RTC_Month_January; - RTC_DateStruct->RTC_Year = 0; -} - -/** - * @brief Get the RTC current date. - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will - * contain the returned current date configuration. - * @retval None - */ -void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the RTC_TR register */ - tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); - RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); - RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the structure parameters to Binary format */ - RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); - RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); - RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group3 Alarms configuration functions - * @brief Alarms (Alarm A and Alarm B) configuration functions - * -@verbatim - =============================================================================== - ##### Alarms A and B configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC Alarms. - -@endverbatim - * @{ - */ - -/** - * @brief Set the specified RTC Alarm. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the RTC_AlarmCmd(DISABLE)). - * @param RTC_Format: specifies the format of the returned parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval None - */ -void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel)); - - if (RTC_Format == RTC_Format_BIN) - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); - } - assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); - assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); - } - } - else - { - if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); - assert_param(IS_RTC_HOUR12(tmpreg)); - assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); - } - else - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); - - if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); - } - else - { - tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); - } - } - - /* Check the input parameters format */ - if (RTC_Format != RTC_Format_BIN) - { - tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - else - { - tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ - ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \ - ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ - ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm register */ - if (RTC_Alarm == RTC_Alarm_A) - { - RTC->ALRMAR = (uint32_t)tmpreg; - } - else - { - RTC->ALRMBR = (uint32_t)tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Fills each RTC_AlarmStruct member with its default value - * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = - * all fields are masked). - * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which - * will be initialized. - * @retval None - */ -void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; - - /* Alarm Date Settings : Date = 1st day of the month */ - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; - RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; -} - -/** - * @brief Get the RTC Alarm value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will - * contains the output alarm configuration values. - * @retval None - */ -void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - assert_param(IS_RTC_ALARM(RTC_Alarm)); - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)(RTC->ALRMAR); - } - else - { - tmpreg = (uint32_t)(RTC->ALRMBR); - } - - /* Fill the structure with the read parameters */ - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \ - RTC_ALRMAR_HU)) >> 16); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \ - RTC_ALRMAR_MNU)) >> 8); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \ - RTC_ALRMAR_SU)); - RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); - RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); - - if (RTC_Format == RTC_Format_BIN) - { - RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Hours); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Minutes); - RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \ - RTC_AlarmTime.RTC_Seconds); - RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); - } -} - -/** - * @brief Enables or disables the specified RTC Alarm. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be any combination of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param NewState: new state of the specified alarm. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Alarm is enabled/disabled - * - ERROR: RTC Alarm is not enabled/disabled - */ -ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) -{ - __IO uint32_t alarmcounter = 0x00; - uint32_t alarmstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm state */ - if (NewState != DISABLE) - { - RTC->CR |= (uint32_t)RTC_Alarm; - - status = SUCCESS; - } - else - { - /* Disable the Alarm in RTC_CR register */ - RTC->CR &= (uint32_t)~RTC_Alarm; - - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - do - { - alarmstatus = RTC->ISR & (RTC_Alarm >> 8); - alarmcounter++; - } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00)); - - if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Configure the RTC AlarmA/B Sub seconds value and mask.* - * @note This function is performed only when the Alarm is disabled. - * @param RTC_Alarm: specifies the alarm to be configured. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param RTC_AlarmSubSecondValue: specifies the Sub seconds value. - * This parameter can be a value from 0 to 0x00007FFF. - * @param RTC_AlarmSubSecondMask: specifies the Sub seconds Mask. - * This parameter can be any combination of the following values: - * @arg RTC_AlarmSubSecondMask_All : All Alarm SS fields are masked. - * There is no comparison on sub seconds for Alarm. - * @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison. - * Only SS[0] is compared - * @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison. - * Only SS[1:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison. - * Only SS[2:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison. - * Only SS[3:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison. - * Only SS[4:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison. - * Only SS[5:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison. - * Only SS[6:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison. - * Only SS[7:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison. - * Only SS[8:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. - * Only SS[9:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. - * Only SS[10:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. - * Only SS[11:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. - * Only SS[12:0] are compared - * @arg RTC_AlarmSubSecondMask_SS14 : SS[14] is don't care in Alarm comparison. - * Only SS[13:0] are compared - * @arg RTC_AlarmSubSecondMask_None : SS[14:0] are compared and must match - * to activate alarm - * @retval None - */ -void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(RTC_Alarm)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Alarm A or Alarm B Sub Second registers */ - tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask); - - if (RTC_Alarm == RTC_Alarm_A) - { - /* Configure the Alarm A Sub Second register */ - RTC->ALRMASSR = tmpreg; - } - else - { - /* Configure the Alarm B Sub Second register */ - RTC->ALRMBSSR = tmpreg; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - -} - -/** - * @brief Gets the RTC Alarm Sub seconds value. - * @param RTC_Alarm: specifies the alarm to be read. - * This parameter can be one of the following values: - * @arg RTC_Alarm_A: to select Alarm A - * @arg RTC_Alarm_B: to select Alarm B - * @param None - * @retval RTC Alarm Sub seconds value. - */ -uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) -{ - uint32_t tmpreg = 0; - - /* Get the RTC_ALRMxR register */ - if (RTC_Alarm == RTC_Alarm_A) - { - tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - return (tmpreg); -} - -/** - * @} - */ - -/** @defgroup RTC_Group4 WakeUp Timer configuration functions - * @brief WakeUp Timer configuration functions - * -@verbatim - =============================================================================== - ##### WakeUp Timer configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to program and read the RTC WakeUp. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC Wakeup clock source. - * @note The WakeUp Clock source can only be changed when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpClock: Wakeup Clock source. - * This parameter can be one of the following values: - * @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16 - * @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8 - * @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4 - * @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2 - * @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE - * @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE - * @retval None - */ -void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the Wakeup Timer clock source bits in CR register */ - RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - RTC->CR |= (uint32_t)RTC_WakeUpClock; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the RTC Wakeup counter. - * @note The RTC WakeUp counter can only be written when the RTC WakeUp - * is disabled (Use the RTC_WakeUpCmd(DISABLE)). - * @param RTC_WakeUpCounter: specifies the WakeUp counter. - * This parameter can be a value from 0x0000 to 0xFFFF. - * @retval None - */ -void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter) -{ - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Wakeup Timer counter */ - RTC->WUTR = (uint32_t)RTC_WakeUpCounter; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC WakeUp timer counter value. - * @param None - * @retval The RTC WakeUp Counter value. - */ -uint32_t RTC_GetWakeUpCounter(void) -{ - /* Get the counter value */ - return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Enables or Disables the RTC WakeUp timer. - * @param NewState: new state of the WakeUp timer. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -ErrorStatus RTC_WakeUpCmd(FunctionalState NewState) -{ - __IO uint32_t wutcounter = 0x00; - uint32_t wutwfstatus = 0x00; - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the Wakeup Timer */ - RTC->CR |= (uint32_t)RTC_CR_WUTE; - status = SUCCESS; - } - else - { - /* Disable the Wakeup Timer */ - RTC->CR &= (uint32_t)~RTC_CR_WUTE; - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - do - { - wutwfstatus = RTC->ISR & RTC_ISR_WUTWF; - wutcounter++; - } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00)); - - if ((RTC->ISR & RTC_ISR_WUTWF) == RESET) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @} - */ - -/** @defgroup RTC_Group5 Daylight Saving configuration functions - * @brief Daylight Saving configuration functions - * -@verbatim - =============================================================================== - ##### Daylight Saving configuration functions ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC DayLight Saving. - -@endverbatim - * @{ - */ - -/** - * @brief Adds or substract one hour from the current time. - * @param RTC_DayLightSaveOperation: the value of hour adjustment. - * This parameter can be one of the following values: - * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) - * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) - * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit - * in CR register to store the operation. - * This parameter can be one of the following values: - * @arg RTC_StoreOperation_Reset: BCK Bit Reset - * @arg RTC_StoreOperation_Set: BCK Bit Set - * @retval None - */ -void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) -{ - /* Check the parameters */ - assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_BCK); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Returns the RTC Day Light Saving stored operation. - * @param None - * @retval RTC Day Light Saving stored operation. - * - RTC_StoreOperation_Reset - * - RTC_StoreOperation_Set - */ -uint32_t RTC_GetStoreOperation(void) -{ - return (RTC->CR & RTC_CR_BCK); -} - -/** - * @} - */ - -/** @defgroup RTC_Group6 Output pin Configuration function - * @brief Output pin Configuration function - * -@verbatim - =============================================================================== - ##### Output pin Configuration function ##### - =============================================================================== - - [..] This section provide functions allowing to configure the RTC Output source. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the RTC output source (AFO_ALARM). - * @param RTC_Output: Specifies which signal will be routed to the RTC output. - * This parameter can be one of the following values: - * @arg RTC_Output_Disable: No output selected - * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output - * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output - * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output - * @param RTC_OutputPolarity: Specifies the polarity of the output signal. - * This parameter can be one of the following: - * @arg RTC_OutputPolarity_High: The output pin is high when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @arg RTC_OutputPolarity_Low: The output pin is low when the - * ALRAF/ALRBF/WUTF is high (depending on OSEL) - * @retval None - */ -void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT(RTC_Output)); - assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Clear the bits to be configured */ - RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); - - /* Configure the output selection and polarity */ - RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @} - */ - -/** @defgroup RTC_Group7 Digital Calibration configuration functions - * @brief Coarse Calibration configuration functions - * -@verbatim - =============================================================================== - ##### Digital Calibration configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Coarse calibration parameters. - * @param RTC_CalibSign: specifies the sign of the coarse calibration value. - * This parameter can be one of the following values: - * @arg RTC_CalibSign_Positive: The value sign is positive - * @arg RTC_CalibSign_Negative: The value sign is negative - * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits). - * - * @note This Calibration value should be between 0 and 63 when using negative - * sign with a 2-ppm step. - * - * @note This Calibration value should be between 0 and 126 when using positive - * sign with a 4-ppm step. - * - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are initialized - * - ERROR: RTC Coarse calibration are not initialized - */ -ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign)); - assert_param(IS_RTC_CALIB_VALUE(Value)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - /* Set the coarse calibration value */ - RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value); - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the Coarse calibration process. - * @param NewState: new state of the Coarse calibration. - * This parameter can be: ENABLE or DISABLE. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Coarse calibration are enabled/disabled - * - ERROR: RTC Coarse calibration are not enabled/disabled - */ -ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Set Initialization mode */ - if (RTC_EnterInitMode() == ERROR) - { - status = ERROR; - } - else - { - if (NewState != DISABLE) - { - /* Enable the Coarse Calibration */ - RTC->CR |= (uint32_t)RTC_CR_DCE; - } - else - { - /* Disable the Coarse Calibration */ - RTC->CR &= (uint32_t)~RTC_CR_DCE; - } - /* Exit Initialization mode */ - RTC_ExitInitMode(); - - status = SUCCESS; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return status; -} - -/** - * @brief Enables or disables the RTC clock to be output through the relative pin. - * @param NewState: new state of the digital calibration Output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_CalibOutputCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Enable the RTC clock output */ - RTC->CR |= (uint32_t)RTC_CR_COE; - } - else - { - /* Disable the RTC clock output */ - RTC->CR &= (uint32_t)~RTC_CR_COE; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param RTC_CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. - * @arg RTC_CalibOutput_1Hz : A signal has a regular waveform at 1Hz. - * @retval None -*/ -void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /*clear flags before configuration */ - RTC->CR &= (uint32_t)~(RTC_CR_COSEL); - - /* Configure the RTC_CR register */ - RTC->CR |= (uint32_t)RTC_CalibOutput; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Configures the Smooth Calibration Settings. - * @param RTC_SmoothCalibPeriod : Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s. - * @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s. - * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibration period is 8s. - * @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK pulse every 2**11 pulses. - * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. - * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Calib registers are configured - * - ERROR: RTC Calib registers are not configured -*/ -ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, - uint32_t RTC_SmoothCalibPlusPulses, - uint32_t RTC_SmouthCalibMinusPulsesValue) -{ - ErrorStatus status = ERROR; - uint32_t recalpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* check if a calibration is pending*/ - if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) - { - /* wait until the Calibration is completed*/ - while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) - { - recalpfcount++; - } - } - - /* check if the calibration pending is completed or if there is no calibration operation at all*/ - if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) - { - /* Configure the Smooth calibration settings */ - RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue); - - status = SUCCESS; - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - - -/** @defgroup RTC_Group8 TimeStamp configuration functions - * @brief TimeStamp configuration functions - * -@verbatim - =============================================================================== - ##### TimeStamp configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or Disables the RTC TimeStamp functionality with the - * specified time stamp pin stimulating edge. - * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is - * activated. - * This parameter can be one of the following: - * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising - * edge of the related pin. - * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the - * falling edge of the related pin. - * @param NewState: new state of the TimeStamp. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Get the new configuration */ - if (NewState != DISABLE) - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); - } - else - { - tmpreg |= (uint32_t)(RTC_TimeStampEdge); - } - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Configure the Time Stamp TSEDGE and Enable bits */ - RTC->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Get the RTC TimeStamp value and masks. - * @param RTC_Format: specifies the format of the output parameters. - * This parameter can be one of the following values: - * @arg RTC_Format_BIN: Binary data format - * @arg RTC_Format_BCD: BCD data format - * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will - * contains the TimeStamp time values. - * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will - * contains the TimeStamp date values. - * @retval None - */ -void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, - RTC_DateTypeDef* RTC_StampDateStruct) -{ - uint32_t tmptime = 0, tmpdate = 0; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(RTC_Format)); - - /* Get the TimeStamp time and date registers values */ - tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16); - - /* Fill the Date structure fields with the read parameters */ - RTC_StampDateStruct->RTC_Year = 0; - RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8); - RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); - - /* Check the input parameters format */ - if (RTC_Format == RTC_Format_BIN) - { - /* Convert the Time structure parameters to Binary format */ - RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); - RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); - RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); - - /* Convert the Date structure parameters to Binary format */ - RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); - RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); - RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); - } -} - -/** - * @brief Get the RTC timestamp Sub seconds value. - * @param None - * @retval RTC current timestamp Sub seconds value. - */ -uint32_t RTC_GetTimeStampSubSecond(void) -{ - /* Get timestamp sub seconds values from the correspondent registers */ - return (uint32_t)(RTC->TSSSR); -} - -/** - * @} - */ - -/** @defgroup RTC_Group9 Tampers configuration functions - * @brief Tampers configuration functions - * -@verbatim - =============================================================================== - ##### Tampers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the select Tamper pin edge. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1 or RTC_Tamper 2 - * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that - * stimulates tamper event. - * This parameter can be one of the following values: - * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. - * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. - * @retval None - */ -void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); - - if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); - } - else - { - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); - } -} - -/** - * @brief Enables or Disables the Tamper detection. - * @param RTC_Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1 or RTC_Tamper_2 - * @param NewState: new state of the tamper pin. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(RTC_Tamper)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_Tamper; - } - else - { - /* Disable the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_Tamper; - } -} - -/** - * @brief Configures the Tampers Filter. - * @param RTC_TamperFilter: Specifies the tampers filter. - * This parameter can be one of the following values: - * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. - * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive - * samples at the active level - * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive - * samples at the active level - * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive - * samples at the active level - * @retval None - */ -void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); - - /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperFilter; -} - -/** - * @brief Configures the Tampers Sampling Frequency. - * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. - * This parameter can be one of the following values: - * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 32768 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 16384 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 8192 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 4096 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 2048 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 1024 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 512 - * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled - * with a frequency = RTCCLK / 256 - * @retval None - */ -void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); - - /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; -} - -/** - * @brief Configures the Tampers Pins input Precharge Duration. - * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input - * Precharge Duration. - * This parameter can be one of the following values: - * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged before sampling during 1 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged before sampling during 2 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged before sampling during 4 RTCCLK cycle - * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged before sampling during 8 RTCCLK cycle - * @retval None - */ -void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); - - /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); - - /* Configure the RTC_TAFCR register */ - RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; -} - -/** - * @brief Enables or Disables the TimeStamp on Tamper Detection Event. - * @note The timestamp is valid even the TSE bit in tamper control register - * is reset. - * @param NewState: new state of the timestamp on tamper event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Save timestamp on tamper detection event */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; - } - else - { - /* Tamper detection does not cause a timestamp to be saved */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; - } -} - -/** - * @brief Enables or Disables the Precharge of Tamper pin. - * @param NewState: new state of tamper pull up. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_TamperPullUpCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable precharge of the selected Tamper pin */ - RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; - } - else - { - /* Disable precharge of the selected Tamper pin */ - RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; - } -} - -/** - * @} - */ - -/** @defgroup RTC_Group10 Backup Data Registers configuration functions - * @brief Backup Data Registers configuration functions - * -@verbatim - =============================================================================== - ##### Backup Data Registers configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None - */ -void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param RTC_BKP_DR: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval None - */ -uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(RTC_BKP_DR)); - - tmp = RTC_BASE + 0x50; - tmp += (RTC_BKP_DR * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @} - */ - -/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions - * @brief RTC Tamper and TimeStamp Pins Selection and Output Type Config - * configuration functions - * -@verbatim - ================================================================================================== - ##### RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions ##### - ================================================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Selects the RTC Tamper Pin. - * @param RTC_TamperPin: specifies the RTC Tamper Pin. - * This parameter can be one of the following values: - * @arg RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin. - * @arg RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin. - * @retval None - */ -void RTC_TamperPinSelection(uint32_t RTC_TamperPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TamperPin); -} - -/** - * @brief Selects the RTC TimeStamp Pin. - * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin. - * @retval None - */ -void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin) -{ - /* Check the parameters */ - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL); - RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin); -} - -/** - * @brief Configures the RTC Output Pin mode. - * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. - * This parameter can be one of the following values: - * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in - * Open Drain mode. - * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in - * Push Pull mode. - * @retval None - */ -void RTC_OutputTypeConfig(uint32_t RTC_OutputType) -{ - /* Check the parameters */ - assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); - - RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE); - RTC->TAFCR |= (uint32_t)(RTC_OutputType); -} - -/** - * @} - */ - -/** @defgroup RTC_Group12 Shift control synchronisation functions - * @brief Shift control synchronisation functions - * -@verbatim - =============================================================================== - ##### Shift control synchronisation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register - * @param RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar. - * This parameter can be one of the following values : - * @arg RTC_ShiftAdd1S_Set : Add one second to the clock calendar. - * @arg RTC_ShiftAdd1S_Reset: No effect. - * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Shift registers are configured - * - ERROR: RTC Shift registers are not configured -*/ -ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) -{ - ErrorStatus status = ERROR; - uint32_t shpfcount = 0; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - /* Check if a Shift is pending*/ - if ((RTC->ISR & RTC_ISR_SHPF) != RESET) - { - /* Wait until the shift is completed*/ - while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) - { - shpfcount++; - } - } - - /* Check if the Shift pending is completed or if there is no Shift operation at all*/ - if ((RTC->ISR & RTC_ISR_SHPF) == RESET) - { - /* check if the reference clock detection is disabled */ - if((RTC->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); - - if(RTC_WaitForSynchro() == ERROR) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - else - { - status = ERROR; - } - } - else - { - status = ERROR; - } - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; - - return (ErrorStatus)(status); -} - -/** - * @} - */ - -/** @defgroup RTC_Group13 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] All RTC interrupts are connected to the EXTI controller. - - (+) To enable the RTC Alarm interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 17 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using - the RTC_SetAlarm() and RTC_AlarmCmd() functions. - - (+) To enable the RTC Wakeup interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 22 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the RTC_WKUP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to generate the RTC wakeup timer event using the - RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() - functions. - - (+) To enable the RTC Tamper interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select - the rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC tamper event using the - RTC_TamperTriggerConfig() and RTC_TamperCmd() functions. - - (+) To enable the RTC TimeStamp interrupt, the following sequence is required: - (++) Configure and enable the EXTI Line 21 in interrupt mode and select the - rising edge sensitivity using the EXTI_Init() function. - (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the - NVIC_Init() function. - (++) Configure the RTC to detect the RTC time stamp event using the - RTC_TimeStampCmd() functions. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified RTC interrupts. - * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt mask - * @arg RTC_IT_WUT: WakeUp Timer interrupt mask - * @arg RTC_IT_ALRB: Alarm B interrupt mask - * @arg RTC_IT_ALRA: Alarm A interrupt mask - * @arg RTC_IT_TAMP: Tamper event interrupt mask - * @param NewState: new state of the specified RTC interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_RTC_CONFIG_IT(RTC_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - if (NewState != DISABLE) - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE); - } - else - { - /* Configure the Interrupts in the RTC_CR register */ - RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE); - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE); - } - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/** - * @brief Checks whether the specified RTC flag is set or not. - * @param RTC_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg RTC_FLAG_RECALPF: RECALPF event flag. - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_INITF: Initialization mode flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @arg RTC_FLAG_INITS: Registers Configured flag - * @arg RTC_FLAG_SHPF: Shift operation pending flag. - * @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag - * @arg RTC_FLAG_ALRBWF: Alarm B Write flag - * @arg RTC_FLAG_ALRAWF: Alarm A write flag - * @retval The new state of RTC_FLAG (SET or RESET). - */ -FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) -{ - FlagStatus bitstatus = RESET; - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); - - /* Get all the flags */ - tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); - - /* Return the status of the flag */ - if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's pending flags. - * @param RTC_FLAG: specifies the RTC flag to clear. - * This parameter can be any combination of the following values: - * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag - * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag - * @arg RTC_FLAG_TSF: Time Stamp event flag - * @arg RTC_FLAG_WUTF: WakeUp Timer flag - * @arg RTC_FLAG_ALRBF: Alarm B flag - * @arg RTC_FLAG_ALRAF: Alarm A flag - * @arg RTC_FLAG_RSF: Registers Synchronized flag - * @retval None - */ -void RTC_ClearFlag(uint32_t RTC_FLAG) -{ - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); - - /* Clear the Flags in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Checks whether the specified RTC interrupt has occurred or not. - * @param RTC_IT: specifies the RTC interrupt source to check. - * This parameter can be one of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @arg RTC_IT_TAMP2: Tamper 2 event interrupt - * @retval The new state of RTC_IT (SET or RESET). - */ -ITStatus RTC_GetITStatus(uint32_t RTC_IT) -{ - ITStatus bitstatus = RESET; - uint32_t tmpreg = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_RTC_GET_IT(RTC_IT)); - - /* Get the TAMPER Interrupt enable bit and pending bit */ - tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE)); - - /* Get the Interrupt enable Status */ - enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)) | (tmpreg & (RTC_IT >> 16))); - - /* Get the Interrupt pending bit */ - tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4))); - - /* Get the status of the Interrupt */ - if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the RTC's interrupt pending bits. - * @param RTC_IT: specifies the RTC interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TS: Time Stamp interrupt - * @arg RTC_IT_WUT: WakeUp Timer interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_TAMP1: Tamper 1 event interrupt - * @arg RTC_IT_TAMP2: Tamper 2 event interrupt - * @retval None - */ -void RTC_ClearITPendingBit(uint32_t RTC_IT) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_RTC_CLEAR_IT(RTC_IT)); - - /* Get the RTC_ISR Interrupt pending bits mask */ - tmpreg = (uint32_t)(RTC_IT >> 4); - - /* Clear the interrupt pending bits in the RTC_ISR register */ - RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); -} - -/** - * @} - */ - -/** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value: Byte to be converted. - * @retval Converted byte - */ -static uint8_t RTC_ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - - while (Value >= 10) - { - bcdhigh++; - Value -= 10; - } - - return ((uint8_t)(bcdhigh << 4) | Value); -} - -/** - * @brief Convert from 2 digit BCD to Binary. - * @param Value: BCD value to be converted. - * @retval Converted word - */ -static uint8_t RTC_Bcd2ToByte(uint8_t Value) -{ - uint8_t tmp = 0; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c deleted file mode 100644 index 85ee039e8..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c +++ /dev/null @@ -1,1167 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sai.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial Audio Interface (SAI): - * + Initialization and Configuration - * + Data transfers functions - * + DMA transfers management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SAI1, ENABLE) for SAI1 - - (#) For each SAI Block A/B enable SCK, SD, FS and MCLK GPIO clocks - using RCC_AHB1PeriphClockCmd() function. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function. - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - -@@- If an external clock source is used then the I2S CKIN pin should be - also configured in Alternate function Push-pull pull-up mode. - - (#) The SAI clock can be generated from different clock source : - PLL I2S, PLL SAI or external clock source. - (++) The PLL I2S is configured using the following functions RCC_PLLI2SConfig(), - RCC_PLLI2SCmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY) and - RCC_SAIPLLI2SClkDivConfig() or; - - (++) The PLL SAI is configured using the following functions RCC_PLLSAIConfig(), - RCC_PLLSAICmd(ENABLE), RCC_GetFlagStatus(RCC_FLAG_PLLSAIRDY) and - RCC_SAIPLLSAIClkDivConfig()or; - - (++) External clock source is configured using the function - RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the - define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - - (#) Each SAI Block A or B has its own clock generator to make these two blocks - completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and - RCC_SAIBlockBCLKConfig() functions. - - (#) Each SAI Block A or B can be configured separately : - (++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge, - Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function. - In case of master mode, program the Master clock divider (MCKDIV) using - the following formula : - (+++) MCLK_x = SAI_CK_x / (MCKDIV * 2) with MCLK_x = 256 * FS - (+++) FS = SAI_CK_x / (MCKDIV * 2) * 256 - (+++) MCKDIV = SAI_CK_x / FS * 512 - (++) Program the Frame Length, Frame active Length, FS Definition, FS Polarity, - FS Offset using SAI_FrameInit() function. - (++) Program the Slot First Bit Offset, Slot Size, Slot Number, Slot Active - using SAI_SlotInit() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - SAI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SAI_DMACmd() function - - (#) Enable the SAI using the SAI_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) The SAI has some specific functions which can be useful depending - on the audio protocol selected. - (++) Enable Mute mode when the audio block is a transmitter using SAI_MuteModeCmd() - function and configure the value transmitted during mute using SAI_MuteValueConfig(). - (++) Detect the Mute mode when audio block is a receiver using SAI_MuteFrameCounterConfig(). - (++) Enable the MONO mode without any data preprocessing in memory when the number - of slot is equal to 2 using SAI_MonoModeConfig() function. - (++) Enable data companding algorithm (U law and A law) using SAI_CompandingModeConfig(). - (++) Choose the behavior of the SD line in output when an inactive slot is sent - on the data line using SAI_TRIStateConfig() function. - [..] - (@) In master TX mode: enabling the audio block immediately generates the bit clock - for the external slaves even if there is no data in the FIFO, However FS signal - generation is conditioned by the presence of data in the FIFO. - - (@) In master RX mode: enabling the audio block immediately generates the bit clock - and FS signal for the external slaves. - - (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: - (+@) First bit Offset <= (SLOT size - Data size) - (+@) Data size <= SLOT size - (+@) Number of SLOT x SLOT size = Frame length - (+@) The number of slots should be even when bit FSDEF in the SAI_xFRCR is set. - - @endverbatim - - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sai.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SAI - * @brief SAI driver modules - * @{ - */ -#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \ - defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \ - defined (STM32F413_423xx) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* *SAI registers Masks */ -#define CR1_CLEAR_MASK ((uint32_t)0xFF07C010) -#define FRCR_CLEAR_MASK ((uint32_t)0xFFF88000) -#define SLOTR_CLEAR_MASK ((uint32_t)0x0000F020) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SAI_Private_Functions - * @{ - */ - -/** @defgroup SAI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to initialize the SAI Audio - Block Mode, Audio Protocol, Data size, Synchronization between audio block, - Master clock Divider, Fifo threshold, Frame configuration, slot configuration, - Tristate mode, Companding mode and Mute mode. - [..] - The SAI_Init(), SAI_FrameInit() and SAI_SlotInit() functions follows the SAI Block - configuration procedures for Master mode and Slave mode (details for these procedures - are available in reference manual(RM0090). - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the SAIx peripheral registers to their default reset values. - * @param SAIx: To select the SAIx peripheral, where x can be the different instances - * - * @retval None - */ -void SAI_DeInit(SAI_TypeDef* SAIx) -{ - /* Check the parameters */ - assert_param(IS_SAI_PERIPH(SAIx)); - - if(SAIx == SAI1) - { - /* Enable SAI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE); - /* Release SAI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE); - } - else - { -#if defined(STM32F446xx) - if(SAIx == SAI2) - { - /* Enable SAI2 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, ENABLE); - /* Release SAI2 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, DISABLE); - } -#endif /* STM32F446xx */ - } -} - -/** - * @brief Initializes the SAI Block x peripheral according to the specified - * parameters in the SAI_InitStruct. - * - * @note SAI clock is generated from a specific output of the PLLSAI or a specific - * output of the PLLI2S or from an alternate function bypassing the PLL I2S. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that - * contains the configuration information for the specified SAI Block peripheral. - * @retval None - */ -void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block parameters */ - assert_param(IS_SAI_BLOCK_MODE(SAI_InitStruct->SAI_AudioMode)); - assert_param(IS_SAI_BLOCK_PROTOCOL(SAI_InitStruct->SAI_Protocol)); - assert_param(IS_SAI_BLOCK_DATASIZE(SAI_InitStruct->SAI_DataSize)); - assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit)); - assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing)); - assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro)); - assert_param(IS_SAI_BLOCK_SYNCEXT(SAI_InitStruct->SAI_SynchroExt)); - assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV)); - assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider)); - assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider)); - assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(SAI_InitStruct->SAI_FIFOThreshold)); - - /* SAI Block_x CR1 Configuration */ - /* Get the SAI Block_x CR1 value */ - tmpreg = SAI_Block_x->CR1; - /* Clear MODE, PRTCFG, DS, LSBFIRST, CKSTR, SYNCEN, OUTDRIV, NODIV, and MCKDIV bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SAI_Block_x: Audio mode, Protocol, Data Size, first transmitted bit, Clock strobing - edge, Synchronization mode, Output drive, Master Divider and FIFO level */ - /* Set MODE bits according to SAI_AudioMode value */ - /* Set PRTCFG bits according to SAI_Protocol value */ - /* Set DS bits according to SAI_DataSize value */ - /* Set LSBFIRST bit according to SAI_FirstBit value */ - /* Set CKSTR bit according to SAI_ClockStrobing value */ - /* Set SYNCEN bit according to SAI_Synchro value */ - /* Set OUTDRIV bit according to SAI_OUTDRIV value */ - /* Set NODIV bit according to SAI_NoDivider value */ - /* Set MCKDIV bits according to SAI_MasterDivider value */ - tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol | - SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit | - SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro | - SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider | - SAI_InitStruct->SAI_SynchroExt | (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20)); - /* Write to SAI_Block_x CR1 */ - SAI_Block_x->CR1 = tmpreg; - - /* SAI Block_x CR2 Configuration */ - /* Get the SAIBlock_x CR2 value */ - tmpreg = SAI_Block_x->CR2; - /* Clear FTH bits */ - tmpreg &= ~(SAI_xCR2_FTH); - /* Configure the FIFO Level */ - /* Set FTH bits according to SAI_FIFOThreshold value */ - tmpreg |= (uint32_t)(SAI_InitStruct->SAI_FIFOThreshold); - /* Write to SAI_Block_x CR2 */ - SAI_Block_x->CR2 = tmpreg; -} - -/** - * @brief Initializes the SAI Block Audio frame according to the specified - * parameters in the SAI_FrameInitStruct. - * - * @note this function has no meaning if the AC'97 or SPDIF audio protocol - * are selected. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FrameInitStruct: pointer to an SAI_FrameInitTypeDef structure that - * contains the configuration of audio frame for a specified SAI Block - * @retval None - */ -void SAI_FrameInit(SAI_Block_TypeDef* SAI_Block_x, SAI_FrameInitTypeDef* SAI_FrameInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block frame parameters */ - assert_param(IS_SAI_BLOCK_FRAME_LENGTH(SAI_FrameInitStruct->SAI_FrameLength)); - assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(SAI_FrameInitStruct->SAI_ActiveFrameLength)); - assert_param(IS_SAI_BLOCK_FS_DEFINITION(SAI_FrameInitStruct->SAI_FSDefinition)); - assert_param(IS_SAI_BLOCK_FS_POLARITY(SAI_FrameInitStruct->SAI_FSPolarity)); - assert_param(IS_SAI_BLOCK_FS_OFFSET(SAI_FrameInitStruct->SAI_FSOffset)); - - /* SAI Block_x FRCR Configuration */ - /* Get the SAI Block_x FRCR value */ - tmpreg = SAI_Block_x->FRCR; - /* Clear FRL, FSALL, FSDEF, FSPOL, FSOFF bits */ - tmpreg &= FRCR_CLEAR_MASK; - /* Configure SAI_Block_x Frame: Frame Length, Active Frame Length, Frame Synchronization - Definition, Frame Synchronization Polarity and Frame Synchronization Polarity */ - /* Set FRL bits according to SAI_FrameLength value */ - /* Set FSALL bits according to SAI_ActiveFrameLength value */ - /* Set FSDEF bit according to SAI_FSDefinition value */ - /* Set FSPOL bit according to SAI_FSPolarity value */ - /* Set FSOFF bit according to SAI_FSOffset value */ - tmpreg |= (uint32_t)((uint32_t)(SAI_FrameInitStruct->SAI_FrameLength - 1) | - SAI_FrameInitStruct->SAI_FSOffset | - SAI_FrameInitStruct->SAI_FSDefinition | - SAI_FrameInitStruct->SAI_FSPolarity | - (uint32_t)((SAI_FrameInitStruct->SAI_ActiveFrameLength - 1) << 8)); - - /* Write to SAI_Block_x FRCR */ - SAI_Block_x->FRCR = tmpreg; -} - -/** - * @brief Initializes the SAI Block audio Slot according to the specified - * parameters in the SAI_SlotInitStruct. - * - * @note this function has no meaning if the AC'97 or SPDIF audio protocol - * are selected. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_SlotInitStruct: pointer to an SAI_SlotInitTypeDef structure that - * contains the configuration of audio slot for a specified SAI Block - * @retval None - */ -void SAI_SlotInit(SAI_Block_TypeDef* SAI_Block_x, SAI_SlotInitTypeDef* SAI_SlotInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Check the SAI Block Slot parameters */ - assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(SAI_SlotInitStruct->SAI_FirstBitOffset)); - assert_param(IS_SAI_BLOCK_SLOT_SIZE(SAI_SlotInitStruct->SAI_SlotSize)); - assert_param(IS_SAI_BLOCK_SLOT_NUMBER(SAI_SlotInitStruct->SAI_SlotNumber)); - assert_param(IS_SAI_SLOT_ACTIVE(SAI_SlotInitStruct->SAI_SlotActive)); - - /* SAI Block_x SLOTR Configuration */ - /* Get the SAI Block_x SLOTR value */ - tmpreg = SAI_Block_x->SLOTR; - /* Clear FBOFF, SLOTSZ, NBSLOT, SLOTEN bits */ - tmpreg &= SLOTR_CLEAR_MASK; - /* Configure SAI_Block_x Slot: First bit offset, Slot size, Number of Slot in - audio frame and slots activated in audio frame */ - /* Set FBOFF bits according to SAI_FirstBitOffset value */ - /* Set SLOTSZ bits according to SAI_SlotSize value */ - /* Set NBSLOT bits according to SAI_SlotNumber value */ - /* Set SLOTEN bits according to SAI_SlotActive value */ - tmpreg |= (uint32_t)(SAI_SlotInitStruct->SAI_FirstBitOffset | - SAI_SlotInitStruct->SAI_SlotSize | - SAI_SlotInitStruct->SAI_SlotActive | - (uint32_t)((SAI_SlotInitStruct->SAI_SlotNumber - 1) << 8)); - - /* Write to SAI_Block_x SLOTR */ - SAI_Block_x->SLOTR = tmpreg; -} - -/** - * @brief Fills each SAI_InitStruct member with its default value. - * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct) -{ - /* Reset SAI init structure parameters values */ - /* Initialize the SAI_AudioMode member */ - SAI_InitStruct->SAI_AudioMode = SAI_Mode_MasterTx; - /* Initialize the SAI_Protocol member */ - SAI_InitStruct->SAI_Protocol = SAI_Free_Protocol; - /* Initialize the SAI_DataSize member */ - SAI_InitStruct->SAI_DataSize = SAI_DataSize_8b; - /* Initialize the SAI_FirstBit member */ - SAI_InitStruct->SAI_FirstBit = SAI_FirstBit_MSB; - /* Initialize the SAI_ClockStrobing member */ - SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge; - /* Initialize the SAI_Synchro member */ - SAI_InitStruct->SAI_Synchro = SAI_Asynchronous; - /* Initialize the SAI_SynchroExt member */ - SAI_InitStruct->SAI_SynchroExt = SAI_SyncExt_Disable; - /* Initialize the SAI_OUTDRIV member */ - SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled; - /* Initialize the SAI_NoDivider member */ - SAI_InitStruct->SAI_NoDivider = SAI_MasterDivider_Enabled; - /* Initialize the SAI_MasterDivider member */ - SAI_InitStruct->SAI_MasterDivider = 0; - /* Initialize the SAI_FIFOThreshold member */ - SAI_InitStruct->SAI_FIFOThreshold = SAI_Threshold_FIFOEmpty; -} - -/** - * @brief Fills each SAI_FrameInitStruct member with its default value. - * @param SAI_FrameInitStruct: pointer to a SAI_FrameInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SAI_FrameStructInit(SAI_FrameInitTypeDef* SAI_FrameInitStruct) -{ - /* Reset SAI Frame init structure parameters values */ - /* Initialize the SAI_FrameLength member */ - SAI_FrameInitStruct->SAI_FrameLength = 8; - /* Initialize the SAI_ActiveFrameLength member */ - SAI_FrameInitStruct->SAI_ActiveFrameLength = 1; - /* Initialize the SAI_FSDefinition member */ - SAI_FrameInitStruct->SAI_FSDefinition = SAI_FS_StartFrame; - /* Initialize the SAI_FSPolarity member */ - SAI_FrameInitStruct->SAI_FSPolarity = SAI_FS_ActiveLow; - /* Initialize the SAI_FSOffset member */ - SAI_FrameInitStruct->SAI_FSOffset = SAI_FS_FirstBit; -} - -/** - * @brief Fills each SAI_SlotInitStruct member with its default value. - * @param SAI_SlotInitStruct: pointer to a SAI_SlotInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SAI_SlotStructInit(SAI_SlotInitTypeDef* SAI_SlotInitStruct) -{ - /* Reset SAI Slot init structure parameters values */ - /* Initialize the SAI_FirstBitOffset member */ - SAI_SlotInitStruct->SAI_FirstBitOffset = 0; - /* Initialize the SAI_SlotSize member */ - SAI_SlotInitStruct->SAI_SlotSize = SAI_SlotSize_DataSize; - /* Initialize the SAI_SlotNumber member */ - SAI_SlotInitStruct->SAI_SlotNumber = 1; - /* Initialize the SAI_SlotActive member */ - SAI_SlotInitStruct->SAI_SlotActive = SAI_Slot_NotActive; - -} - -/** - * @brief Enables or disables the specified SAI Block peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the SAI_Block_x peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_Cmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SAI peripheral */ - SAI_Block_x->CR1 |= SAI_xCR1_SAIEN; - } - else - { - /* Disable the selected SAI peripheral */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_SAIEN); - } -} - -/** - * @brief Configures the mono mode for the selected SAI block. - * - * @note This function has a meaning only when the number of slot is equal to 2. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MonoMode: specifies the SAI block mono mode. - * This parameter can be one of the following values: - * @arg SAI_MonoMode : Set mono audio mode - * @arg SAI_StreoMode : Set streo audio mode - * @retval None - */ -void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoMode) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MONO_STREO_MODE(SAI_MonoMode)); - /* Clear MONO bit */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); - /* Set new Mono Mode value */ - SAI_Block_x->CR1 |= SAI_MonoMode; -} - -/** - * @brief Configures the TRIState management on data line for the selected SAI block. - * - * @note This function has a meaning only when the SAI block is configured in transmitter - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_TRIState: specifies the SAI block TRIState management. - * This parameter can be one of the following values: - * @arg SAI_Output_NotReleased : SD output line is still driven by the SAI. - * @arg SAI_Output_Released : SD output line is released (HI-Z) - * @retval None - */ -void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(SAI_TRIState)); - /* Clear MONO bit */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_MONO); - /* Set new Mono Mode value */ - SAI_Block_x->CR1 |= SAI_MonoMode; - -} - -/** - * @brief Configures the companding mode for the selected SAI block. - * - * @note The data expansion or data compression are determined by the state of - * SAI block selected (transmitter or receiver). - - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_CompandingMode: specifies the SAI block companding mode. - * This parameter can be one of the following values: - * @arg SAI_NoCompanding : no companding algorithm set - * @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation) - * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement representation) - * @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation) - * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement representation) - * @retval None - */ -void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_COMPANDING_MODE(SAI_CompandingMode)); - /* Clear Companding Mode bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_COMP); - /* Set new Companding Mode value */ - SAI_Block_x->CR2 |= SAI_CompandingMode; -} - -/** - * @brief Enables or disables the Mute mode for the selected SAI block. - * - * @note This function has a meaning only when the audio block is transmitter - * @note Mute mode is applied for an entire frame for all the valid slot - * It becomes active at the end of an audio frame when set somewhere in a frame. - * Mute mode exit occurs at the end of the frame in which the bit MUTE has been set. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the SAIx block. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SAI block mute mode */ - SAI_Block_x->CR2 |= SAI_xCR2_MUTE; - } - else - { - /* Disable the selected SAI SS output */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTE); - } -} - -/** - * @brief Configure the mute value for the selected SAI block. - * - * @note This function has a meaning only when the audio block is transmitter - * @note the configuration last value sent during mute mode has only a meaning - * when the number of slot is lower or equal to 2 and if the MUTE bit is set. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MuteValue: specifies the SAI block mute value. - * This parameter can be one of the following values: - * @arg SAI_ZeroValue : bit value 0 is sent during Mute Mode - * @arg SAI_LastSentValue : Last value is sent during Mute Mode - * @retval None - */ -void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MUTE_VALUE(SAI_MuteValue)); - - /* Clear Mute value bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTEVAL); - /* Set new Mute value */ - SAI_Block_x->CR2 |= SAI_MuteValue; -} - -/** - * @brief Enables or disables the Mute mode for the selected SAI block. - * - * @note This function has a meaning only when the audio block is Receiver - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_MuteCounter: specifies the SAI block mute value. - * This parameter can be a number between 0 and 63. - - * @retval None - */ -void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_MUTE_COUNTER(SAI_MuteCounter)); - - /* Clear Mute value bits */ - SAI_Block_x->CR2 &= ~(SAI_xCR2_MUTECNT); - /* Set new Mute value */ - SAI_Block_x->CR2 |= (SAI_MuteCounter << 7); -} -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx) -/** - * @brief Configure SAI Block synchronization mode - * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that - * contains the configuration information for the specified SAI Block peripheral. - * @param SAIx: To select the SAIx peripheral, where x can be the different instances - * @retval None - */ -void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx) -{ - uint32_t tmpregisterGCR = 0U; - -#if defined(STM32F446xx) - /* This setting must be done with both audio block (A & B) disabled */ - switch(SAI_InitStruct->SAI_SynchroExt) - { - case SAI_SyncExt_Disable : - tmpregisterGCR = 0U; - break; - case SAI_SyncExt_OutBlockA_Enable : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SyncExt_OutBlockB_Enable : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default: - break; - } - - if(((SAI_InitStruct->SAI_Synchro) == SAI_Synchronous_Ext) && (SAIx == SAI1)) - { - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } - - if(SAIx == SAI1) - { - SAI1->GCR = tmpregisterGCR; - } - else - { - SAI2->GCR = tmpregisterGCR; - } - -#endif /* STM32F446xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F469_479xx) || defined(STM32F413_423xx) - /* This setting must be done with both audio block (A & B) disabled */ - switch(SAI_InitStruct->SAI_SynchroExt) - { - case SAI_SyncExt_Disable : - tmpregisterGCR = 0U; - break; - case SAI_SyncExt_OutBlockA_Enable : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SyncExt_OutBlockB_Enable : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default: - break; - } - SAI1->GCR = tmpregisterGCR; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx */ -} -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */ - -/** - * @brief Reinitialize the FIFO pointer - * - * @note The FIFO pointers can be reinitialized at anytime The data present - * into the FIFO, if it is not empty, will be lost. - * - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the selected SAI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* FIFO flush */ - SAI_Block_x->CR2 |= SAI_xCR2_FFLUSH; -} - -/** - * @} - */ - -/** @defgroup SAI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to manage the SAI data transfers. - [..] - In reception, data are received and then stored into an internal FIFO while - In transmission, data are first stored into an internal FIFO before being - transmitted. - [..] - The read access of the SAI_xDR register can be done using the SAI_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SAI_DR - can be done using SAI_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SAI block x peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @retval The value of the received data. - */ -uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Return the data in the DR register */ - return SAI_Block_x->DR; -} - -/** - * @brief Transmits a Data through the SAI block x peripheral. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @param Data: Data to be transmitted. - * @retval None - */ -void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Write in the DR register the data to be sent */ - SAI_Block_x->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SAI_Group3 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SAI Block x DMA interface. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param NewState: new state of the selected SAI block DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SAI block mute mode */ - SAI_Block_x->CR1 |= SAI_xCR1_DMAEN; - } - else - { - /* Disable the selected SAI SS output */ - SAI_Block_x->CR1 &= ~(SAI_xCR1_DMAEN); - } -} - -/** - * @} - */ - -/** @defgroup SAI_Group4 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This section provides a set of functions allowing to configure the SAI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] - In Polling Mode, the SAI communication can be managed by 7 flags: - (#) SAI_FLAG_FREQ : to indicate if there is a FIFO Request to write or to read. - (#) SAI_FLAG_MUTEDET : to indicate if a MUTE frame detected - (#) SAI_FLAG_OVRUDR : to indicate if an Overrun or Underrun error occur - (#) SAI_FLAG_AFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) earlier than expected - (#) SAI_FLAG_LFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) later than expected - (#) SAI_FLAG_CNRDY : to indicate if the codec is not ready to communicate during - the reception of the TAG 0 (slot0) of the AC97 audio frame - (#) SAI_FLAG_WCKCFG: to indicate if wrong clock configuration in master mode - error occurs. - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); - (+) void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - In Interrupt Mode, the SAI communication can be managed by 7 interrupt sources - and 7 pending bits: - (+) Pending Bits: - (##) SAI_IT_FREQ : to indicate if there is a FIFO Request to write or to read. - (##) SAI_IT_MUTEDET : to indicate if a MUTE frame detected. - (##) SAI_IT_OVRUDR : to indicate if an Overrun or Underrun error occur. - (##) SAI_IT_AFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) earlier than expected. - (##) SAI_IT_LFSDET : to indicate if there is the detection of a audio frame - synchronisation (FS) later than expected. - (##) SAI_IT_CNRDY : to indicate if the codec is not ready to communicate during - the reception of the TAG 0 (slot0) of the AC97 audio frame. - (##) SAI_IT_WCKCFG: to indicate if wrong clock configuration in master mode - error occurs. - - (+) Interrupt Source: - (##) SAI_IT_FREQ : specifies the interrupt source for FIFO Request. - (##) SAI_IT_MUTEDET : specifies the interrupt source for MUTE frame detected. - (##) SAI_IT_OVRUDR : specifies the interrupt source for overrun or underrun error. - (##) SAI_IT_AFSDET : specifies the interrupt source for anticipated frame synchronization - detection interrupt. - (##) SAI_IT_LFSDET : specifies the interrupt source for late frame synchronization - detection interrupt. - (##) SAI_IT_CNRDY : specifies the interrupt source for codec not ready interrupt - (##) SAI_IT_WCKCFG: specifies the interrupt source for wrong clock configuration - interrupt. - [..] - In this Mode it is advised to use the following functions: - (+) void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState); - (+) ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); - (+) void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT); - - *** DMA Mode *** - ================ - [..] - In DMA Mode, each SAI audio block has an independent DMA interface in order to - read or to write into the SAI_xDR register (to hit the internal FIFO). - There is one DMA channel by audio block following basic DMA request/acknowledge - protocol. - [..] - In this Mode it is advised to use the following function: - (+) void SAI_DMACmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState); - [..] - This section provides also functions allowing to - (+) Check the SAI Block enable status - (+)Check the FIFO status - - *** SAI Block Enable status *** - =============================== - [..] - After disabling a SAI Block, it is recommended to check (or wait until) the SAI Block - is effectively disabled. If a Block is disabled while an audio frame transfer is ongoing - the current frame will be transferred and the block will be effectively disabled only at - the end of audio frame. - To monitor this state it is possible to use the following function: - (+) FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x); - - *** SAI Block FIFO status *** - ============================= - [..] - It is possible to monitor the FIFO status when a transfer is ongoing using the following - function: - (+) uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SAI Block interrupts. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SAI_IT_FREQ: FIFO Request interrupt mask - * @arg SAI_IT_MUTEDET: MUTE detection interrupt mask - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt mask - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection - * interrupt mask - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt - * mask - * @arg SAI_IT_CNRDY: codec not ready interrupt mask - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt mask - * @param NewState: new state of the specified SAI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SAI_ITConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - if (NewState != DISABLE) - { - /* Enable the selected SAI Block interrupt */ - SAI_Block_x->IMR |= SAI_IT; - } - else - { - /* Disable the selected SAI Block interrupt */ - SAI_Block_x->IMR &= ~(SAI_IT); - } -} - -/** - * @brief Checks whether the specified SAI block x flag is set or not. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FLAG: specifies the SAI block flag to check. - * This parameter can be one of the following values: - * @arg SAI_FLAG_FREQ: FIFO Request flag. - * @arg SAI_FLAG_MUTEDET: MUTE detection flag. - * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. - * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. - * @arg SAI_FLAG_CNRDY: codec not ready flag. - * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. - * @retval The new state of SAI_FLAG (SET or RESET). - */ -FlagStatus SAI_GetFlagStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_GET_FLAG(SAI_FLAG)); - - /* Check the status of the specified SAI flag */ - if ((SAI_Block_x->SR & SAI_FLAG) != (uint32_t)RESET) - { - /* SAI_FLAG is set */ - bitstatus = SET; - } - else - { - /* SAI_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SAI_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the specified SAI Block x flag. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_FLAG: specifies the SAI block flag to check. - * This parameter can be one of the following values: - * @arg SAI_FLAG_MUTEDET: MUTE detection flag. - * @arg SAI_FLAG_OVRUDR: overrun/underrun flag. - * @arg SAI_FLAG_WCKCFG: wrong clock configuration flag. - * @arg SAI_FLAG_CNRDY: codec not ready flag. - * @arg SAI_FLAG_AFSDET: anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: late frame synchronization detection flag. - * - * @note FREQ (FIFO Request) flag is cleared : - * - When the audio block is transmitter and the FIFO is full or the FIFO - * has one data (one buffer mode) depending the bit FTH in the - * SAI_xCR2 register. - * - When the audio block is receiver and the FIFO is not empty - * - * @retval None - */ -void SAI_ClearFlag(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CLEAR_FLAG(SAI_FLAG)); - - /* Clear the selected SAI Block flag */ - SAI_Block_x->CLRFR |= SAI_FLAG; -} - -/** - * @brief Checks whether the specified SAI Block x interrupt has occurred or not. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SAI_IT_FREQ: FIFO Request interrupt - * @arg SAI_IT_MUTEDET: MUTE detection interrupt - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt - * @arg SAI_IT_CNRDY: codec not ready interrupt - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt - * - * @retval The new state of SAI_IT (SET or RESET). - */ -ITStatus SAI_GetITStatus(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) -{ - ITStatus bitstatus = RESET; - uint32_t enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - /* Get the SAI_IT enable bit status */ - enablestatus = (SAI_Block_x->IMR & SAI_IT) ; - - /* Check the status of the specified SAI interrupt */ - if (((SAI_Block_x->SR & SAI_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) - { - /* SAI_IT is set */ - bitstatus = SET; - } - else - { - /* SAI_IT is reset */ - bitstatus = RESET; - } - /* Return the SAI_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SAI Block x interrupt pending bit. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * @param SAI_IT: specifies the SAI Block interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg SAI_IT_MUTEDET: MUTE detection interrupt. - * @arg SAI_IT_OVRUDR: overrun/underrun interrupt. - * @arg SAI_IT_WCKCFG: wrong clock configuration interrupt. - * @arg SAI_IT_CNRDY: codec not ready interrupt. - * @arg SAI_IT_AFSDET: anticipated frame synchronization detection interrupt. - * @arg SAI_IT_LFSDET: late frame synchronization detection interrupt. - * - * @note FREQ (FIFO Request) flag is cleared : - * - When the audio block is transmitter and the FIFO is full or the FIFO - * has one data (one buffer mode) depending the bit FTH in the - * SAI_xCR2 register. - * - When the audio block is receiver and the FIFO is not empty - * - * @retval None - */ -void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT) -{ - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - assert_param(IS_SAI_BLOCK_CONFIG_IT(SAI_IT)); - - /* Clear the selected SAI Block x interrupt pending bit */ - SAI_Block_x->CLRFR |= SAI_IT; -} - -/** - * @brief Returns the status of EN bit for the specified SAI Block x. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @note After disabling a SAI Block, it is recommended to check (or wait until) - * the SAI Block is effectively disabled. If a Block is disabled while - * an audio frame transfer is ongoing, the current frame will be - * transferred and the block will be effectively disabled only at - * the end of audio frame. - * - * @retval Current state of the DMAy Streamx (ENABLE or DISABLE). - */ -FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x) -{ - FunctionalState state = DISABLE; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - if ((SAI_Block_x->CR1 & (uint32_t)SAI_xCR1_SAIEN) != 0) - { - /* The selected SAI Block x EN bit is set (audio frame transfer is ongoing) */ - state = ENABLE; - } - else - { - /* The selected SAI Block x EN bit is cleared (SAI Block is disabled and - all transfers are complete) */ - state = DISABLE; - } - return state; -} - -/** - * @brief Returns the current SAI Block x FIFO filled level. - * @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral. - * - * @retval The FIFO filling state. - * - SAI_FIFOStatus_Empty: when FIFO is empty - * - SAI_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - SAI_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - SAI_FIFOStatus_HalfFull: if more than 1 half-full. - * - SAI_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - SAI_FIFOStatus_Full: when FIFO is full - */ -uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SAI_BLOCK_PERIPH(SAI_Block_x)); - - /* Get the FIFO level bits */ - tmpreg = (uint32_t)((SAI_Block_x->SR & SAI_xSR_FLVL)); - - return tmpreg; -} - - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c deleted file mode 100644 index ec4faff45..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c +++ /dev/null @@ -1,1011 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_sdio.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Secure digital input/output interface (SDIO) - * peripheral: - * + Initialization and Configuration - * + Command path state machine (CPSM) management - * + Data path state machine (DPSM) management - * + SDIO IO Cards mode management - * + CE-ATA mode management - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL - (PLL48CLK). Before to start working with SDIO peripheral make sure that the - PLL is well configured. - The SDIO peripheral uses two clock signals: - (++) SDIO adapter clock (SDIOCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)) - - (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE). - - (#) According to the SDIO mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. - The I/O can be one of the following configurations: - (++) 1-bit data length: SDIO_CMD, SDIO_CK and D0. - (++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0]. - (++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0]. - - (#) Peripheral alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, - hardware, flow control and the Clock Divider using the SDIO_Init() - function. - - (#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) - function. - - (#) Enable the clock using the SDIO_ClockCmd() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - SDIO_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SDIO_DMACmd() function - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - (#) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDIO_SendCommand(), - SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has - to fill the command structure (pointer to SDIO_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDIO_CMDRESP - register using the SDIO_GetCommandResponse(). - The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the - SDIO_GetResponse() function. - - (#) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), - SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDIO) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to receive the data from the card - according to selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Read command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDIO_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDIO resources to send the data to the card according to - selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Write command (refer to step 11). - - (#) Use the SDIO flags/interrupts to check the transfer status. - - -@endverbatim - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_sdio.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SDIO - * @brief SDIO driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ------------ SDIO registers bit address in the alias region ----------- */ -#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) - -/* --- CLKCR Register ---*/ -/* Alias word address of CLKEN bit */ -#define CLKCR_OFFSET (SDIO_OFFSET + 0x04) -#define CLKEN_BitNumber 0x08 -#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) - -/* --- CMD Register ---*/ -/* Alias word address of SDIOSUSPEND bit */ -#define CMD_OFFSET (SDIO_OFFSET + 0x0C) -#define SDIOSUSPEND_BitNumber 0x0B -#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) - -/* Alias word address of ENCMDCOMPL bit */ -#define ENCMDCOMPL_BitNumber 0x0C -#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) - -/* Alias word address of NIEN bit */ -#define NIEN_BitNumber 0x0D -#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) - -/* Alias word address of ATACMD bit */ -#define ATACMD_BitNumber 0x0E -#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) - -/* --- DCTRL Register ---*/ -/* Alias word address of DMAEN bit */ -#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C) -#define DMAEN_BitNumber 0x03 -#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) - -/* Alias word address of RWSTART bit */ -#define RWSTART_BitNumber 0x08 -#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) - -/* Alias word address of RWSTOP bit */ -#define RWSTOP_BitNumber 0x09 -#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) - -/* Alias word address of RWMOD bit */ -#define RWMOD_BitNumber 0x0A -#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) - -/* Alias word address of SDIOEN bit */ -#define SDIOEN_BitNumber 0x0B -#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) - -/* ---------------------- SDIO registers bit mask ------------------------ */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) - -/* --- PWRCTRL Register ---*/ -/* SDIO PWRCTRL Mask */ -#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) - -/* --- DCTRL Register ---*/ -/* SDIO DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) - -/* SDIO RESP Registers Address */ -#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SDIO_Private_Functions - * @{ - */ - -/** @defgroup SDIO_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the SDIO peripheral registers to their default reset values. - * @param None - * @retval None - */ -void SDIO_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); -} - -/** - * @brief Initializes the SDIO peripheral according to the specified - * parameters in the SDIO_InitStruct. - * @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure - * that contains the configuration information for the SDIO peripheral. - * @retval None - */ -void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge)); - assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass)); - assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave)); - assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide)); - assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); - -/*---------------------------- SDIO CLKCR Configuration ------------------------*/ - /* Get the SDIO CLKCR value */ - tmpreg = SDIO->CLKCR; - - /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - tmpreg &= CLKCR_CLEAR_MASK; - - /* Set CLKDIV bits according to SDIO_ClockDiv value */ - /* Set PWRSAV bit according to SDIO_ClockPowerSave value */ - /* Set BYPASS bit according to SDIO_ClockBypass value */ - /* Set WIDBUS bits according to SDIO_BusWide value */ - /* Set NEGEDGE bits according to SDIO_ClockEdge value */ - /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */ - tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | - SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | - SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); - - /* Write to SDIO CLKCR */ - SDIO->CLKCR = tmpreg; -} - -/** - * @brief Fills each SDIO_InitStruct member with its default value. - * @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which - * will be initialized. - * @retval None - */ -void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct) -{ - /* SDIO_InitStruct members default value */ - SDIO_InitStruct->SDIO_ClockDiv = 0x00; - SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; - SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; - SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; - SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; - SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; -} - -/** - * @brief Enables or disables the SDIO Clock. - * @param NewState: new state of the SDIO Clock. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ClockCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState; -} - -/** - * @brief Sets the power status of the controller. - * @param SDIO_PowerState: new state of the Power state. - * This parameter can be one of the following values: - * @arg SDIO_PowerState_OFF: SDIO Power OFF - * @arg SDIO_PowerState_ON: SDIO Power ON - * @retval None - */ -void SDIO_SetPowerState(uint32_t SDIO_PowerState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState)); - - SDIO->POWER = SDIO_PowerState; -} - -/** - * @brief Gets the power status of the controller. - * @param None - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDIO_GetPowerState(void) -{ - return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions - * @brief Command path state machine (CPSM) management functions - * -@verbatim - =============================================================================== - ##### Command path state machine (CPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Command path - state machine (CPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO Command according to the specified - * parameters in the SDIO_CmdInitStruct and send the command. - * @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef - * structure that contains the configuration information for the SDIO - * command. - * @retval None - */ -void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex)); - assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response)); - assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait)); - assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM)); - -/*---------------------------- SDIO ARG Configuration ------------------------*/ - /* Set the SDIO Argument value */ - SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; - -/*---------------------------- SDIO CMD Configuration ------------------------*/ - /* Get the SDIO CMD value */ - tmpreg = SDIO->CMD; - /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */ - tmpreg &= CMD_CLEAR_MASK; - /* Set CMDINDEX bits according to SDIO_CmdIndex value */ - /* Set WAITRESP bits according to SDIO_Response value */ - /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */ - /* Set CPSMEN bits according to SDIO_CPSM value */ - tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response - | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; - - /* Write to SDIO CMD */ - SDIO->CMD = tmpreg; -} - -/** - * @brief Fills each SDIO_CmdInitStruct member with its default value. - * @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef - * structure which will be initialized. - * @retval None - */ -void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct) -{ - /* SDIO_CmdInitStruct members default value */ - SDIO_CmdInitStruct->SDIO_Argument = 0x00; - SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; - SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; - SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; - SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; -} - -/** - * @brief Returns command index of last command for which response received. - * @param None - * @retval Returns the command index of the last command response received. - */ -uint8_t SDIO_GetCommandResponse(void) -{ - return (uint8_t)(SDIO->RESPCMD); -} - -/** - * @brief Returns response received from the card for the last command. - * @param SDIO_RESP: Specifies the SDIO response register. - * This parameter can be one of the following values: - * @arg SDIO_RESP1: Response Register 1 - * @arg SDIO_RESP2: Response Register 2 - * @arg SDIO_RESP3: Response Register 3 - * @arg SDIO_RESP4: Response Register 4 - * @retval The Corresponding response register value. - */ -uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_RESP(SDIO_RESP)); - - tmp = SDIO_RESP_ADDR + SDIO_RESP; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @} - */ - -/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions - * @brief Data path state machine (DPSM) management functions - * -@verbatim - =============================================================================== - ##### Data path state machine (DPSM) management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the Data path - state machine (DPSM). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDIO data path according to the specified - * parameters in the SDIO_DataInitStruct. - * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure - * that contains the configuration information for the SDIO command. - * @retval None - */ -void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength)); - assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize)); - assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir)); - assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode)); - assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM)); - -/*---------------------------- SDIO DTIMER Configuration ---------------------*/ - /* Set the SDIO Data TimeOut value */ - SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; - -/*---------------------------- SDIO DLEN Configuration -----------------------*/ - /* Set the SDIO DataLength value */ - SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; - -/*---------------------------- SDIO DCTRL Configuration ----------------------*/ - /* Get the SDIO DCTRL value */ - tmpreg = SDIO->DCTRL; - /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */ - tmpreg &= DCTRL_CLEAR_MASK; - /* Set DEN bit according to SDIO_DPSM value */ - /* Set DTMODE bit according to SDIO_TransferMode value */ - /* Set DTDIR bit according to SDIO_TransferDir value */ - /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */ - tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir - | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; - - /* Write to SDIO DCTRL */ - SDIO->DCTRL = tmpreg; -} - -/** - * @brief Fills each SDIO_DataInitStruct member with its default value. - * @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure - * which will be initialized. - * @retval None - */ -void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct) -{ - /* SDIO_DataInitStruct members default value */ - SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; - SDIO_DataInitStruct->SDIO_DataLength = 0x00; - SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; - SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; - SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; - SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param None - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDIO_GetDataCounter(void) -{ - return SDIO->DCOUNT; -} - -/** - * @brief Read one data word from Rx FIFO. - * @param None - * @retval Data received - */ -uint32_t SDIO_ReadData(void) -{ - return SDIO->FIFO; -} - -/** - * @brief Write one data word to Tx FIFO. - * @param Data: 32-bit data word to write. - * @retval None - */ -void SDIO_WriteData(uint32_t Data) -{ - SDIO->FIFO = Data; -} - -/** - * @brief Returns the number of words left to be written to or read from FIFO. - * @param None - * @retval Remaining number of words. - */ -uint32_t SDIO_GetFIFOCount(void) -{ - return SDIO->FIFOCNT; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions - * @brief SDIO IO Cards mode management functions - * -@verbatim - =============================================================================== - ##### SDIO IO Cards mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the SDIO IO Cards. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the SD I/O Read Wait operation. - * @param NewState: new state of the Start SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StartSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState; -} - -/** - * @brief Stops the SD I/O Read Wait operation. - * @param NewState: new state of the Stop SDIO Read Wait operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_StopSDIOReadWait(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState; -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode. - * This parameter can be: - * @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK - * @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2 - * @retval None - */ -void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode)); - - *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode; -} - -/** - * @brief Enables or disables the SD I/O Mode Operation. - * @param NewState: new state of SDIO specific operation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SetSDIOOperation(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the SD I/O Mode suspend command sending. - * @param NewState: new state of the SD I/O Mode suspend command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group5 CE-ATA mode management functions - * @brief CE-ATA mode management functions - * -@verbatim - =============================================================================== - ##### CE-ATA mode management functions ##### - =============================================================================== - - This section provide functions allowing to program and read the CE-ATA card. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the command completion signal. - * @param NewState: new state of command completion signal. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CommandCompletionCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState; -} - -/** - * @brief Enables or disables the CE-ATA interrupt. - * @param NewState: new state of CE-ATA interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_CEATAITCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); -} - -/** - * @brief Sends CE-ATA command (CMD61). - * @param NewState: new state of CE-ATA command. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_SendCEATACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group6 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - - This section provide functions allowing to program SDIO DMA transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO DMA request. - * @param NewState: new state of the selected SDIO DMA request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_DMACmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState; -} - -/** - * @} - */ - -/** @defgroup SDIO_Group7 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SDIO interrupts. - * @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @param NewState: new state of the specified SDIO interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SDIO_IT(SDIO_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the SDIO interrupts */ - SDIO->MASK |= SDIO_IT; - } - else - { - /* Disable the SDIO interrupts */ - SDIO->MASK &= ~SDIO_IT; - } -} - -/** - * @brief Checks whether the specified SDIO flag is set or not. - * @param SDIO_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode. - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_CMDACT: Command transfer in progress - * @arg SDIO_FLAG_TXACT: Data transmit in progress - * @arg SDIO_FLAG_RXACT: Data receive in progress - * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full - * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval The new state of SDIO_FLAG (SET or RESET). - */ -FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) -{ - FlagStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_FLAG(SDIO_FLAG)); - - if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's pending flags. - * @param SDIO_FLAG: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDIO_FLAG_CTIMEOUT: Command response timeout - * @arg SDIO_FLAG_DTIMEOUT: Data timeout - * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) - * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) - * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode - * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received - * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearFlag(uint32_t SDIO_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG)); - - SDIO->ICR = SDIO_FLAG; -} - -/** - * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param SDIO_IT: specifies the SDIO interrupt source to check. - * This parameter can be one of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt - * @arg SDIO_IT_TXACT: Data transmit in progress interrupt - * @arg SDIO_IT_RXACT: Data receive in progress interrupt - * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt - * @retval The new state of SDIO_IT (SET or RESET). - */ -ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) -{ - ITStatus bitstatus = RESET; - - /* Check the parameters */ - assert_param(IS_SDIO_GET_IT(SDIO_IT)); - if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the SDIO's interrupt pending bits. - * @param SDIO_IT: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt - * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt - * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide - * bus mode interrupt - * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt - * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 - * @retval None - */ -void SDIO_ClearITPendingBit(uint32_t SDIO_IT) -{ - /* Check the parameters */ - assert_param(IS_SDIO_CLEAR_IT(SDIO_IT)); - - SDIO->ICR = SDIO_IT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c deleted file mode 100644 index 523e220b5..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c +++ /dev/null @@ -1,1327 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_spi.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Serial peripheral interface (SPI): - * + Initialization and Configuration - * + Data transfers functions - * + Hardware CRC Calculation - * + DMA transfers management - * + Interrupts and flags management - * -@verbatim - - =================================================================== - ##### How to use this driver ##### - =================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI4 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI5 - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI6. - - (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd() - function. In I2S mode, if an external clock source is used then the I2S - CKIN pin GPIO clock should also be enabled. - - (#) Peripherals alternate function: - (++) Connect the pin to the desired peripherals' Alternate Function (AF) - using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via GPIO_PuPd, - GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function In I2S mode, if an external clock source is - used then the I2S CKIN pin should be also configured in Alternate - function Push-pull pull-up mode. - - (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave - Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio - frequency and Polarity using I2S_Init() function. For I2S mode, make sure - that either: - (++) I2S PLL is configured using the functions - RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), RCC_PLLI2SCmd(ENABLE) and - RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY); or - (++) External clock source is configured using the function - RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly - the define constant I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. - - (#) Enable the NVIC and the corresponding interrupt using the function - SPI_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using SPI_I2S_DMACmd() function - - (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using - I2S_Cmd(). - - (#) Enable the DMA using the DMA_Cmd() function when using DMA mode. - - (#) Optionally, you can enable/configure the following parameters without - re-initialization (i.e there is no need to call again SPI_Init() function): - (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx) - is programmed as Data direction parameter using the SPI_Init() function - it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx - using the SPI_BiDirectionalLineConfig() function. - (++) When SPI_NSS_Soft is selected as Slave Select Management parameter - using the SPI_Init() function it can be possible to manage the - NSS internal signal using the SPI_NSSInternalSoftwareConfig() function. - (++) Reconfigure the data size using the SPI_DataSizeConfig() function - (++) Enable or disable the SS output using the SPI_SSOutputCmd() function - - (#) To use the CRC Hardware calculation feature refer to the Peripheral - CRC hardware Calculation subsection. - - - [..] It is possible to use SPI in I2S full duplex mode, in this case, each SPI - peripheral is able to manage sending and receiving data simultaneously - using two data lines. Each SPI peripheral has an extended block called I2Sxext - (ie. I2S2ext for SPI2 and I2S3ext for SPI3). - The extension block is not a full SPI IP, it is used only as I2S slave to - implement full duplex mode. The extension block uses the same clock sources - as its master. - To configure I2S full duplex you have to: - - (#) Configure SPIx in I2S mode (I2S_Init() function) as described above. - - (#) Call the I2S_FullDuplexConfig() function using the same structure passed to - I2S_Init() function. - - (#) Call I2S_Cmd() for SPIx then for its extended block. - - (#) To configure interrupts or DMA requests and to get/clear flag status, - use I2Sxext instance for the extension block. - - [..] Functions that can be called with I2Sxext instances are: I2S_Cmd(), - I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), - SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), - SPI_I2S_ClearFlag(), SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit(). - - Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx): - - RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE); - I2S_StructInit(&I2SInitStruct); - I2SInitStruct.Mode = I2S_Mode_MasterTx; - I2S_Init(SPI3, &I2SInitStruct); - I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct) - I2S_Cmd(SPI3, ENABLE); - I2S_Cmd(SPI3ext, ENABLE); - ... - while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET) - {} - SPI_I2S_SendData(SPI3, txdata[i]); - ... - while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET) - {} - rxdata[i] = SPI_I2S_ReceiveData(I2S3ext); - ... - - [..] - (@) In I2S mode: if an external clock is used as source clock for the I2S, - then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should - be enabled and set to the value of the source clock frequency (in Hz). - - (@) In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() - just after calling the function SPI_Init(). - -@endverbatim - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_spi.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SPI - * @brief SPI driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* SPI registers Masks */ -#define CR1_CLEAR_MASK ((uint16_t)0x3040) -#define I2SCFGR_CLEAR_MASK ((uint16_t)0xF040) - -/* RCC PLLs masks */ -#define PLLCFGR_PPLR_MASK ((uint32_t)0x70000000) -#define PLLCFGR_PPLN_MASK ((uint32_t)0x00007FC0) - -#define SPI_CR2_FRF ((uint16_t)0x0010) -#define SPI_SR_TIFRFE ((uint16_t)0x0100) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/** @defgroup SPI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides a set of functions allowing to initialize the SPI - Direction, SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS - Management, SPI Baud Rate Prescaler, SPI First Bit and SPI CRC Polynomial. - - [..] The SPI_Init() function follows the SPI configuration procedures for Master - mode and Slave mode (details for these procedures are available in reference - manual (RM0090)). - -@endverbatim - * @{ - */ - -/** - * @brief De-initialize the SPIx peripheral registers to their default reset values. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode. - * - * @note The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are de-initialized - * when the relative I2S peripheral is de-initialized (the extended block's clock - * is managed by the I2S peripheral clock). - * - * @retval None - */ -void SPI_I2S_DeInit(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - if (SPIx == SPI1) - { - /* Enable SPI1 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); - /* Release SPI1 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); - } - else if (SPIx == SPI2) - { - /* Enable SPI2 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); - /* Release SPI2 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); - } - else if (SPIx == SPI3) - { - /* Enable SPI3 reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); - /* Release SPI3 from reset state */ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); - } - else if (SPIx == SPI4) - { - /* Enable SPI4 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, ENABLE); - /* Release SPI4 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI4, DISABLE); - } - else if (SPIx == SPI5) - { - /* Enable SPI5 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, ENABLE); - /* Release SPI5 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI5, DISABLE); - } - else - { - if (SPIx == SPI6) - { - /* Enable SPI6 reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, ENABLE); - /* Release SPI6 from reset state */ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI6, DISABLE); - } - } -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the SPI_InitStruct. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral. - * @retval None - */ -void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) -{ - uint16_t tmpreg = 0; - - /* check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Check the SPI parameters */ - assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); - assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); - assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize)); - assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); - assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); - assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); - assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); - -/*---------------------------- SPIx CR1 Configuration ------------------------*/ - /* Get the SPIx CR1 value */ - tmpreg = SPIx->CR1; - /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */ - tmpreg &= CR1_CLEAR_MASK; - /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler - master/salve mode, CPOL and CPHA */ - /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ - /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */ - /* Set LSBFirst bit according to SPI_FirstBit value */ - /* Set BR bits according to SPI_BaudRatePrescaler value */ - /* Set CPOL bit according to SPI_CPOL value */ - /* Set CPHA bit according to SPI_CPHA value */ - tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | - SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | - SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | - SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); - /* Write to SPIx CR1 */ - SPIx->CR1 = tmpreg; - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); -/*---------------------------- SPIx CRCPOLY Configuration --------------------*/ - /* Write to SPIx CRCPOLY */ - SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; -} - -/** - * @brief Initializes the SPIx peripheral according to the specified - * parameters in the I2S_InitStruct. - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (configured in I2S mode). - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified SPI peripheral - * configured in I2S mode. - * - * @note The function calculates the optimal prescaler needed to obtain the most - * accurate audio frequency (depending on the I2S clock source, the PLL values - * and the product configuration). But in case the prescaler value is greater - * than 511, the default value (0x02) will be configured instead. - * - * @note if an external clock is used as source clock for the I2S, then the define - * I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set - * to the value of the source clock frequency (in Hz). - * - * @retval None - */ -void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; -#ifndef I2S_EXTERNAL_CLOCK_VAL - uint32_t pllm = 0, plln = 0, pllr = 0; -#endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Check the I2S parameters */ - assert_param(IS_SPI_23_PERIPH(SPIx)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; - SPIx->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = SPIx->I2SCFGR; - - /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ - if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) - { - i2sodd = (uint16_t)0; - i2sdiv = (uint16_t)2; - } - /* If the requested audio frequency is not the default, compute the prescaler */ - else - { - /* Check the frame length (For the Prescaler computing) *******************/ - if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) - { - /* Packet length is 16 bits */ - packetlength = 1; - } - else - { - /* Packet length is 32 bits */ - packetlength = 2; - } - - /* Get I2S source Clock frequency ****************************************/ - - /* If an external I2S clock has to be used, this define should be set - in the project configuration or in the stm32f4xx_conf.h file */ - #ifdef I2S_EXTERNAL_CLOCK_VAL - /* Set external clock as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0) - { - RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC; - } - - /* Set the I2S clock to the external clock value */ - i2sclk = I2S_EXTERNAL_CLOCK_VAL; - - #else /* There is no define for External I2S clock source */ - /* Set PLLI2S as I2S clock source */ - if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0) - { - RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC; - } - - /* Get the PLLI2SN value */ - plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \ - (RCC_PLLI2SCFGR_PLLI2SN >> 6)); - - /* Get the PLLI2SR value */ - pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \ - (RCC_PLLI2SCFGR_PLLI2SR >> 28)); - - /* Get the PLLM value */ - pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE) - { - /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr); - } - else - { /* Get the I2S source clock value */ - i2sclk = (uint32_t)(((HSI_VALUE / pllm) * plln) / pllr); - } - #endif /* I2S_EXTERNAL_CLOCK_VAL */ - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) - { - /* MCLK output is enabled */ - tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - else - { - /* MCLK output is disabled */ - tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5); - } - - /* Remove the flatting point */ - tmp = tmp / 10; - - /* Check the parity of the divider */ - i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint16_t)((tmp - i2sodd) / 2); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint16_t) (i2sodd << 8); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2) || (i2sdiv > 0xFF)) - { - /* Set the default values */ - i2sdiv = 2; - i2sodd = 0; - } - - /* Write to SPIx I2SPR register the computed value */ - SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - -#if defined(SPI_I2SCFGR_ASTRTEN) - if((I2S_InitStruct->I2S_Standard == I2S_Standard_PCMShort) || (I2S_InitStruct->I2S_Standard == I2S_Standard_PCMLong)) - { - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN; - } -#else - /* Write to SPIx I2SCFGR */ - SPIx->I2SCFGR = tmpreg ; -#endif -} - -/** - * @brief Fills each SPI_InitStruct member with its default value. - * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. - * @retval None - */ -void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) -{ -/*--------------- Reset SPI init structure parameters values -----------------*/ - /* Initialize the SPI_Direction member */ - SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; - /* initialize the SPI_Mode member */ - SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; - /* initialize the SPI_DataSize member */ - SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; - /* Initialize the SPI_CPOL member */ - SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; - /* Initialize the SPI_CPHA member */ - SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; - /* Initialize the SPI_NSS member */ - SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; - /* Initialize the SPI_BaudRatePrescaler member */ - SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; - /* Initialize the SPI_FirstBit member */ - SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; - /* Initialize the SPI_CRCPolynomial member */ - SPI_InitStruct->SPI_CRCPolynomial = 7; -} - -/** - * @brief Fills each I2S_InitStruct member with its default value. - * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized. - * @retval None - */ -void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) -{ -/*--------------- Reset I2S init structure parameters values -----------------*/ - /* Initialize the I2S_Mode member */ - I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; - - /* Initialize the I2S_Standard member */ - I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; - - /* Initialize the I2S_DataFormat member */ - I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; - - /* Initialize the I2S_MCLKOutput member */ - I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; - - /* Initialize the I2S_AudioFreq member */ - I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; - - /* Initialize the I2S_CPOL member */ - I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; -} - -/** - * @brief Enables or disables the specified SPI peripheral. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral */ - SPIx->CR1 |= SPI_CR1_SPE; - } - else - { - /* Disable the selected SPI peripheral */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); - } -} - -/** - * @brief Enables or disables the specified SPI peripheral (in I2S mode). - * @param SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext - * for full duplex mode). - * @param NewState: new state of the SPIx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_23_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI peripheral (in I2S mode) */ - SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE; - } - else - { - /* Disable the selected SPI peripheral in I2S mode */ - SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE); - } -} - -/** - * @brief Configures the data size for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_DataSize: specifies the SPI data size. - * This parameter can be one of the following values: - * @arg SPI_DataSize_16b: Set data frame format to 16bit - * @arg SPI_DataSize_8b: Set data frame format to 8bit - * @retval None - */ -void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DATASIZE(SPI_DataSize)); - /* Clear DFF bit */ - SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b; - /* Set new DFF bit value */ - SPIx->CR1 |= SPI_DataSize; -} - -/** - * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. - * This parameter can be one of the following values: - * @arg SPI_Direction_Tx: Selects Tx transmission direction - * @arg SPI_Direction_Rx: Selects Rx receive direction - * @retval None - */ -void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_DIRECTION(SPI_Direction)); - if (SPI_Direction == SPI_Direction_Tx) - { - /* Set the Tx only mode */ - SPIx->CR1 |= SPI_Direction_Tx; - } - else - { - /* Set the Rx only mode */ - SPIx->CR1 &= SPI_Direction_Rx; - } -} - -/** - * @brief Configures internally by software the NSS pin for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. - * This parameter can be one of the following values: - * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally - * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally - * @retval None - */ -void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); - if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) - { - /* Set NSS pin internally by software */ - SPIx->CR1 |= SPI_NSSInternalSoft_Set; - } - else - { - /* Reset NSS pin internally by software */ - SPIx->CR1 &= SPI_NSSInternalSoft_Reset; - } -} - -/** - * @brief Enables or disables the SS output for the selected SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx SS output. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI SS output */ - SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE; - } - else - { - /* Disable the selected SPI SS output */ - SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); - } -} - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * - * @note This function can be called only after the SPI_Init() function has - * been called. - * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA - * are not taken into consideration and are configured by hardware - * respectively to the TI mode requirements. - * - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 - * @param NewState: new state of the selected SPI TI communication mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TI mode for the selected SPI peripheral */ - SPIx->CR2 |= SPI_CR2_FRF; - } - else - { - /* Disable the TI mode for the selected SPI peripheral */ - SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF; - } -} - -/** - * @brief Configures the full duplex mode for the I2Sx peripheral using its - * extension I2Sxext according to the specified parameters in the - * I2S_InitStruct. - * @param I2Sxext: where x can be 2 or 3 to select the I2S peripheral extension block. - * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that - * contains the configuration information for the specified I2S peripheral - * extension. - * - * @note The structure pointed by I2S_InitStruct parameter should be the same - * used for the master I2S peripheral. In this case, if the master is - * configured as transmitter, the slave will be receiver and vice versa. - * Or you can force a different mode by modifying the field I2S_Mode to the - * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. - * - * @note The I2S full duplex extension can be configured in slave mode only. - * - * @retval None - */ -void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct) -{ - uint16_t tmpreg = 0, tmp = 0; - - /* Check the I2S parameters */ - assert_param(IS_I2S_EXT_PERIPH(I2Sxext)); - assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode)); - assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); - assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat)); - assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL)); - -/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; - I2Sxext->I2SPR = 0x0002; - - /* Get the I2SCFGR register value */ - tmpreg = I2Sxext->I2SCFGR; - - /* Get the mode to be configured for the extended I2S */ - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx)) - { - tmp = I2S_Mode_SlaveRx; - } - else - { - if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx)) - { - tmp = I2S_Mode_SlaveTx; - } - } - - - /* Configure the I2S with the SPI_InitStruct values */ - tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ - (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \ - (uint16_t)I2S_InitStruct->I2S_CPOL)))); - - /* Write to SPIx I2SCFGR */ - I2Sxext->I2SCFGR = tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI data - transfers. In reception, data are received and then stored into an internal - Rx buffer while. In transmission, data are first stored into an internal Tx - buffer before being transmitted. - - [..] The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData() - function and returns the Rx buffered value. Whereas a write access to the SPI_DR - can be done using SPI_I2S_SendData() function and stores the written data into - Tx buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @retval The value of the received data. - */ -uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Return the data in the DR register */ - return SPIx->DR; -} - -/** - * @brief Transmits a Data through the SPIx/I2Sx peripheral. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param Data: Data to be transmitted. - * @retval None - */ -void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - - /* Write in the DR register the data to be sent */ - SPIx->DR = Data; -} - -/** - * @} - */ - -/** @defgroup SPI_Group3 Hardware CRC Calculation functions - * @brief Hardware CRC Calculation functions - * -@verbatim - =============================================================================== - ##### Hardware CRC Calculation functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to manage the SPI CRC hardware - calculation - - [..] SPI communication using CRC is possible through the following procedure: - (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, - Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init() - function. - (#) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#) Enable the SPI using the SPI_Cmd() function - (#) Before writing the last data to the TX buffer, set the CRCNext bit using the - SPI_TransmitCRC() function to indicate that after transmission of the last - data, the CRC should be transmitted. - (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT - bit is reset. The CRC is also received and compared against the SPI_RXCRCR - value. - If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt - can be generated when the SPI_I2S_IT_ERR interrupt is enabled. - - [..] - (@) It is advised not to read the calculated CRC values during the communication. - - (@) When the SPI is in slave mode, be careful to enable CRC calculation only - when the clock is stable, that is, when the clock is in the steady state. - If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive - to the SCK slave input clock as soon as CRCEN is set, and this, whatever - the value of the SPE bit. - - (@) With high bitrate frequencies, be careful when transmitting the CRC. - As the number of used CPU cycles has to be as low as possible in the CRC - transfer phase, it is forbidden to call software functions in the CRC - transmission sequence to avoid errors in the last data and CRC reception. - In fact, CRCNEXT bit has to be written before the end of the transmission/reception - of the last data. - - (@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the - degradation of the SPI speed performance due to CPU accesses impacting the - SPI bandwidth. - - (@) When the STM32F4xx is configured as slave and the NSS hardware mode is - used, the NSS pin needs to be kept low between the data phase and the CRC - phase. - - (@) When the SPI is configured in slave mode with the CRC feature enabled, CRC - calculation takes place even if a high level is applied on the NSS pin. - This may happen for example in case of a multi-slave environment where the - communication master addresses slaves alternately. - - (@) Between a slave de-selection (high level on NSS) and a new slave selection - (low level on NSS), the CRC value should be cleared on both master and slave - sides in order to resynchronize the master and slave for their respective - CRC calculation. - - (@) To clear the CRC, follow the procedure below: - (#@) Disable SPI using the SPI_Cmd() function - (#@) Disable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable the CRC calculation using the SPI_CalculateCRC() function. - (#@) Enable SPI using the SPI_Cmd() function. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the CRC value calculation of the transferred bytes. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param NewState: new state of the SPIx CRC value calculation. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the selected SPI CRC calculation */ - SPIx->CR1 |= SPI_CR1_CRCEN; - } - else - { - /* Disable the selected SPI CRC calculation */ - SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); - } -} - -/** - * @brief Transmit the SPIx CRC value. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval None - */ -void SPI_TransmitCRC(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Enable the selected SPI CRC transmission */ - SPIx->CR1 |= SPI_CR1_CRCNEXT; -} - -/** - * @brief Returns the transmit or the receive CRC register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param SPI_CRC: specifies the CRC register to be read. - * This parameter can be one of the following values: - * @arg SPI_CRC_Tx: Selects Tx CRC register - * @arg SPI_CRC_Rx: Selects Rx CRC register - * @retval The selected CRC register value.. - */ -uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) -{ - uint16_t crcreg = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - assert_param(IS_SPI_CRC(SPI_CRC)); - if (SPI_CRC != SPI_CRC_Rx) - { - /* Get the Tx CRC register */ - crcreg = SPIx->TXCRCR; - } - else - { - /* Get the Rx CRC register */ - crcreg = SPIx->RXCRCR; - } - /* Return the selected CRC register */ - return crcreg; -} - -/** - * @brief Returns the CRC Polynomial register value for the specified SPI. - * @param SPIx: where x can be 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval The CRC Polynomial register value. - */ -uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH(SPIx)); - - /* Return the CRC polynomial register */ - return SPIx->CRCPR; -} - -/** - * @} - */ - -/** @defgroup SPI_Group4 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the SPIx/I2Sx DMA interface. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request - * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request - * @param NewState: new state of the selected SPI DMA transfer request. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq)); - - if (NewState != DISABLE) - { - /* Enable the selected SPI DMA requests */ - SPIx->CR2 |= SPI_I2S_DMAReq; - } - else - { - /* Disable the selected SPI DMA requests */ - SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup SPI_Group5 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - - [..] This section provides a set of functions allowing to configure the SPI Interrupts - sources and check or clear the flags or pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== -[..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags: - (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register - (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register - (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI. - (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur - (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur - (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur - (#) I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs. - (#) I2S_FLAG_UDR: to indicate an Underrun error occurs. - (#) I2S_FLAG_CHSIDE: to indicate Channel Side. - - (@) Do not use the BSY flag to handle each data transmission or reception. It is - better to use the TXE and RXNE flags instead. - - [..] In this Mode it is advised to use the following functions: - (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); - - *** Interrupt Mode *** - ====================== - [..] In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources - and 7 pending bits: - (+) Pending Bits: - (##) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register - (##) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register - (##) SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only) - (##) SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only) - (##) SPI_I2S_IT_OVR : to indicate if an Overrun error occur - (##) I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only). - (##) I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only). - - (+) Interrupt Source: - (##) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty - interrupt. - (##) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt. - - [..] In this Mode it is advised to use the following functions: - (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); - (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - (+) void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); - - *** DMA Mode *** - ================ - [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests: - (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request - - [..] In this Mode it is advised to use the following function: - (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState - NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified SPI/I2S interrupts. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask - * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask - * @arg SPI_I2S_IT_ERR: Error interrupt mask - * @param NewState: new state of the specified SPI interrupt. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) -{ - uint16_t itpos = 0, itmask = 0 ; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT)); - - /* Get the SPI IT index */ - itpos = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = (uint16_t)1 << (uint16_t)itpos; - - if (NewState != DISABLE) - { - /* Enable the selected SPI interrupt */ - SPIx->CR2 |= itmask; - } - else - { - /* Disable the selected SPI interrupt */ - SPIx->CR2 &= (uint16_t)~itmask; - } -} - -/** - * @brief Checks whether the specified SPIx/I2Sx flag is set or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag. - * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag. - * @arg SPI_I2S_FLAG_BSY: Busy flag. - * @arg SPI_I2S_FLAG_OVR: Overrun flag. - * @arg SPI_FLAG_MODF: Mode Fault flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * @arg SPI_I2S_FLAG_TIFRFE: Format Error. - * @arg I2S_FLAG_UDR: Underrun Error flag. - * @arg I2S_FLAG_CHSIDE: Channel Side flag. - * @retval The new state of SPI_I2S_FLAG (SET or RESET). - */ -FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG)); - - /* Check the status of the specified SPI flag */ - if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET) - { - /* SPI_I2S_FLAG is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_FLAG is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_FLAG status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) flag. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_FLAG: specifies the SPI flag to clear. - * This function clears only CRCERR flag. - * @arg SPI_FLAG_CRCERR: CRC Error flag. - * - * @note OVR (OverRun error) flag is cleared by software sequence: a read - * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note UDR (UnderRun error) flag is cleared by a read operation to - * SPI_SR register (SPI_I2S_GetFlagStatus()). - * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write - * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a - * write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). - * - * @retval None - */ -void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG) -{ - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG)); - - /* Clear the selected SPI CRC Error (CRCERR) flag */ - SPIx->SR = (uint16_t)~SPI_I2S_FLAG; -} - -/** - * @brief Checks whether the specified SPIx/I2Sx interrupt has occurred or not. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt. - * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt. - * @arg SPI_I2S_IT_OVR: Overrun interrupt. - * @arg SPI_IT_MODF: Mode Fault interrupt. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * @arg I2S_IT_UDR: Underrun interrupt. - * @arg SPI_I2S_IT_TIFRFE: Format Error interrupt. - * @retval The new state of SPI_I2S_IT (SET or RESET). - */ -ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itpos = 0, itmask = 0, enablestatus = 0; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S_IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Get the SPI_I2S_IT IT mask */ - itmask = SPI_I2S_IT >> 4; - - /* Set the IT mask */ - itmask = 0x01 << itmask; - - /* Get the SPI_I2S_IT enable bit status */ - enablestatus = (SPIx->CR2 & itmask) ; - - /* Check the status of the specified SPI interrupt */ - if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) - { - /* SPI_I2S_IT is set */ - bitstatus = SET; - } - else - { - /* SPI_I2S_IT is reset */ - bitstatus = RESET; - } - /* Return the SPI_I2S_IT status */ - return bitstatus; -} - -/** - * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. - * @param SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2, 3, 4, 5 or 6 - * in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. - * @param SPI_I2S_IT: specifies the SPI interrupt pending bit to clear. - * This function clears only CRCERR interrupt pending bit. - * @arg SPI_IT_CRCERR: CRC Error interrupt. - * - * @note OVR (OverRun Error) interrupt pending bit is cleared by software - * sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) - * followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note UDR (UnderRun Error) interrupt pending bit is cleared by a read - * operation to SPI_SR register (SPI_I2S_GetITStatus()). - * @note MODF (Mode Fault) interrupt pending bit is cleared by software sequence: - * a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) - * followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable - * the SPI). - * @retval None - */ -void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT) -{ - uint16_t itpos = 0; - /* Check the parameters */ - assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx)); - assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT)); - - /* Get the SPI_I2S IT index */ - itpos = 0x01 << (SPI_I2S_IT & 0x0F); - - /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */ - SPIx->SR = (uint16_t)~itpos; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c deleted file mode 100644 index 240c9fc88..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c +++ /dev/null @@ -1,521 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_syscfg.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the SYSCFG peripheral. - * - @verbatim - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] This driver provides functions for: - - (#) Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig() - - (#) Swapping the internal flash Bank1 and Bank2 this features is only visible for - STM32F42xxx/43xxx devices Devices. - - (#) Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig() - - (#) Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig() - - -@- SYSCFG APB clock must be enabled to get write access to SYSCFG registers, - using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_syscfg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup SYSCFG - * @brief SYSCFG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* ------------ RCC registers bit address in the alias region ----------- */ -#define SYSCFG_OFFSET (SYSCFG_BASE - PERIPH_BASE) -/* --- MEMRMP Register ---*/ -/* Alias word address of UFB_MODE bit */ -#define MEMRMP_OFFSET SYSCFG_OFFSET -#define UFB_MODE_BitNumber ((uint8_t)0x8) -#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4)) - -/* --- PMC Register ---*/ -/* Alias word address of MII_RMII_SEL bit */ -#define PMC_OFFSET (SYSCFG_OFFSET + 0x04) -#define MII_RMII_SEL_BitNumber ((uint8_t)0x17) -#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) - -/* --- CMPCR Register ---*/ -/* Alias word address of CMP_PD bit */ -#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20) -#define CMP_PD_BitNumber ((uint8_t)0x00) -#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) - -/* --- MCHDLYCR Register ---*/ -/* Alias word address of BSCKSEL bit */ -#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30) -#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL) -#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32) + (BSCKSEL_BIT_NUMBER * 4)) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Functions - * @{ - */ - -/** - * @brief Deinitializes the Alternate Functions (remap and EXTI configuration) - * registers to their default reset values. - * @param None - * @retval None - */ -void SYSCFG_DeInit(void) -{ - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE); -} - -/** - * @brief Changes the mapping of the specified pin. - * @param SYSCFG_Memory: selects the memory remapping. - * This parameter can be one of the following values: - * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx, STM32F415xx/417xx and STM32F413_423xx devices. - * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @arg SYSCFG_MemoryRemap_ExtMEM: External Memory mapped at 0x00000000 for STM32F446xx/STM32F469_479xx devices. - * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000 - * @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices. - * @retval None - */ -void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap)); - - SYSCFG->MEMRMP = SYSCFG_MemoryRemap; -} - -/** - * @brief Enables or disables the Internal FLASH Bank Swapping. - * - * @note This function can be used only for STM32F42xxx/43xxx devices. - * - * @param NewState: new state of Internal FLASH Bank swapping. - * This parameter can be one of the following values: - * @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) - * and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000) - * @arg DISABLE:(the default state) Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000) - and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) - * @retval None - */ -void SYSCFG_MemorySwappingBank(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) UFB_MODE_BB = (uint32_t)NewState; -} - -/** - * @brief Selects the GPIO pin used as EXTI Line. - * @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for - * EXTI lines where x can be (A..K) for STM32F42xxx/43xxx devices, (A..I) - * for STM32F405xx/407xx and STM32F415xx/417xx devices or (A, B, C, D and H) - * for STM32401xx devices. - * - * @param EXTI_PinSourcex: specifies the EXTI line to be configured. - * This parameter can be EXTI_PinSourcex where x can be (0..15, except - * for EXTI_PortSourceGPIOI x can be (0..11) for STM32F405xx/407xx - * and STM32F405xx/407xx devices and for EXTI_PortSourceGPIOK x can - * be (0..7) for STM32F42xxx/43xxx devices. - * - * @retval None - */ -void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) -{ - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); - assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); - - tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; - SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); -} - -/** - * @brief Selects the ETHERNET media interface - * @param SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. - * This parameter can be one of the following values: - * @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected - * @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected - * @retval None - */ -void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) -{ - assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); - /* Configure MII_RMII selection bit */ - *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; -} - -/** - * @brief Enables or disables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @param NewState: new state of the I/O Compensation Cell. - * This parameter can be one of the following values: - * @arg ENABLE: I/O compensation cell enabled - * @arg DISABLE: I/O compensation cell power-down mode - * @retval None - */ -void SYSCFG_CompensationCellCmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState; -} - -/** - * @brief Checks whether the I/O Compensation Cell ready flag is set or not. - * @param None - * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET) - */ -FlagStatus SYSCFG_GetCompensationCellStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) -/** - * @brief Connects the selected parameter to the break input of TIM1. - * @note The selected configuration is locked and can be unlocked by system reset - * @param SYSCFG_Break: selects the configuration to be connected to break - * input of TIM1 - * This parameter can be any combination of the following values: - * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1/8. - * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1/8. - * @retval None - */ -void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); - - SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break; -} -#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */ - -#if defined(STM32F413_423xx) -/** - * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock. - * @param source: BITSTREAM_CLOCK_DFSDM2. - * BITSTREAM_CLOCK_TIM2OC1. - * @retval None - */ -void DFSDM_BitstreamClock_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL)); - - SYSCFG->MCHDLYCR = (tmp|source); -} - -/** - * @brief Disable Delay Clock for DFSDM1/2. - * @param MCHDLY: MCHDLY_CLOCK_DFSDM2. - * MCHDLY_CLOCK_DFSDM1. - * @retval None - */ -void DFSDM_DisableDelayClock(uint32_t MCHDLY) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - if(MCHDLY == MCHDLY_CLOCK_DFSDM2) - { - tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN); - } - else - { - tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN); - } - - SYSCFG->MCHDLYCR = tmp; -} - -/** - * @brief Enable Delay Clock for DFSDM1/2. - * @param MCHDLY: MCHDLY_CLOCK_DFSDM2. - * MCHDLY_CLOCK_DFSDM1. - * @retval None - */ -void DFSDM_EnableDelayClock(uint32_t MCHDLY) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - tmp = tmp & ~MCHDLY; - - SYSCFG->MCHDLYCR = (tmp|MCHDLY); -} - -/** - * @brief Select the source for CKin signals for DFSDM1/2. - * @param source: DFSDM2_CKIN_PAD. - * DFSDM2_CKIN_DM. - * DFSDM1_CKIN_PAD. - * DFSDM1_CKIN_DM. - * @retval None - */ -void DFSDM_ClockIn_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - if((source == DFSDM2_CKIN_PAD) || (source == DFSDM2_CKIN_DM)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG); - } - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Select the source for CKOut signals for DFSDM1/2. - * @param source: DFSDM2_CKOUT_DFSDM2. - * DFSDM2_CKOUT_M27. - * DFSDM1_CKOUT_DFSDM1. - * DFSDM1_CKOUT_M27. - * @retval None - */ -void DFSDM_ClockOut_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - if((source == DFSDM2_CKOUT_DFSDM2) || (source == DFSDM2_CKOUT_M27)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL); - } - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Select the source for DataIn0 signals for DFSDM1/2. - * @param source: DATAIN0_DFSDM2_PAD. - * DATAIN0_DFSDM2_DATAIN1. - * DATAIN0_DFSDM1_PAD. - * DATAIN0_DFSDM1_DATAIN1. - * @retval None - */ -void DFSDM_DataIn0_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - if((source == DATAIN0_DFSDM2_PAD)|| (source == DATAIN0_DFSDM2_DATAIN1)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL); - } - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Select the source for DataIn2 signals for DFSDM1/2. - * @param source: DATAIN2_DFSDM2_PAD. - * DATAIN2_DFSDM2_DATAIN3. - * DATAIN2_DFSDM1_PAD. - * DATAIN2_DFSDM1_DATAIN3. - * @retval None - */ -void DFSDM_DataIn2_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - if((source == DATAIN2_DFSDM2_PAD)|| (source == DATAIN2_DFSDM2_DATAIN3)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL); - } - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Select the source for DataIn4 signals for DFSDM2. - * @param source: DATAIN4_DFSDM2_PAD. - * DATAIN4_DFSDM2_DATAIN5 - * @retval None - */ -void DFSDM_DataIn4_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL); - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Select the source for DataIn6 signals for DFSDM2. - * @param source: DATAIN6_DFSDM2_PAD. - * DATAIN6_DFSDM2_DATAIN7. - * @retval None - */ -void DFSDM_DataIn6_SourceSelection(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL); - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Configure the distribution of the bitstream clock gated from TIM4. - * @param source: DFSDM1_CLKIN0_TIM4OC2 - * DFSDM1_CLKIN2_TIM4OC2 - * DFSDM1_CLKIN1_TIM4OC1 - * DFSDM1_CLKIN3_TIM4OC1 - * @retval None - */ -void DFSDM1_BitStreamClk_Config(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - if ((source == DFSDM1_CLKIN0_TIM4OC2) || (source == DFSDM1_CLKIN2_TIM4OC2)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL); - } - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -/** - * @brief Configure the distribution of the bitstream clock gated from TIM3. - * @param source: DFSDM2_CLKIN0_TIM3OC4 - * DFSDM2_CLKIN4_TIM3OC4 - * DFSDM2_CLKIN1_TIM3OC3 - * DFSDM2_CLKIN5_TIM3OC3 - * DFSDM2_CLKIN2_TIM3OC2 - * DFSDM2_CLKIN6_TIM3OC2 - * DFSDM2_CLKIN3_TIM3OC1 - * DFSDM2_CLKIN7_TIM3OC1 - * @retval None - */ -void DFSDM2_BitStreamClk_Config(uint32_t source) -{ - uint32_t tmp = 0; - - tmp = SYSCFG->MCHDLYCR; - - if ((source == DFSDM2_CLKIN0_TIM3OC4) || (source == DFSDM2_CLKIN4_TIM3OC4)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL); - } - else if ((source == DFSDM2_CLKIN1_TIM3OC3) || (source == DFSDM2_CLKIN5_TIM3OC3)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL); - - }else if ((source == DFSDM2_CLKIN2_TIM3OC2) || (source == DFSDM2_CLKIN6_TIM3OC2)) - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL); - } - else - { - tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL); - } - - SYSCFG->MCHDLYCR |= (source|tmp); -} - -#endif /* STM32F413_423xx */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c deleted file mode 100644 index 7c62e1ab0..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c +++ /dev/null @@ -1,3365 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_tim.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the TIM peripheral: - * + TimeBase management - * + Output Compare management - * + Input Capture management - * + Advanced-control timers (TIM1 and TIM8) specific features - * + Interrupts, DMA and flags management - * + Clocks management - * + Synchronization management - * + Specific interface management - * + Specific remapping management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - This driver provides functions to configure and program the TIM - of all STM32F4xx devices. - These functions are split in 9 groups: - - (#) TIM TimeBase management: this group includes all needed functions - to configure the TM Timebase unit: - (++) Set/Get Prescaler - (++) Set/Get Autoreload - (++) Counter modes configuration - (++) Set Clock division - (++) Select the One Pulse mode - (++) Update Request Configuration - (++) Update Disable Configuration - (++) Auto-Preload Configuration - (++) Enable/Disable the counter - - (#) TIM Output Compare management: this group includes all needed - functions to configure the Capture/Compare unit used in Output - compare mode: - (++) Configure each channel, independently, in Output Compare mode - (++) Select the output compare modes - (++) Select the Polarities of each channel - (++) Set/Get the Capture/Compare register values - (++) Select the Output Compare Fast mode - (++) Select the Output Compare Forced mode - (++) Output Compare-Preload Configuration - (++) Clear Output Compare Reference - (++) Select the OCREF Clear signal - (++) Enable/Disable the Capture/Compare Channels - - (#) TIM Input Capture management: this group includes all needed - functions to configure the Capture/Compare unit used in - Input Capture mode: - (++) Configure each channel in input capture mode - (++) Configure Channel1/2 in PWM Input mode - (++) Set the Input Capture Prescaler - (++) Get the Capture/Compare values - - (#) Advanced-control timers (TIM1 and TIM8) specific features - (++) Configures the Break input, dead time, Lock level, the OSSI, - the OSSR State and the AOE(automatic output enable) - (++) Enable/Disable the TIM peripheral Main Outputs - (++) Select the Commutation event - (++) Set/Reset the Capture Compare Preload Control bit - - (#) TIM interrupts, DMA and flags management - (++) Enable/Disable interrupt sources - (++) Get flags status - (++) Clear flags/ Pending bits - (++) Enable/Disable DMA requests - (++) Configure DMA burst mode - (++) Select CaptureCompare DMA request - - (#) TIM clocks management: this group includes all needed functions - to configure the clock controller unit: - (++) Select internal/External clock - (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx - - (#) TIM synchronization management: this group includes all needed - functions to configure the Synchronization unit: - (++) Select Input Trigger - (++) Select Output Trigger - (++) Select Master Slave Mode - (++) ETR Configuration when used as external trigger - - (#) TIM specific interface management, this group includes all - needed functions to use the specific TIM interface: - (++) Encoder Interface Configuration - (++) Select Hall Sensor - - (#) TIM specific remapping management includes the Remapping - configuration of specific timers - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_tim.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup TIM - * @brief TIM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ---------------------- TIM registers bit mask ------------------------ */ -#define SMCR_ETR_MASK ((uint16_t)0x00FF) -#define CCMR_OFFSET ((uint16_t)0x0018) -#define CCER_CCE_SET ((uint16_t)0x0001) -#define CCER_CCNE_SET ((uint16_t)0x0004) -#define CCMR_OC13M_MASK ((uint16_t)0xFF8F) -#define CCMR_OC24M_MASK ((uint16_t)0x8FFF) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter); - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup TIM_Private_Functions - * @{ - */ - -/** @defgroup TIM_Group1 TimeBase management functions - * @brief TimeBase management functions - * -@verbatim - =============================================================================== - ##### TimeBase management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Timing(Time base) Mode ##### - =============================================================================== - [..] - To use the Timer in Timing(Time base) mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function - - (#) Fill the TIM_TimeBaseInitStruct with the desired parameters. - - (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit - with the corresponding configuration - - (#) Enable the NVIC if you need to generate the update interrupt. - - (#) Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the TIMx peripheral registers to their default reset values. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval None - - */ -void TIM_DeInit(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - if (TIMx == TIM1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); - } - else if (TIMx == TIM2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); - } - else if (TIMx == TIM3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); - } - else if (TIMx == TIM4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); - } - else if (TIMx == TIM5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); - } - else if (TIMx == TIM6) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); - } - else if (TIMx == TIM7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); - } - else if (TIMx == TIM8) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); - } - else if (TIMx == TIM9) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); - } - else if (TIMx == TIM10) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); - } - else if (TIMx == TIM11) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); - } - else if (TIMx == TIM12) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); - } - else if (TIMx == TIM13) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); - } - else - { - if (TIMx == TIM14) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); - } - } -} - -/** - * @brief Initializes the TIMx Time Base Unit peripheral according to - * the specified parameters in the TIM_TimeBaseInitStruct. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure - * that contains the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); - assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); - - tmpcr1 = TIMx->CR1; - - if((TIMx == TIM1) || (TIMx == TIM8)|| - (TIMx == TIM2) || (TIMx == TIM3)|| - (TIMx == TIM4) || (TIMx == TIM5)) - { - /* Select the Counter Mode */ - tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; - } - - if((TIMx != TIM6) && (TIMx != TIM7)) - { - /* Set the clock division */ - tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); - tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; - } - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; - - /* Set the Prescaler value */ - TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; - - if ((TIMx == TIM1) || (TIMx == TIM8)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter(only for TIM1 and TIM8) value immediately */ - TIMx->EGR = TIM_PSCReloadMode_Immediate; -} - -/** - * @brief Fills each TIM_TimeBaseInitStruct member with its default value. - * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef - * structure which will be initialized. - * @retval None - */ -void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) -{ - /* Set the default configuration */ - TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; - TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; - TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; - TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; -} - -/** - * @brief Configures the TIMx Prescaler. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Prescaler: specifies the Prescaler Register value - * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode - * This parameter can be one of the following values: - * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. - * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. - * @retval None - */ -void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); - /* Set the Prescaler value */ - TIMx->PSC = Prescaler; - /* Set or reset the UG Bit */ - TIMx->EGR = TIM_PSCReloadMode; -} - -/** - * @brief Specifies the TIMx Counter Mode to be used. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_CounterMode: specifies the Counter Mode to be used - * This parameter can be one of the following values: - * @arg TIM_CounterMode_Up: TIM Up Counting Mode - * @arg TIM_CounterMode_Down: TIM Down Counting Mode - * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 - * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 - * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 - * @retval None - */ -void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) -{ - uint16_t tmpcr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); - - tmpcr1 = TIMx->CR1; - - /* Reset the CMS and DIR Bits */ - tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS); - - /* Set the Counter Mode */ - tmpcr1 |= TIM_CounterMode; - - /* Write to TIMx CR1 register */ - TIMx->CR1 = tmpcr1; -} - -/** - * @brief Sets the TIMx Counter Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Counter: specifies the Counter register new value. - * @retval None - */ -void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Counter Register value */ - TIMx->CNT = Counter; -} - -/** - * @brief Sets the TIMx Autoreload Register value - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param Autoreload: specifies the Autoreload register new value. - * @retval None - */ -void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Set the Autoreload Register value */ - TIMx->ARR = Autoreload; -} - -/** - * @brief Gets the TIMx Counter value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Counter Register value - */ -uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Counter Register value */ - return TIMx->CNT; -} - -/** - * @brief Gets the TIMx Prescaler value. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @retval Prescaler Register value. - */ -uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Get the Prescaler Register value */ - return TIMx->PSC; -} - -/** - * @brief Enables or Disables the TIMx Update event. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx UDIS bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the Update Disable Bit */ - TIMx->CR1 |= TIM_CR1_UDIS; - } - else - { - /* Reset the Update Disable Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS; - } -} - -/** - * @brief Configures the TIMx Update Request Interrupt source. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_UpdateSource: specifies the Update source. - * This parameter can be one of the following values: - * @arg TIM_UpdateSource_Global: Source of update is the counter - * overflow/underflow or the setting of UG bit, or an update - * generation through the slave mode controller. - * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. - * @retval None - */ -void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); - - if (TIM_UpdateSource != TIM_UpdateSource_Global) - { - /* Set the URS Bit */ - TIMx->CR1 |= TIM_CR1_URS; - } - else - { - /* Reset the URS Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_URS; - } -} - -/** - * @brief Enables or disables TIMx peripheral Preload register on ARR. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param NewState: new state of the TIMx peripheral Preload register - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the ARR Preload Bit */ - TIMx->CR1 |= TIM_CR1_ARPE; - } - else - { - /* Reset the ARR Preload Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE; - } -} - -/** - * @brief Selects the TIMx's One Pulse Mode. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_OPMode: specifies the OPM Mode to be used. - * This parameter can be one of the following values: - * @arg TIM_OPMode_Single - * @arg TIM_OPMode_Repetitive - * @retval None - */ -void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); - - /* Reset the OPM Bit */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - TIMx->CR1 |= TIM_OPMode; -} - -/** - * @brief Sets the TIMx Clock Division value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_CKD: specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CKD_DIV1: TDTS = Tck_tim - * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim - * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim - * @retval None - */ -void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CKD_DIV(TIM_CKD)); - - /* Reset the CKD Bits */ - TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD); - - /* Set the CKD value */ - TIMx->CR1 |= TIM_CKD; -} - -/** - * @brief Enables or disables the specified TIM peripheral. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param NewState: new state of the TIMx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Counter */ - TIMx->CR1 |= TIM_CR1_CEN; - } - else - { - /* Disable the TIM Counter */ - TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group2 Output Compare management functions - * @brief Output Compare management functions - * -@verbatim - =============================================================================== - ##### Output Compare management functions ##### - =============================================================================== - - - ##### TIM Driver: how to use it in Output Compare Mode ##### - =============================================================================== - [..] - To use the Timer in Output Compare mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - (++) if needed, else the Timer will run with the default configuration: - Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_OCInitStruct with the desired parameters including: - (++) The TIM Output Compare mode: TIM_OCMode - (++) TIM Output State: TIM_OutputState - (++) TIM Pulse value: TIM_Pulse - (++) TIM Output Compare Polarity : TIM_OCPolarity - - (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired - channel with the corresponding configuration - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - - -@- In case of PWM mode, this function is mandatory: - TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); - - -@- If the corresponding interrupt or DMA request are needed, the user should: - (+@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). - (+@) Enable the corresponding interrupt (or DMA request) using the function - TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIMx Channel1 according to the specified parameters in - * the TIM_OCInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; - - /* Set the Output State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputState; - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NE; - - /* Set the Output N State */ - tmpccer |= TIM_OCInitStruct->TIM_OutputNState; - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel2 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M; - tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel3 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); - assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - - /* Reset the Output N Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); - /* Reset the Output N State */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NE; - - /* Set the Output N State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3; - tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); - /* Set the Output N Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Initializes the TIMx Channel4 according to the specified parameters - * in the TIM_OCInitStruct. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); - assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M; - tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); - - /* Reset the Output Polarity level */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); - - /* Set the Output State */ - tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); - - if((TIMx == TIM1) || (TIMx == TIM8)) - { - assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); - /* Reset the Output Compare IDLE State */ - tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4; - /* Set the Output Idle state */ - tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Fills each TIM_OCInitStruct member with its default value. - * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) -{ - /* Set the default configuration */ - TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; - TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; - TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; - TIM_OCInitStruct->TIM_Pulse = 0x00000000; - TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; - TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; - TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; -} - -/** - * @brief Selects the TIM Output Compare Mode. - * @note This function disables the selected channel before changing the Output - * Compare Mode. If needed, user has to enable this channel using - * TIM_CCxCmd() and TIM_CCxNCmd() functions. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_OCMode: specifies the TIM Output Compare Mode. - * This parameter can be one of the following values: - * @arg TIM_OCMode_Timing - * @arg TIM_OCMode_Active - * @arg TIM_OCMode_Toggle - * @arg TIM_OCMode_PWM1 - * @arg TIM_OCMode_PWM2 - * @arg TIM_ForcedAction_Active - * @arg TIM_ForcedAction_InActive - * @retval None - */ -void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) -{ - uint32_t tmp = 0; - uint16_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_OCM(TIM_OCMode)); - - tmp = (uint32_t) TIMx; - tmp += CCMR_OFFSET; - - tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel; - - /* Disable the Channel: Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t) ~tmp1; - - if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) - { - tmp += (TIM_Channel>>1); - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= TIM_OCMode; - } - else - { - tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; - - /* Reset the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK; - - /* Configure the OCxM bits in the CCMRx register */ - *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); - } -} - -/** - * @brief Sets the TIMx Capture Compare1 Register value - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param Compare1: specifies the Capture Compare1 register new value. - * @retval None - */ -void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Set the Capture Compare1 Register value */ - TIMx->CCR1 = Compare1; -} - -/** - * @brief Sets the TIMx Capture Compare2 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param Compare2: specifies the Capture Compare2 register new value. - * @retval None - */ -void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Set the Capture Compare2 Register value */ - TIMx->CCR2 = Compare2; -} - -/** - * @brief Sets the TIMx Capture Compare3 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare3: specifies the Capture Compare3 register new value. - * @retval None - */ -void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare3 Register value */ - TIMx->CCR3 = Compare3; -} - -/** - * @brief Sets the TIMx Capture Compare4 Register value - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param Compare4: specifies the Capture Compare4 register new value. - * @retval None - */ -void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Set the Capture Compare4 Register value */ - TIMx->CCR4 = Compare4; -} - -/** - * @brief Forces the TIMx output 1 waveform to active or inactive level. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC1REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. - * @retval None - */ -void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= TIM_ForcedAction; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 2 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC2REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. - * @retval None - */ -void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2M Bits */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M; - - /* Configure The Forced output Mode */ - tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Forces the TIMx output 3 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC3REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. - * @retval None - */ -void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC1M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= TIM_ForcedAction; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Forces the TIMx output 4 waveform to active or inactive level. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. - * This parameter can be one of the following values: - * @arg TIM_ForcedAction_Active: Force active level on OC4REF - * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. - * @retval None - */ -void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC2M Bits */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M; - - /* Configure The Forced output Mode */ - tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR1. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= TIM_OCPreload; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR2. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2PE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR3. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= TIM_OCPreload; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Enables or disables the TIMx peripheral Preload register on CCR4. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPreload: new state of the TIMx peripheral Preload register - * This parameter can be one of the following values: - * @arg TIM_OCPreload_Enable - * @arg TIM_OCPreload_Disable - * @retval None - */ -void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4PE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE); - - /* Enable or Disable the Output Compare Preload feature */ - tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 1 Fast feature. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1FE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= TIM_OCFast; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 2 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2FE Bit */ - tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Configures the TIMx Output Compare 3 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3FE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE; - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= TIM_OCFast; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx Output Compare 4 Fast feature. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCFast_Enable: TIM output compare fast enable - * @arg TIM_OCFast_Disable: TIM output compare fast disable - * @retval None - */ -void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4FE Bit */ - tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE); - - /* Enable or Disable the Output Compare Fast Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF1 signal on an external event - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC1CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= TIM_OCClear; - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF2 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr1 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr1 = TIMx->CCMR1; - - /* Reset the OC2CE Bit */ - tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR1 register */ - TIMx->CCMR1 = tmpccmr1; -} - -/** - * @brief Clears or safeguards the OCREF3 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC3CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= TIM_OCClear; - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Clears or safeguards the OCREF4 signal on an external event - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. - * This parameter can be one of the following values: - * @arg TIM_OCClear_Enable: TIM Output clear enable - * @arg TIM_OCClear_Disable: TIM Output clear disable - * @retval None - */ -void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) -{ - uint16_t tmpccmr2 = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); - - tmpccmr2 = TIMx->CCMR2; - - /* Reset the OC4CE Bit */ - tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE; - - /* Enable or Disable the Output Compare Clear Bit */ - tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); - - /* Write to TIMx CCMR2 register */ - TIMx->CCMR2 = tmpccmr2; -} - -/** - * @brief Configures the TIMx channel 1 polarity. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC1P); - tmpccer |= TIM_OCPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 1N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC1N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC1NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC1NP; - tmpccer |= TIM_OCNPolarity; - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 2 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_OCPolarity: specifies the OC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2P Bit */ - tmpccer &= (uint16_t)(~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_OCPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 2N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC2N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC2NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC2NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 3 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC3 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx Channel 3N polarity. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_OCNPolarity: specifies the OC3N Polarity - * This parameter can be one of the following values: - * @arg TIM_OCNPolarity_High: Output Compare active high - * @arg TIM_OCNPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC3NP Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC3NP; - tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Configures the TIMx channel 4 polarity. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_OCPolarity: specifies the OC4 Polarity - * This parameter can be one of the following values: - * @arg TIM_OCPolarity_High: Output Compare active high - * @arg TIM_OCPolarity_Low: Output Compare active low - * @retval None - */ -void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) -{ - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); - - tmpccer = TIMx->CCER; - - /* Set or Reset the CC4P Bit */ - tmpccer &= (uint16_t)~TIM_CCER_CC4P; - tmpccer |= (uint16_t)(TIM_OCPolarity << 12); - - /* Write to TIMx CCER register */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @arg TIM_Channel_4: TIM Channel 4 - * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. - * @retval None - */ -void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCX(TIM_CCx)); - - tmp = CCER_CCE_SET << TIM_Channel; - - /* Reset the CCxE Bit */ - TIMx->CCER &= (uint16_t)~ tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. - * @param TIM_Channel: specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_Channel_1: TIM Channel 1 - * @arg TIM_Channel_2: TIM Channel 2 - * @arg TIM_Channel_3: TIM Channel 3 - * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. - * @retval None - */ -void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) -{ - uint16_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); - assert_param(IS_TIM_CCXN(TIM_CCxN)); - - tmp = CCER_CCNE_SET << TIM_Channel; - - /* Reset the CCxNE Bit */ - TIMx->CCER &= (uint16_t) ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); -} -/** - * @} - */ - -/** @defgroup TIM_Group3 Input Capture management functions - * @brief Input Capture management functions - * -@verbatim - =============================================================================== - ##### Input Capture management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in Input Capture Mode ##### - =============================================================================== - [..] - To use the Timer in Input Capture mode, the following steps are mandatory: - - (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) - function - - (#) Configure the TIM pins by configuring the corresponding GPIO pins - - (#) Configure the Time base unit as described in the first part of this driver, - if needed, else the Timer will run with the default configuration: - (++) Autoreload value = 0xFFFF - (++) Prescaler value = 0x0000 - (++) Counter mode = Up counting - (++) Clock Division = TIM_CKD_DIV1 - - (#) Fill the TIM_ICInitStruct with the desired parameters including: - (++) TIM Channel: TIM_Channel - (++) TIM Input Capture polarity: TIM_ICPolarity - (++) TIM Input Capture selection: TIM_ICSelection - (++) TIM Input Capture Prescaler: TIM_ICPrescaler - (++) TIM Input Capture filter value: TIM_ICFilter - - (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel - with the corresponding configuration and to measure only frequency - or duty cycle of the input signal, or, Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) - to configure the desired channels with the corresponding configuration - and to measure the frequency and the duty cycle of the input signal - - (#) Enable the NVIC or the DMA to read the measured frequency. - - (#) Enable the corresponding interrupt (or DMA request) to read the Captured - value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx) - (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) - - (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter. - - (#) Use TIM_GetCapturex(TIMx); to read the captured value. - - -@- All other functions can be used separately to modify, if needed, - a specific feature of the Timer. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); - - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI4 Configuration */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, - TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Fills each TIM_ICInitStruct member with its default value. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will - * be initialized. - * @retval None - */ -void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; - TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; - TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; - TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; - TIM_ICInitStruct->TIM_ICFilter = 0x00; -} - -/** - * @brief Configures the TIM peripheral according to the specified parameters - * in the TIM_ICInitStruct to measure an external PWM signal. - * @param TIMx: where x can be 1, 2, 3, 4, 5,8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains - * the configuration information for the specified TIM peripheral. - * @retval None - */ -void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) -{ - uint16_t icoppositepolarity = TIM_ICPolarity_Rising; - uint16_t icoppositeselection = TIM_ICSelection_DirectTI; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Select the Opposite Input Polarity */ - if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) - { - icoppositepolarity = TIM_ICPolarity_Falling; - } - else - { - icoppositepolarity = TIM_ICPolarity_Rising; - } - /* Select the Opposite Input */ - if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) - { - icoppositeselection = TIM_ICSelection_IndirectTI; - } - else - { - icoppositeselection = TIM_ICSelection_DirectTI; - } - if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) - { - /* TI1 Configuration */ - TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI2 Configuration */ - TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } - else - { - /* TI2 Configuration */ - TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, - TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - /* TI1 Configuration */ - TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); - /* Set the Input Capture Prescaler value */ - TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); - } -} - -/** - * @brief Gets the TIMx Input Capture 1 value. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @retval Capture Compare 1 Register value. - */ -uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - - /* Get the Capture 1 Register value */ - return TIMx->CCR1; -} - -/** - * @brief Gets the TIMx Input Capture 2 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval Capture Compare 2 Register value. - */ -uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Get the Capture 2 Register value */ - return TIMx->CCR2; -} - -/** - * @brief Gets the TIMx Input Capture 3 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 3 Register value. - */ -uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 3 Register value */ - return TIMx->CCR3; -} - -/** - * @brief Gets the TIMx Input Capture 4 value. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @retval Capture Compare 4 Register value. - */ -uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - - /* Get the Capture 4 Register value */ - return TIMx->CCR4; -} - -/** - * @brief Sets the TIMx Input Capture 1 prescaler. - * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC1PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - TIMx->CCMR1 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 2 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC2PSC Bits */ - TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); -} - -/** - * @brief Sets the TIMx Input Capture 3 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC3PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - TIMx->CCMR2 |= TIM_ICPSC; -} - -/** - * @brief Sets the TIMx Input Capture 4 prescaler. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); - - /* Reset the IC4PSC Bits */ - TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); -} -/** - * @} - */ - -/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features - * @brief Advanced-control timers (TIM1 and TIM8) specific features - * -@verbatim - =============================================================================== - ##### Advanced-control timers (TIM1 and TIM8) specific features ##### - =============================================================================== - - ##### TIM Driver: how to use the Break feature ##### - =============================================================================== - [..] - After configuring the Timer channel(s) in the appropriate Output Compare mode: - - (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer - Break Polarity, dead time, Lock level, the OSSI/OSSR State and the - AOE(automatic output enable). - - (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer - - (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) - - (#) Once the break even occurs, the Timer's output signals are put in reset - state or in a known state (according to the configuration made in - TIM_BDTRConfig() function). - -@endverbatim - * @{ - */ - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param TIMx: where x can be 1 or 8 to select the TIM - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @retval None - */ -void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); - assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); - assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); - assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); - assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | - TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | - TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | - TIM_BDTRInitStruct->TIM_AutomaticOutput; -} - -/** - * @brief Fills each TIM_BDTRInitStruct member with its default value. - * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which - * will be initialized. - * @retval None - */ -void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; - TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; - TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; - TIM_BDTRInitStruct->TIM_DeadTime = 0x00; - TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; - TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; - TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; -} - -/** - * @brief Enables or disables the TIM peripheral Main Outputs. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. - * @param NewState: new state of the TIM peripheral Main Outputs. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the TIM Main Output */ - TIMx->BDTR |= TIM_BDTR_MOE; - } - else - { - /* Disable the TIM Main Output */ - TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE; - } -} - -/** - * @brief Selects the TIM peripheral Commutation event. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Commutation event. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the COM Bit */ - TIMx->CR2 |= TIM_CR2_CCUS; - } - else - { - /* Reset the COM Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS; - } -} - -/** - * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. - * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral - * @param NewState: new state of the Capture Compare Preload Control bit - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST4_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Set the CCPC Bit */ - TIMx->CR2 |= TIM_CR2_CCPC; - } - else - { - /* Reset the CCPC Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group5 Interrupts DMA and flags management functions - * @brief Interrupts, DMA and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts, DMA and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified TIM interrupts. - * @param TIMx: where x can be 1 to 14 to select the TIMx peripheral. - * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note For TIM6 and TIM7 only the parameter TIM_IT_Update can be used - * @note For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update, - * TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. - * @note For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can - * be used: TIM_IT_Update or TIM_IT_CC1 - * @note TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 - * - * @param NewState: new state of the TIM interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_IT(TIM_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Interrupt sources */ - TIMx->DIER |= TIM_IT; - } - else - { - /* Disable the Interrupt sources */ - TIMx->DIER &= (uint16_t)~TIM_IT; - } -} - -/** - * @brief Configures the TIMx event to be generate by software. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_EventSource: specifies the event source. - * This parameter can be one or more of the following values: - * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_COM: Timer COM event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @arg TIM_EventSource_Break: Timer Break event source - * - * @note TIM6 and TIM7 can only generate an update event. - * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); - - /* Set the event sources */ - TIMx->EGR = TIM_EventSource; -} - -/** - * @brief Checks whether the specified TIM flag is set or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval The new state of TIM_FLAG (SET or RESET). - */ -FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); - - - if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's pending flags. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_FLAG: specifies the flag bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_FLAG_Update: TIM update Flag - * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag - * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag - * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag - * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag - * @arg TIM_FLAG_COM: TIM Commutation Flag - * @arg TIM_FLAG_Trigger: TIM Trigger Flag - * @arg TIM_FLAG_Break: TIM Break Flag - * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag - * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag - * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag - * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag - * - * @note TIM6 and TIM7 can have only one update flag. - * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the flags */ - TIMx->SR = (uint16_t)~TIM_FLAG; -} - -/** - * @brief Checks whether the TIM interrupt has occurred or not. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_Update: TIM update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval The new state of the TIM_IT(SET or RESET). - */ -ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - ITStatus bitstatus = RESET; - uint16_t itstatus = 0x0, itenable = 0x0; - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - assert_param(IS_TIM_GET_IT(TIM_IT)); - - itstatus = TIMx->SR & TIM_IT; - - itenable = TIMx->DIER & TIM_IT; - if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the TIMx's interrupt pending bits. - * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. - * @param TIM_IT: specifies the pending bit to clear. - * This parameter can be any combination of the following values: - * @arg TIM_IT_Update: TIM1 update Interrupt source - * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source - * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source - * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source - * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source - * @arg TIM_IT_COM: TIM Commutation Interrupt source - * @arg TIM_IT_Trigger: TIM Trigger Interrupt source - * @arg TIM_IT_Break: TIM Break Interrupt source - * - * @note TIM6 and TIM7 can generate only an update interrupt. - * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. - * - * @retval None - */ -void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) -{ - /* Check the parameters */ - assert_param(IS_TIM_ALL_PERIPH(TIMx)); - - /* Clear the IT pending Bit */ - TIMx->SR = (uint16_t)~TIM_IT; -} - -/** - * @brief Configures the TIMx's DMA interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_DMABase: DMA Base address. - * This parameter can be one of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM1_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_RCR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_BDTR - * @arg TIM_DMABase_DCR - * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value - * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. - * @retval None - */ -void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); - assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); - - /* Set the DMA Base and the DMA Burst Length */ - TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; -} - -/** - * @brief Enables or disables the TIMx's DMA Requests. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * @param TIM_DMASource: specifies the DMA Request sources. - * This parameter can be any combination of the following values: - * @arg TIM_DMA_Update: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_Trigger: TIM Trigger DMA source - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA sources */ - TIMx->DIER |= TIM_DMASource; - } - else - { - /* Disable the DMA sources */ - TIMx->DIER &= (uint16_t)~TIM_DMASource; - } -} - -/** - * @brief Selects the TIMx peripheral Capture Compare DMA source. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param NewState: new state of the Capture Compare DMA source - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the CCDS Bit */ - TIMx->CR2 |= TIM_CR2_CCDS; - } - else - { - /* Reset the CCDS Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group6 Clocks management functions - * @brief Clocks management functions - * -@verbatim - =============================================================================== - ##### Clocks management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx internal Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @retval None - */ -void TIM_InternalClockConfig(TIM_TypeDef* TIMx) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - - /* Disable slave mode to clock the prescaler directly with the internal clock */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; -} - -/** - * @brief Configures the TIMx Internal Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_InputTriggerSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @retval None - */ -void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Select the Internal Trigger */ - TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); - - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the TIMx Trigger as External Clock - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_TIxExternalCLKSource: Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector - * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 - * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 - * @param TIM_ICPolarity: specifies the TIx Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @param ICFilter: specifies the filter value. - * This parameter must be a value between 0x0 and 0xF. - * @retval None - */ -void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, - uint16_t TIM_ICPolarity, uint16_t ICFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); - assert_param(IS_TIM_IC_FILTER(ICFilter)); - - /* Configure the Timer Input Clock Source */ - if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) - { - TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - else - { - TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); - } - /* Select the Trigger source */ - TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); - /* Select the External clock mode1 */ - TIMx->SMCR |= TIM_SlaveMode_External1; -} - -/** - * @brief Configures the External clock Mode1 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the SMS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the External clock mode1 */ - tmpsmcr |= TIM_SlaveMode_External1; - - /* Select the Trigger selection : ETRF */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - tmpsmcr |= TIM_TS_ETRF; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Configures the External clock Mode2 - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - /* Configure the ETR Clock source */ - TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); - - /* Enable the External clock mode2 */ - TIMx->SMCR |= TIM_SMCR_ECE; -} -/** - * @} - */ - -/** @defgroup TIM_Group7 Synchronization management functions - * @brief Synchronization management functions - * -@verbatim - =============================================================================== - ##### Synchronization management functions ##### - =============================================================================== - - ##### TIM Driver: how to use it in synchronization Mode ##### - =============================================================================== - [..] - - *** Case of two/several Timers *** - ================================== - [..] - (#) Configure the Master Timers using the following functions: - (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); - (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - - *** Case of Timers and external trigger(ETR pin) *** - ==================================================== - [..] - (#) Configure the External trigger using this function: - (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, - uint16_t ExtTRGFilter); - (#) Configure the Slave Timers using the following functions: - (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); - (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); - -@endverbatim - * @{ - */ - -/** - * @brief Selects the Input Trigger source - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_InputTriggerSource: The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST1_PERIPH(TIMx)); - assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Reset the TS Bits */ - tmpsmcr &= (uint16_t)~TIM_SMCR_TS; - - /* Set the Input Trigger source */ - tmpsmcr |= TIM_InputTriggerSource; - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Selects the TIMx Trigger Output Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. - * - * @param TIM_TRGOSource: specifies the Trigger Output source. - * This parameter can be one of the following values: - * - * - For all TIMx - * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO) - * - * - For all TIMx except TIM6 and TIM7 - * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag - * is to be set, as soon as a capture or compare match occurs(TRGO) - * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO) - * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO) - * - * @retval None - */ -void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST5_PERIPH(TIMx)); - assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); - - /* Reset the MMS Bits */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS; - /* Select the TRGO source */ - TIMx->CR2 |= TIM_TRGOSource; -} - -/** - * @brief Selects the TIMx Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_SlaveMode: specifies the Timer Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize - * the counter and triggers an update of the registers - * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high - * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI - * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter - * @retval None - */ -void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); - - /* Reset the SMS Bits */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS; - - /* Select the Slave Mode */ - TIMx->SMCR |= TIM_SlaveMode; -} - -/** - * @brief Sets or Resets the TIMx Master/Slave Mode. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. - * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. - * This parameter can be one of the following values: - * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer - * and its slaves (through TRGO) - * @arg TIM_MasterSlaveMode_Disable: No action - * @retval None - */ -void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); - - /* Reset the MSM Bit */ - TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM; - - /* Set or Reset the MSM Bit */ - TIMx->SMCR |= TIM_MasterSlaveMode; -} - -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. - * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. - * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. - * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. - * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, - uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) -{ - uint16_t tmpsmcr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST3_PERIPH(TIMx)); - assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); - assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); - assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= SMCR_ETR_MASK; - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @} - */ - -/** @defgroup TIM_Group8 Specific interface management functions - * @brief Specific interface management functions - * -@verbatim - =============================================================================== - ##### Specific interface management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIMx Encoder Interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. - * This parameter can be one of the following values: - * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. - * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. - * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending - * on the level of the other input. - * @param TIM_IC1Polarity: specifies the IC1 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @param TIM_IC2Polarity: specifies the IC2 Polarity - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Falling: IC Falling edge. - * @arg TIM_ICPolarity_Rising: IC Rising edge. - * @retval None - */ -void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, - uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) -{ - uint16_t tmpsmcr = 0; - uint16_t tmpccmr1 = 0; - uint16_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = TIMx->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Set the encoder Mode */ - tmpsmcr &= (uint16_t)~TIM_SMCR_SMS; - tmpsmcr |= TIM_EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S); - tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P); - tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Enables or disables the TIMx's Hall sensor interface. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param NewState: new state of the TIMx Hall sensor interface. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST2_PERIPH(TIMx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Set the TI1S Bit */ - TIMx->CR2 |= TIM_CR2_TI1S; - } - else - { - /* Reset the TI1S Bit */ - TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S; - } -} -/** - * @} - */ - -/** @defgroup TIM_Group9 Specific remapping management function - * @brief Specific remapping management function - * -@verbatim - =============================================================================== - ##### Specific remapping management function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param TIMx: where x can be 2, 5 or 11 to select the TIM peripheral. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. - * @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @retval None - */ -void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap) -{ - /* Check the parameters */ - assert_param(IS_TIM_LIST6_PERIPH(TIMx)); - assert_param(IS_TIM_REMAP(TIM_Remap)); - - /* Set the Timer remapping configuration */ - TIMx->OR = TIM_Remap; -} -/** - * @} - */ - -/** - * @brief Configure the TI1 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 - * to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F); - tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM - * peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 4); - - /* Select the Input and set the filter */ - tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); - tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 8); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPolarity_Rising - * @arg TIM_ICPolarity_Falling - * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, - uint16_t TIM_ICFilter) -{ - uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - tmpccer = TIMx->CCER; - tmp = (uint16_t)(TIM_ICPolarity << 12); - - /* Select the Input and set the filter */ - tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F); - tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); - tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c deleted file mode 100644 index d4ebc3f4c..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c +++ /dev/null @@ -1,1486 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_usart.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Universal synchronous asynchronous receiver - * transmitter (USART): - * + Initialization and Configuration - * + Data transfers - * + Multi-Processor Communication - * + LIN mode - * + Half-duplex mode - * + Smartcard mode - * + IrDA mode - * + DMA transfers management - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable peripheral clock using the following functions - RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 - RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, - UART4 or UART5. - - (#) According to the USART mode, enable the GPIO clocks using - RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, - or/and SCLK). - - (#) Peripheral's alternate function: - (++) Connect the pin to the desired peripherals' Alternate - Function (AF) using GPIO_PinAFConfig() function - (++) Configure the desired pin in alternate function by: - GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF - (++) Select the type, pull-up/pull-down and output speed via - GPIO_PuPd, GPIO_OType and GPIO_Speed members - (++) Call GPIO_Init() function - - (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware - flow control and Mode(Receiver/Transmitter) using the USART_Init() - function. - - (#) For synchronous mode, enable the clock and program the polarity, - phase and last bit using the USART_ClockInit() function. - - (#) Enable the NVIC and the corresponding interrupt using the function - USART_ITConfig() if you need to use interrupt mode. - - (#) When using the DMA mode - (++) Configure the DMA using DMA_Init() function - (++) Active the needed channel Request using USART_DMACmd() function - - (#) Enable the USART using the USART_Cmd() function. - - (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode. - - -@- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections - for more details - - [..] - In order to reach higher communication baudrates, it is possible to - enable the oversampling by 8 mode using the function USART_OverSampling8Cmd(). - This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd()) - and before calling the function USART_Init(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_usart.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup USART - * @brief USART driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */ -#define CR1_CLEAR_MASK ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE)) - -/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */ -#define CR2_CLOCK_CLEAR_MASK ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) - -/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */ -#define CR3_CLEAR_MASK ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE)) - -/*!< USART Interrupts mask */ -#define IT_MASK ((uint16_t)0x001F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup USART_Private_Functions - * @{ - */ - -/** @defgroup USART_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - Depending on the frame length defined by the M bit (8-bits or 9-bits), - the possible USART frame formats are as listed in the following table: - +-------------------------------------------------------------+ - | M bit | PCE bit | USART frame | - |---------------------|---------------------------------------| - | 0 | 0 | | SB | 8 bit data | STB | | - |---------|-----------|---------------------------------------| - | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|-----------|---------------------------------------| - | 1 | 0 | | SB | 9 bit data | STB | | - |---------|-----------|---------------------------------------| - | 1 | 1 | | SB | 8 bit data | PB | STB | | - +-------------------------------------------------------------+ - (++) Hardware flow control - (++) Receiver/transmitter modes - - [..] - The USART_Init() function follows the USART asynchronous configuration - procedure (details for the procedure are available in reference manual (RM0090)). - - (+) For the synchronous mode in addition to the asynchronous mode parameters these - parameters should be also configured: - (++) USART Clock Enabled - (++) USART polarity - (++) USART phase - (++) USART LastBit - - [..] - These parameters can be configured using the USART_ClockInit() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the USARTx peripheral registers to their default reset values. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_DeInit(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - if (USARTx == USART1) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); - } - else if (USARTx == USART2) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); - } - else if (USARTx == USART3) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); - } - else if (USARTx == UART4) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); - } - else if (USARTx == UART5) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); - } - else if (USARTx == USART6) - { - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); - RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); - } - else if (USARTx == UART7) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); - } - else - { - if (USARTx == UART8) - { - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); - } - } -} - -/** - * @brief Initializes the USARTx peripheral according to the specified - * parameters in the USART_InitStruct . - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains - * the configuration information for the specified USART peripheral. - * @retval None - */ -void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) -{ - uint32_t tmpreg = 0x00, apbclock = 0x00; - uint32_t integerdivider = 0x00; - uint32_t fractionaldivider = 0x00; - RCC_ClocksTypeDef RCC_ClocksStatus; - - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); - assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength)); - assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); - assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); - assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); - assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); - - /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */ - if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - - /* Clear STOP[13:12] bits */ - tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); - - /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : - Set STOP[13:12] bits according to USART_StopBits value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; - - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; - -/*---------------------------- USART CR1 Configuration -----------------------*/ - tmpreg = USARTx->CR1; - - /* Clear M, PCE, PS, TE and RE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); - - /* Configure the USART Word Length, Parity and mode: - Set the M bits according to USART_WordLength value - Set PCE and PS bits according to USART_Parity value - Set TE and RE bits according to USART_Mode value */ - tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | - USART_InitStruct->USART_Mode; - - /* Write to USART CR1 */ - USARTx->CR1 = (uint16_t)tmpreg; - -/*---------------------------- USART CR3 Configuration -----------------------*/ - tmpreg = USARTx->CR3; - - /* Clear CTSE and RTSE bits */ - tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); - - /* Configure the USART HFC : - Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ - tmpreg |= USART_InitStruct->USART_HardwareFlowControl; - - /* Write to USART CR3 */ - USARTx->CR3 = (uint16_t)tmpreg; - -/*---------------------------- USART BRR Configuration -----------------------*/ - /* Configure the USART Baud Rate */ - RCC_GetClocksFreq(&RCC_ClocksStatus); - - if ((USARTx == USART1) || (USARTx == USART6)) - { - apbclock = RCC_ClocksStatus.PCLK2_Frequency; - } - else - { - apbclock = RCC_ClocksStatus.PCLK1_Frequency; - } - - /* Determine the integer part */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - /* Integer part computing in case Oversampling mode is 8 Samples */ - integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - /* Integer part computing in case Oversampling mode is 16 Samples */ - integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); - } - tmpreg = (integerdivider / 100) << 4; - - /* Determine the fractional part */ - fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); - - /* Implement the fractional part in the register */ - if ((USARTx->CR1 & USART_CR1_OVER8) != 0) - { - tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); - } - else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ - { - tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); - } - - /* Write to USART BRR register */ - USARTx->BRR = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_InitStruct member with its default value. - * @param USART_InitStruct: pointer to a USART_InitTypeDef structure which will - * be initialized. - * @retval None - */ -void USART_StructInit(USART_InitTypeDef* USART_InitStruct) -{ - /* USART_InitStruct members default value */ - USART_InitStruct->USART_BaudRate = 9600; - USART_InitStruct->USART_WordLength = USART_WordLength_8b; - USART_InitStruct->USART_StopBits = USART_StopBits_1; - USART_InitStruct->USART_Parity = USART_Parity_No ; - USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; -} - -/** - * @brief Initializes the USARTx peripheral Clock according to the - * specified parameters in the USART_ClockInitStruct . - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that - * contains the configuration information for the specified USART peripheral. - * @note The Smart Card and Synchronous modes are not available for UART4 and UART5. - * @retval None - */ -void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - uint32_t tmpreg = 0x00; - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock)); - assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL)); - assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA)); - assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit)); - -/*---------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = USARTx->CR2; - /* Clear CLKEN, CPOL, CPHA and LBCL bits */ - tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK); - /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/ - /* Set CLKEN bit according to USART_Clock value */ - /* Set CPOL bit according to USART_CPOL value */ - /* Set CPHA bit according to USART_CPHA value */ - /* Set LBCL bit according to USART_LastBit value */ - tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | - USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; - /* Write to USART CR2 */ - USARTx->CR2 = (uint16_t)tmpreg; -} - -/** - * @brief Fills each USART_ClockInitStruct member with its default value. - * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure - * which will be initialized. - * @retval None - */ -void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct) -{ - /* USART_ClockInitStruct members default value */ - USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; - USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; - USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; - USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; -} - -/** - * @brief Enables or disables the specified USART peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USARTx peripheral. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the selected USART by setting the UE bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_UE; - } - else - { - /* Disable the selected USART by clearing the UE bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); - } -} - -/** - * @brief Sets the system clock prescaler. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Prescaler: specifies the prescaler clock. - * @note The function is used for IrDA mode with UART4 and UART5. - * @retval None - */ -void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Clear the USART prescaler */ - USARTx->GTPR &= USART_GTPR_GT; - /* Set the USART prescaler */ - USARTx->GTPR |= USART_Prescaler; -} - -/** - * @brief Enables or disables the USART's 8x oversampling mode. - * @note This function has to be called before calling USART_Init() function - * in order to have correct baudrate Divider value. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART 8x oversampling mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_OVER8; - } - else - { - /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8); - } -} - -/** - * @brief Enables or disables the USART's one bit sampling method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART one bit sampling method. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_ONEBIT; - } - else - { - /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group2 Data transfers functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Data transfers functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART data - transfers. - [..] - During an USART reception, data shifts in least significant bit first through - the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) - between the internal bus and the received shift register. - [..] - When a transmission is taking place, a write instruction to the USART_DR register - stores the data in the TDR register and which is copied in the shift register - at the end of the current transmission. - [..] - The read access of the USART_DR register can be done using the USART_ReceiveData() - function and returns the RDR buffered value. Whereas a write access to the USART_DR - can be done using USART_SendData() function and stores the written data into - TDR buffer. - -@endverbatim - * @{ - */ - -/** - * @brief Transmits single data through the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param Data: the data to transmit. - * @retval None - */ -void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DATA(Data)); - - /* Transmit Data */ - USARTx->DR = (Data & (uint16_t)0x01FF); -} - -/** - * @brief Returns the most recent received data by the USARTx peripheral. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval The received data. - */ -uint16_t USART_ReceiveData(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Receive Data */ - return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); -} - -/** - * @} - */ - -/** @defgroup USART_Group3 MultiProcessor Communication functions - * @brief Multi-Processor Communication functions - * -@verbatim - =============================================================================== - ##### Multi-Processor Communication functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - multiprocessor communication. - [..] - For instance one of the USARTs can be the master, its TX output is connected - to the RX input of the other USART. The others are slaves, their respective - TX outputs are logically ANDed together and connected to the RX input of the - master. - [..] - USART multiprocessor communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode - transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark) - using USART_WakeUpConfig() function only for the slaves. - (#) Enable the USART using the USART_Cmd() function. - (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function. - [..] - The USART Slave exit from mute mode when receive the wake up condition. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the address of the USART node. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_Address: Indicates the address of the USART node. - * @retval None - */ -void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_ADDRESS(USART_Address)); - - /* Clear the USART address */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD); - /* Set the USART address node */ - USARTx->CR2 |= USART_Address; -} - -/** - * @brief Determines if the USART is in mute mode or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART mute mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - USARTx->CR1 |= USART_CR1_RWU; - } - else - { - /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU); - } -} -/** - * @brief Selects the USART WakeUp method. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_WakeUp: specifies the USART wakeup method. - * This parameter can be one of the following values: - * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection - * @arg USART_WakeUp_AddressMark: WakeUp by an address mark - * @retval None - */ -void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_WAKEUP(USART_WakeUp)); - - USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE); - USARTx->CR1 |= USART_WakeUp; -} - -/** - * @} - */ - -/** @defgroup USART_Group4 LIN mode functions - * @brief LIN mode functions - * -@verbatim - =============================================================================== - ##### LIN mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART LIN - Mode communication. - [..] - In LIN mode, 8-bit data format with 1 stop bit is required in accordance with - the LIN standard. - [..] - Only this LIN Feature is supported by the USART IP: - (+) LIN Master Synchronous Break send capability and LIN slave break detection - capability : 13-bit break generation and 10/11 bit break detection - - [..] - USART LIN Master transmitter communication is possible through the following - procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the LIN mode using the USART_LINCmd() function. - (#) Send the break character using USART_SendBreak() function. - [..] - USART LIN Master receiver communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, - Mode transmitter or Mode receiver and hardware flow control values using - the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the break detection length using the USART_LINBreakDetectLengthConfig() - function. - (#) Enable the LIN mode using the USART_LINCmd() function. - - -@- In LIN mode, the following bits must be kept cleared: - (+@) CLKEN in the USART_CR2 register, - (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Sets the USART LIN Break detection length. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_LINBreakDetectLength: specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg USART_LINBreakDetectLength_10b: 10-bit break detection - * @arg USART_LINBreakDetectLength_11b: 11-bit break detection - * @retval None - */ -void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength)); - - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL); - USARTx->CR2 |= USART_LINBreakDetectLength; -} - -/** - * @brief Enables or disables the USART's LIN mode. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART LIN mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - USARTx->CR2 |= USART_CR2_LINEN; - } - else - { - /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */ - USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN); - } -} - -/** - * @brief Transmits break characters. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @retval None - */ -void USART_SendBreak(USART_TypeDef* USARTx) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - - /* Send break characters */ - USARTx->CR1 |= USART_CR1_SBK; -} - -/** - * @} - */ - -/** @defgroup USART_Group5 Halfduplex mode function - * @brief Half-duplex mode function - * -@verbatim - =============================================================================== - ##### Half-duplex mode function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Half-duplex communication. - [..] - The USART can be configured to follow a single-wire half-duplex protocol where - the TX and RX lines are internally connected. - [..] - USART Half duplex communication is possible through the following procedure: - (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter - or Mode receiver and hardware flow control values using the USART_Init() - function. - (#) Configures the USART address using the USART_SetAddress() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Enable the half duplex mode using USART_HalfDuplexCmd() function. - - - -@- The RX pin is no longer used - -@- In Half-duplex mode the following bits must be kept cleared: - (+@) LINEN and CLKEN bits in the USART_CR2 register. - (+@) SCEN and IREN bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's Half Duplex communication. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the USART Communication. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_HDSEL; - } - else - { - /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL); - } -} - -/** - * @} - */ - - -/** @defgroup USART_Group6 Smartcard mode functions - * @brief Smartcard mode functions - * -@verbatim - =============================================================================== - ##### Smartcard mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - Smartcard communication. - [..] - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. - [..] - The USART can provide a clock to the smartcard through the SCLK output. - In smartcard mode, SCLK is not associated to the communication but is simply derived - from the internal peripheral input clock through a 5-bit prescaler. - [..] - Smartcard communication is possible through the following procedure: - (#) Configures the Smartcard Prescaler using the USART_SetPrescaler() function. - (#) Configures the Smartcard Guard Time using the USART_SetGuardTime() function. - (#) Program the USART clock using the USART_ClockInit() function as following: - (++) USART Clock enabled - (++) USART CPOL Low - (++) USART CPHA on first edge - (++) USART Last Bit Clock Enabled - (#) Program the Smartcard interface using the USART_Init() function as following: - (++) Word Length = 9 Bits - (++) 1.5 Stop Bit - (++) Even parity - (++) BaudRate = 12096 baud - (++) Hardware flow control disabled (RTS and CTS signals) - (++) Tx and Rx enabled - (#) POptionally you can enable the parity error interrupt using the USART_ITConfig() - function - (#) PEnable the USART using the USART_Cmd() function. - (#) PEnable the Smartcard NACK using the USART_SmartCardNACKCmd() function. - (#) PEnable the Smartcard interface using the USART_SmartCardCmd() function. - - Please refer to the ISO 7816-3 specification for more details. - - -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended - to use 1.5 stop bits for both transmitting and receiving to avoid switching - between the two configurations. - -@- In smartcard mode, the following bits must be kept cleared: - (+@) LINEN bit in the USART_CR2 register. - (+@) HDSEL and IREN bits in the USART_CR3 register. - -@- Smartcard mode is available on USART peripherals only (not available on UART4 - and UART5 peripherals). - -@endverbatim - * @{ - */ - -/** - * @brief Sets the specified USART guard time. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param USART_GuardTime: specifies the guard time. - * @retval None - */ -void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - - /* Clear the USART Guard time */ - USARTx->GTPR &= USART_GTPR_PSC; - /* Set the USART guard time */ - USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); -} - -/** - * @brief Enables or disables the USART's Smart Card mode. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the Smart Card mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the SC mode by setting the SCEN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_SCEN; - } - else - { - /* Disable the SC mode by clearing the SCEN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN); - } -} - -/** - * @brief Enables or disables NACK transmission. - * @param USARTx: where x can be 1, 2, 3 or 6 to select the USART or - * UART peripheral. - * @param NewState: new state of the NACK transmission. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_1236_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - /* Enable the NACK transmission by setting the NACK bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_NACK; - } - else - { - /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group7 IrDA mode functions - * @brief IrDA mode functions - * -@verbatim - =============================================================================== - ##### IrDA mode functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the USART - IrDA communication. - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - [..] - IrDA communication is possible through the following procedure: - (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver - modes and hardware flow control values using the USART_Init() function. - (#) Enable the USART using the USART_Cmd() function. - (#) Configures the IrDA pulse width by configuring the prescaler using - the USART_SetPrescaler() function. - (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode - using the USART_IrDAConfig() function. - (#) Enable the IrDA using the USART_IrDACmd() function. - - -@- A pulse of width less than two and greater than one PSC period(s) may or may - not be rejected. - -@- The receiver set up time should be managed by software. The IrDA physical layer - specification specifies a minimum of 10 ms delay between transmission and - reception (IrDA is a half duplex protocol). - -@- In IrDA mode, the following bits must be kept cleared: - (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register. - (+@) SCEN and HDSEL bits in the USART_CR3 register. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IrDAMode: specifies the IrDA mode. - * This parameter can be one of the following values: - * @arg USART_IrDAMode_LowPower - * @arg USART_IrDAMode_Normal - * @retval None - */ -void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_IRDA_MODE(USART_IrDAMode)); - - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP); - USARTx->CR3 |= USART_IrDAMode; -} - -/** - * @brief Enables or disables the USART's IrDA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param NewState: new state of the IrDA mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the IrDA mode by setting the IREN bit in the CR3 register */ - USARTx->CR3 |= USART_CR3_IREN; - } - else - { - /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */ - USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN); - } -} - -/** - * @} - */ - -/** @defgroup USART_Group8 DMA transfers management functions - * @brief DMA transfers management functions - * -@verbatim - =============================================================================== - ##### DMA transfers management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the USART's DMA interface. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_DMAReq: specifies the DMA request. - * This parameter can be any combination of the following values: - * @arg USART_DMAReq_Tx: USART DMA transmit request - * @arg USART_DMAReq_Rx: USART DMA receive request - * @param NewState: new state of the DMA Request sources. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_DMAREQ(USART_DMAReq)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the DMA transfer for selected requests by setting the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 |= USART_DMAReq; - } - else - { - /* Disable the DMA transfer for selected requests by clearing the DMAT and/or - DMAR bits in the USART CR3 register */ - USARTx->CR3 &= (uint16_t)~USART_DMAReq; - } -} - -/** - * @} - */ - -/** @defgroup USART_Group9 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to configure the USART - Interrupts sources, DMA channels requests and check or clear the flags or - pending bits status. - The user should identify which mode will be used in his application to manage - the communication: Polling mode, Interrupt mode or DMA mode. - - *** Polling Mode *** - ==================== - [..] - In Polling Mode, the SPI communication can be managed by 10 flags: - (#) USART_FLAG_TXE : to indicate the status of the transmit buffer register - (#) USART_FLAG_RXNE : to indicate the status of the receive buffer register - (#) USART_FLAG_TC : to indicate the status of the transmit operation - (#) USART_FLAG_IDLE : to indicate the status of the Idle Line - (#) USART_FLAG_CTS : to indicate the status of the nCTS input - (#) USART_FLAG_LBD : to indicate the status of the LIN break detection - (#) USART_FLAG_NE : to indicate if a noise error occur - (#) USART_FLAG_FE : to indicate if a frame error occur - (#) USART_FLAG_PE : to indicate if a parity error occur - (#) USART_FLAG_ORE : to indicate if an Overrun error occur - [..] - In this Mode it is advised to use the following functions: - (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); - (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); - - *** Interrupt Mode *** - ====================== - [..] - In Interrupt Mode, the USART communication can be managed by 8 interrupt sources - and 10 pending bits: - - (#) Pending Bits: - - (##) USART_IT_TXE : to indicate the status of the transmit buffer register - (##) USART_IT_RXNE : to indicate the status of the receive buffer register - (##) USART_IT_TC : to indicate the status of the transmit operation - (##) USART_IT_IDLE : to indicate the status of the Idle Line - (##) USART_IT_CTS : to indicate the status of the nCTS input - (##) USART_IT_LBD : to indicate the status of the LIN break detection - (##) USART_IT_NE : to indicate if a noise error occur - (##) USART_IT_FE : to indicate if a frame error occur - (##) USART_IT_PE : to indicate if a parity error occur - (##) USART_IT_ORE : to indicate if an Overrun error occur - - (#) Interrupt Source: - - (##) USART_IT_TXE : specifies the interrupt source for the Tx buffer empty - interrupt. - (##) USART_IT_RXNE : specifies the interrupt source for the Rx buffer not - empty interrupt. - (##) USART_IT_TC : specifies the interrupt source for the Transmit complete - interrupt. - (##) USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt. - (##) USART_IT_CTS : specifies the interrupt source for the CTS interrupt. - (##) USART_IT_LBD : specifies the interrupt source for the LIN break detection - interrupt. - (##) USART_IT_PE : specifies the interrupt source for the parity error interrupt. - (##) USART_IT_ERR : specifies the interrupt source for the errors interrupt. - - -@@- Some parameters are coded in order to use them as interrupt source - or as pending bits. - [..] - In this Mode it is advised to use the following functions: - (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); - (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); - (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); - - *** DMA Mode *** - ================ - [..] - In DMA Mode, the USART communication can be managed by 2 DMA Channel requests: - (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request - (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request - [..] - In this Mode it is advised to use the following function: - (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); - -@endverbatim - * @{ - */ - -/** - * @brief Enables or disables the specified USART interrupts. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error) - * @param NewState: new state of the specified USARTx interrupts. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) -{ - uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; - uint32_t usartxbase = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CONFIG_IT(USART_IT)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - usartxbase = (uint32_t)USARTx; - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - - /* Get the interrupt position */ - itpos = USART_IT & IT_MASK; - itmask = (((uint32_t)0x01) << itpos); - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - usartxbase += 0x0C; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - usartxbase += 0x10; - } - else /* The IT is in CR3 register */ - { - usartxbase += 0x14; - } - if (NewState != DISABLE) - { - *(__IO uint32_t*)usartxbase |= itmask; - } - else - { - *(__IO uint32_t*)usartxbase &= ~itmask; - } -} - -/** - * @brief Checks whether the specified USART flag is set or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to check. - * This parameter can be one of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5) - * @arg USART_FLAG_LBD: LIN Break detection flag - * @arg USART_FLAG_TXE: Transmit data register empty flag - * @arg USART_FLAG_TC: Transmission Complete flag - * @arg USART_FLAG_RXNE: Receive data register not empty flag - * @arg USART_FLAG_IDLE: Idle Line detection flag - * @arg USART_FLAG_ORE: OverRun Error flag - * @arg USART_FLAG_NE: Noise Error flag - * @arg USART_FLAG_FE: Framing Error flag - * @arg USART_FLAG_PE: Parity Error flag - * @retval The new state of USART_FLAG (SET or RESET). - */ -FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - FlagStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if (USART_FLAG == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears the USARTx's pending flags. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_FLAG: specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg USART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5). - * @arg USART_FLAG_LBD: LIN Break detection flag. - * @arg USART_FLAG_TC: Transmission Complete flag. - * @arg USART_FLAG_RXNE: Receive data register not empty flag. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) flags are cleared by software - * sequence: a read operation to USART_SR register (USART_GetFlagStatus()) - * followed by a read operation to USART_DR register (USART_ReceiveData()). - * @note RXNE flag can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC flag can be also cleared by software sequence: a read operation to - * USART_SR register (USART_GetFlagStatus()) followed by a write operation - * to USART_DR register (USART_SendData()). - * @note TXE flag is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG) -{ - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); - - /* The CTS flag is not available for UART4 and UART5 */ - if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - USARTx->SR = (uint16_t)~USART_FLAG; -} - -/** - * @brief Checks whether the specified USART interrupt has occurred or not. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TXE: Transmit Data Register empty interrupt - * @arg USART_IT_TC: Transmission complete interrupt - * @arg USART_IT_RXNE: Receive Data register not empty interrupt - * @arg USART_IT_IDLE: Idle line detection interrupt - * @arg USART_IT_ORE_RX : OverRun Error interrupt if the RXNEIE bit is set - * @arg USART_IT_ORE_ER : OverRun Error interrupt if the EIE bit is set - * @arg USART_IT_NE: Noise Error interrupt - * @arg USART_IT_FE: Framing Error interrupt - * @arg USART_IT_PE: Parity Error interrupt - * @retval The new state of USART_IT (SET or RESET). - */ -ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; - ITStatus bitstatus = RESET; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_GET_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - /* Get the USART register index */ - usartreg = (((uint8_t)USART_IT) >> 0x05); - /* Get the interrupt position */ - itmask = USART_IT & IT_MASK; - itmask = (uint32_t)0x01 << itmask; - - if (usartreg == 0x01) /* The IT is in CR1 register */ - { - itmask &= USARTx->CR1; - } - else if (usartreg == 0x02) /* The IT is in CR2 register */ - { - itmask &= USARTx->CR2; - } - else /* The IT is in CR3 register */ - { - itmask &= USARTx->CR3; - } - - bitpos = USART_IT >> 0x08; - bitpos = (uint32_t)0x01 << bitpos; - bitpos &= USARTx->SR; - if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET)) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - - return bitstatus; -} - -/** - * @brief Clears the USARTx's interrupt pending bits. - * @param USARTx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or - * UART peripheral. - * @param USART_IT: specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg USART_IT_CTS: CTS change interrupt (not available for UART4 and UART5) - * @arg USART_IT_LBD: LIN Break detection interrupt - * @arg USART_IT_TC: Transmission complete interrupt. - * @arg USART_IT_RXNE: Receive Data register not empty interrupt. - * - * @note PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun - * error) and IDLE (Idle line detected) pending bits are cleared by - * software sequence: a read operation to USART_SR register - * (USART_GetITStatus()) followed by a read operation to USART_DR register - * (USART_ReceiveData()). - * @note RXNE pending bit can be also cleared by a read to the USART_DR register - * (USART_ReceiveData()). - * @note TC pending bit can be also cleared by software sequence: a read - * operation to USART_SR register (USART_GetITStatus()) followed by a write - * operation to USART_DR register (USART_SendData()). - * @note TXE pending bit is cleared only by a write to the USART_DR register - * (USART_SendData()). - * - * @retval None - */ -void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT) -{ - uint16_t bitpos = 0x00, itmask = 0x00; - /* Check the parameters */ - assert_param(IS_USART_ALL_PERIPH(USARTx)); - assert_param(IS_USART_CLEAR_IT(USART_IT)); - - /* The CTS interrupt is not available for UART4 and UART5 */ - if (USART_IT == USART_IT_CTS) - { - assert_param(IS_USART_1236_PERIPH(USARTx)); - } - - bitpos = USART_IT >> 0x08; - itmask = ((uint16_t)0x01 << (uint16_t)bitpos); - USARTx->SR = (uint16_t)~itmask; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c deleted file mode 100644 index 45bf1dda7..000000000 --- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f4xx_wwdg.c - * @author MCD Application Team - * @version V1.8.0 - * @date 04-November-2016 - * @brief This file provides firmware functions to manage the following - * functionalities of the Window watchdog (WWDG) peripheral: - * + Prescaler, Refresh window and Counter configuration - * + WWDG activation - * + Interrupts and flags management - * - @verbatim - =============================================================================== - ##### WWDG features ##### - =============================================================================== - [..] - Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (downcounter) - before to reach 0x3F value (i.e. a reset is generated when the counter - value rolls over from 0x40 to 0x3F). - An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - - Once enabled the WWDG cannot be disabled except by a system reset. - - WWDGRST flag in RCC_CSR register can be used to inform when a WWDG - reset occurs. - - The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - - WWDG counter clock = PCLK1 / Prescaler - WWDG timeout = (WWDG counter clock) * (counter value) - - Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms - - ##### How to use this driver ##### - =============================================================================== - [..] - (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function - - (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function - - (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function - - (#) Set the WWDG counter value and start it using WWDG_Enable() function. - When the WWDG is enabled the counter value should be configured to - a value greater than 0x40 to prevent generating an immediate reset. - - (#) Optionally you can enable the Early wakeup interrupt which is - generated when the counter reach 0x40. - Once enabled this interrupt cannot be disabled except by a system reset. - - (#) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - WWDG_SetCounter() function. This operation must occur only when - the counter value is lower than the refresh window value, - programmed using WWDG_SetWindowValue(). - - @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f4xx_wwdg.h" -#include "stm32f4xx_rcc.h" - -/** @addtogroup STM32F4xx_StdPeriph_Driver - * @{ - */ - -/** @defgroup WWDG - * @brief WWDG driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* ----------- WWDG registers bit address in the alias region ----------- */ -#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) -/* Alias word address of EWI bit */ -#define CFR_OFFSET (WWDG_OFFSET + 0x04) -#define EWI_BitNumber 0x09 -#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) - -/* --------------------- WWDG registers bit mask ------------------------ */ -/* CFR register bit mask */ -#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) -#define CFR_W_MASK ((uint32_t)0xFFFFFF80) -#define BIT_MASK ((uint8_t)0x7F) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions - * @{ - */ - -/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions - * @brief Prescaler, Refresh window and Counter configuration functions - * -@verbatim - =============================================================================== - ##### Prescaler, Refresh window and Counter configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the WWDG peripheral registers to their default reset values. - * @param None - * @retval None - */ -void WWDG_DeInit(void) -{ - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); - RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); -} - -/** - * @brief Sets the WWDG Prescaler. - * @param WWDG_Prescaler: specifies the WWDG Prescaler. - * This parameter can be one of the following values: - * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 - * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 - * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 - * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 - * @retval None - */ -void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) -{ - uint32_t tmpreg = 0; - /* Check the parameters */ - assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); - /* Clear WDGTB[1:0] bits */ - tmpreg = WWDG->CFR & CFR_WDGTB_MASK; - /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ - tmpreg |= WWDG_Prescaler; - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Sets the WWDG window value. - * @param WindowValue: specifies the window value to be compared to the downcounter. - * This parameter value must be lower than 0x80. - * @retval None - */ -void WWDG_SetWindowValue(uint8_t WindowValue) -{ - __IO uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); - /* Clear W[6:0] bits */ - - tmpreg = WWDG->CFR & CFR_W_MASK; - - /* Set W[6:0] bits according to WindowValue value */ - tmpreg |= WindowValue & (uint32_t) BIT_MASK; - - /* Store the new value */ - WWDG->CFR = tmpreg; -} - -/** - * @brief Enables the WWDG Early Wakeup interrupt(EWI). - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @param None - * @retval None - */ -void WWDG_EnableIT(void) -{ - *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; -} - -/** - * @brief Sets the WWDG counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_SetCounter(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - /* Write to T[6:0] bits to configure the counter value, no need to do - a read-modify-write; writing a 0 to WDGA bit does nothing */ - WWDG->CR = Counter & BIT_MASK; -} -/** - * @} - */ - -/** @defgroup WWDG_Group2 WWDG activation functions - * @brief WWDG activation functions - * -@verbatim - =============================================================================== - ##### WWDG activation function ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Enables WWDG and load the counter value. - * @param Counter: specifies the watchdog counter value. - * This parameter must be a number between 0x40 and 0x7F (to prevent generating - * an immediate reset) - * @retval None - */ -void WWDG_Enable(uint8_t Counter) -{ - /* Check the parameters */ - assert_param(IS_WWDG_COUNTER(Counter)); - WWDG->CR = WWDG_CR_WDGA | Counter; -} -/** - * @} - */ - -/** @defgroup WWDG_Group3 Interrupts and flags management functions - * @brief Interrupts and flags management functions - * -@verbatim - =============================================================================== - ##### Interrupts and flags management functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Checks whether the Early Wakeup interrupt flag is set or not. - * @param None - * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) - */ -FlagStatus WWDG_GetFlagStatus(void) -{ - FlagStatus bitstatus = RESET; - - if ((WWDG->SR) != (uint32_t)RESET) - { - bitstatus = SET; - } - else - { - bitstatus = RESET; - } - return bitstatus; -} - -/** - * @brief Clears Early Wakeup interrupt flag. - * @param None - * @retval None - */ -void WWDG_ClearFlag(void) -{ - WWDG->SR = (uint32_t)RESET; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/radio/src/thirdparty/libopenui/src/mainwindow.cpp b/radio/src/thirdparty/libopenui/src/mainwindow.cpp index 29294cbeb..af9c7e9bd 100644 --- a/radio/src/thirdparty/libopenui/src/mainwindow.cpp +++ b/radio/src/thirdparty/libopenui/src/mainwindow.cpp @@ -23,6 +23,9 @@ #include "layout.h" #include "themes/etx_lv_theme.h" +// timers_driver.h +uint32_t timersGetMsTick(); + MainWindow* MainWindow::_instance = nullptr; MainWindow* MainWindow::instance() @@ -51,7 +54,7 @@ void MainWindow::emptyTrash() void MainWindow::run(bool trash) { - auto start = ticksNow(); + auto start = timersGetMsTick(); auto opaque = Layer::getFirstOpaque(); if (opaque) { @@ -67,10 +70,9 @@ void MainWindow::run(bool trash) if (trash) emptyTrash(); - auto delta = ticksNow() - start; - if (delta > 10 * SYSTEM_TICKS_1MS) { - TRACE_WINDOWS("MainWindow::run took %dms", - (ticksNow() - start) / SYSTEM_TICKS_1MS); + auto delta = timersGetMsTick() - start; + if (delta > 10) { + TRACE_WINDOWS("MainWindow::run took %dms", delta); } }