Fixes #1436 - Be careful, there is a conversion on M128/gruvin9x boards,

L13, L14 and L15 are removed
This commit is contained in:
bsongis
2014-07-04 12:23:08 +02:00
parent b8a6548686
commit 711b54c98e
13 changed files with 10 additions and 29 deletions
+4 -4
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@@ -58,10 +58,10 @@
#define EEPROM_VER 216
#define FIRST_CONV_EEPROM_VER 215
#elif defined(CPUM2560) || defined(CPUM2561)
#define EEPROM_VER 216
#define EEPROM_VER 217
#define FIRST_CONV_EEPROM_VER EEPROM_VER
#elif defined(CPUM128)
#define EEPROM_VER 216
#define EEPROM_VER 217
#else
#define EEPROM_VER 216
#endif
@@ -108,7 +108,7 @@
#define MAX_FLIGHT_MODES 6
#define MAX_MIXERS 32
#define MAX_EXPOS 16
#define NUM_LOGICAL_SWITCH 15 // number of custom switches
#define NUM_LOGICAL_SWITCH 12 // number of custom switches
#define NUM_CFN 24 // number of functions assigned to switches
#define NUM_TRAINER 8
#define NUM_POTS 3
@@ -119,7 +119,7 @@
#define MAX_FLIGHT_MODES 5
#define MAX_MIXERS 32
#define MAX_EXPOS 14
#define NUM_LOGICAL_SWITCH 15 // number of custom switches
#define NUM_LOGICAL_SWITCH 12 // number of custom switches
#define NUM_CFN 24 // number of functions assigned to switches
#define NUM_TRAINER 8
#define NUM_POTS 3
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif
-2
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@@ -420,8 +420,6 @@
#if defined(CPUARM)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15""L16""L17""L18""L19""L20""L21""L22""L23""L24""L25""L26""L27""L28""L29""L30""L31""L32"
#elif defined(PCBGRUVIN9X) || defined(CPUM2561) || defined(CPUM128)
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12""L13""L14""L15"
#else
#define TR_LOGICALSW "L1\0""L2\0""L3\0""L4\0""L5\0""L6\0""L7\0""L8\0""L9\0""L10""L11""L12"
#endif