diff --git a/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp b/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp
index ec611b9e5..5e41b7518 100644
--- a/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp
+++ b/radio/src/targets/common/arm/stm32/audio_dac_driver.cpp
@@ -29,87 +29,8 @@
 
 #include "edgetx.h"
 
-
-const AudioBuffer * nextBuffer = nullptr;
-
-#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
-// 16 bit, 1 channels
-#define DMA_BUFFER_HALF_LEN AUDIO_BUFFER_SIZE
-
-// 2 buffers
-#define DMA_BUFFER_LEN (DMA_BUFFER_HALF_LEN * 2)
-
-static uint16_t _dma_buffer[DMA_BUFFER_LEN] __DMA_NO_CACHE;
-
-static volatile uint32_t _dma_buffer_offset = 0;
-
-static inline uint32_t _calc_offset(uint8_t tc)
-{
-  return tc * DMA_BUFFER_HALF_LEN;
-}
-
-// the returned bool is true when there is no more data available
-static bool audio_update_dma_buffer(uint8_t tc)
-{
-  _dma_buffer_offset = _calc_offset(tc);
-
-  auto buffer = audioQueue.buffersFifo.getNextFilledBuffer();
-  nextBuffer = buffer;
-  if (!buffer) {
-    unsigned idx = 0;
-    for (; idx < DMA_BUFFER_HALF_LEN; idx++) {
-      uint32_t offset = _dma_buffer_offset + idx;
-      _dma_buffer[offset] = AUDIO_DATA_SILENCE;
-    }
-    return true;
-  } else {
-    unsigned idx = 0;
-    for (; idx < buffer->size; idx++) {
-      uint32_t offset = _dma_buffer_offset + idx;
-      _dma_buffer[offset] = (uint16_t)buffer->data[idx];
-    }
-    for (; idx < DMA_BUFFER_HALF_LEN; idx++) {
-      uint32_t offset = _dma_buffer_offset + idx;
-      _dma_buffer[offset] = AUDIO_DATA_SILENCE;
-    }
-    audioQueue.buffersFifo.freeNextFilledBuffer();
-    return false;
-  }
-}
-#else
-#define AUDIO_DAC DAC
-#endif
-
-// Init timer that triggers the DAC conversion
-// at sampling frequency
-static void dac_trigger_init()
-{
-  stm32_timer_enable_clock(AUDIO_TIMER);
-
-  // set timer to: 10 uS, 100 kHz
-  AUDIO_TIMER->PSC = 0;
-  AUDIO_TIMER->ARR = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 100000 - 1;
-
-  // reset counter
-  AUDIO_TIMER->CNT = 0;
-
-  // set expiry to sample period (1 / sample_rate)
-  AUDIO_TIMER->ARR =
-      (PERI1_FREQUENCY * TIMER_MULT_APB1) / AUDIO_SAMPLE_RATE - 1;
-
-  // Master mode selection
-  //
-  //  000: Reset
-  AUDIO_TIMER->CR2 = 0;
-  //  010: The update event is selected as trigger output (TRGO)
-  //       (used to trigger DAC conversion)
-  AUDIO_TIMER->CR2 = TIM_CR2_MMS_1;
-
-  // enable timer
-  AUDIO_TIMER->CR1 |= TIM_CR1_CEN;
-}
-
 #if defined(AUDIO_MUTE_GPIO)
+
 static inline void set_mute_pin(bool enabled)
 {
 #if defined(INVERTED_MUTE_PIN)
@@ -126,91 +47,7 @@ static inline bool get_mute_pin(void)
 #endif  
   return enabled;
 }
-#endif
 
-// Configure DAC0
-// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function
-// So maybe it is automatically done
-void dacInit()
-{  
-#if defined(AUDIO_MUTE_GPIO)
-  // Mute before init anything
-  gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW);
-  set_mute_pin(true);
-#endif
-
-  dac_trigger_init();
-
-  gpio_init_analog(AUDIO_OUTPUT_GPIO);
-  stm32_dma_enable_clock(AUDIO_DMA);
-
-#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
-  LL_DMA_DeInit(AUDIO_DMA, AUDIO_DMA_Stream);
-
-  LL_DMA_InitTypeDef dmaInit;
-  LL_DMA_StructInit(&dmaInit);
-
-#if defined(STM32H7)
-  dmaInit.Mode = LL_DMA_MODE_CIRCULAR;
-  dmaInit.PeriphRequest = AUDIO_DMA_Channel;
-  dmaInit.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
-  dmaInit.Priority = LL_DMA_PRIORITY_VERYHIGH;
-  dmaInit.PeriphOrM2MSrcAddress = LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED);
-  dmaInit.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
-  dmaInit.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
-  dmaInit.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
-#elif defined(STM32H7RS)
-  #error not implemented
-#endif
-  LL_DMA_Init(AUDIO_DMA, AUDIO_DMA_Stream, &dmaInit);
-#else
-  // Disable DMA stream
-  AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN;
-
-  // clear DMA stream flags
-  AUDIO_DMA->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 |
-                     DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5;
-
-  // Chan 7, 16-bit wide, Medium priority, memory increments
-  AUDIO_DMA_Stream->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 |
-                         DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 |
-                         DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 |
-                         DMA_SxCR_CIRC;
-
-  // write to DAC channel 1 (12 bits, left-aligned)
-  AUDIO_DMA_Stream->PAR = CONVERT_PTR_UINT(&AUDIO_DAC->DHR12L1);
-
-  // disable direct mode and set FIFO threshold to half
-  AUDIO_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0;
-#endif
-
-#if defined(LL_APB1_GRP1_PERIPH_DAC12)
-  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC12);
-#else
-  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC1);
-#endif
-
-  // set data registre to silence
-  AUDIO_DAC->DHR12L1 = AUDIO_DATA_SILENCE;
-#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
-  LL_DAC_ClearFlag_DMAUDR1(AUDIO_DAC);
-  LL_DAC_SetTriggerSource(AUDIO_DAC, LL_DAC_CHANNEL_1, LL_DAC_TRIG_EXT_TIM6_TRGO);
-  LL_DAC_EnableTrigger(AUDIO_DAC, LL_DAC_CHANNEL_1);
-  LL_DAC_Enable(AUDIO_DAC, LL_DAC_CHANNEL_1);
-
-#else
-  // clear underrun flag
-  AUDIO_DAC->SR = DAC_SR_DMAUDR1;
-
-  // use TIM6 TRGO as trigger (TSEL1 = TSEL2 = 000)
-  // enable DAC & channel 1 trigger
-  AUDIO_DAC->CR = DAC_CR_TEN1 | DAC_CR_EN1;
-#endif
-  NVIC_EnableIRQ(AUDIO_DMA_Stream_IRQn);
-  NVIC_SetPriority(AUDIO_DMA_Stream_IRQn, 7);
-}
-
-#if defined(AUDIO_MUTE_GPIO)
 void audioMute()
 {
   if (!g_eeGeneral.audioMuteEnable) return;
@@ -252,55 +89,113 @@ void audioUnmute()
 }
 #endif
 
+#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
+
+#define DAC_TRIGGER LL_DAC_TRIG_EXT_TIM6_TRGO
+
+// 16 bit, 1 channels
+#define DMA_BUFFER_HALF_LEN AUDIO_BUFFER_SIZE
+
+// 2 buffers
+#define DMA_BUFFER_LEN (DMA_BUFFER_HALF_LEN * 2)
+
+static uint16_t _dma_buffer[DMA_BUFFER_LEN] __DMA_NO_CACHE;
+
+static volatile uint32_t _dma_buffer_offset = 0;
+
+static inline uint32_t _calc_offset(uint8_t tc)
+{
+  return tc * DMA_BUFFER_HALF_LEN;
+}
+
+// return true if no more data available
+static bool audio_update_dma_buffer(uint8_t tc)
+{
+  _dma_buffer_offset = _calc_offset(tc);
+
+  auto buffer = audioQueue.buffersFifo.getNextFilledBuffer();
+  if (!buffer) {
+    unsigned idx = 0;
+    for (; idx < DMA_BUFFER_HALF_LEN; idx++) {
+      uint32_t offset = _dma_buffer_offset + idx;
+      _dma_buffer[offset] = AUDIO_DATA_SILENCE;
+    }
+    return true;
+  } else {
+    unsigned idx = 0;
+    for (; idx < buffer->size; idx++) {
+      uint32_t offset = _dma_buffer_offset + idx;
+      _dma_buffer[offset] = (uint16_t)buffer->data[idx];
+    }
+    for (; idx < DMA_BUFFER_HALF_LEN; idx++) {
+      uint32_t offset = _dma_buffer_offset + idx;
+      _dma_buffer[offset] = AUDIO_DATA_SILENCE;
+    }
+    audioQueue.buffersFifo.freeNextFilledBuffer();
+    return false;
+  }
+}
+
+static void dac_dma_init()
+{
+  stm32_dma_enable_clock(AUDIO_DMA);
+
+  LL_DMA_DeInit(AUDIO_DMA, AUDIO_DMA_Stream);
+
+  LL_DMA_InitTypeDef dmaInit;
+  LL_DMA_StructInit(&dmaInit);
+
+#if defined(STM32H7)
+  dmaInit.Mode = LL_DMA_MODE_CIRCULAR;
+  dmaInit.PeriphRequest = AUDIO_DMA_Channel;
+  dmaInit.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH;
+  dmaInit.Priority = LL_DMA_PRIORITY_VERYHIGH;
+  dmaInit.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT;
+  dmaInit.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_HALFWORD;
+  dmaInit.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_HALFWORD;
+  dmaInit.PeriphOrM2MSrcAddress = LL_DAC_DMA_GetRegAddr(
+      DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED);
+  dmaInit.MemoryOrM2MDstAddress = (uintptr_t)_dma_buffer;
+  dmaInit.NbData = DMA_BUFFER_LEN;
+#elif defined(STM32H7RS)
+  #error not implemented
+#endif
+  LL_DMA_Init(AUDIO_DMA, AUDIO_DMA_Stream, &dmaInit);
+
+  NVIC_EnableIRQ(AUDIO_DMA_Stream_IRQn);
+  NVIC_SetPriority(AUDIO_DMA_Stream_IRQn, 7);
+}
+
+static void dac_close_dma_xfer()
+{
+  LL_DMA_DisableIT_TC(AUDIO_DMA, AUDIO_DMA_Stream);
+  LL_DMA_DisableIT_HT(AUDIO_DMA, AUDIO_DMA_Stream);
+  // TODO: reset flags
+  LL_DMA_DisableStream(AUDIO_DMA, AUDIO_DMA_Stream);
+}
+
+static void dac_start_dma()
+{
+  // enable DMA stream and transfer complete interrupt
+  LL_DMA_EnableIT_HT(AUDIO_DMA, AUDIO_DMA_Stream);
+  LL_DMA_EnableIT_TC(AUDIO_DMA, AUDIO_DMA_Stream);
+  LL_DMA_EnableStream(AUDIO_DMA, AUDIO_DMA_Stream);
+
+  // clear underrun flag
+  LL_DAC_ClearFlag_DMAUDR1(AUDIO_DAC);
+
+  // enable DAC
+  AUDIO_DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1;
+}
+
 void audioConsumeCurrentBuffer()
 {
-#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
   if (!LL_DMA_IsEnabledStream(AUDIO_DMA, AUDIO_DMA_Stream)) {
     if (!audio_update_dma_buffer(0)) {
 #if defined(AUDIO_MUTE_GPIO)
       audioUnmute();
 #endif
-
-      LL_DMA_DisableStream(AUDIO_DMA, AUDIO_DMA_Stream);
-      stm32_dma_check_tc_flag(AUDIO_DMA, AUDIO_DMA_Stream);
-      stm32_dma_check_ht_flag(AUDIO_DMA, AUDIO_DMA_Stream);
-      LL_DAC_ClearFlag_DMAUDR1(AUDIO_DAC);
-      LL_DAC_EnableDMAReq(AUDIO_DAC, LL_DAC_CHANNEL_1);
-      LL_DAC_Enable(AUDIO_DAC, LL_DAC_CHANNEL_1);
-      LL_DMA_SetMemoryAddress(AUDIO_DMA, AUDIO_DMA_Stream, (intptr_t)_dma_buffer);
-      LL_DMA_SetDataLength(AUDIO_DMA, AUDIO_DMA_Stream, DMA_BUFFER_LEN);
-      LL_DMA_EnableStream(AUDIO_DMA, AUDIO_DMA_Stream);
-      LL_DMA_EnableIT_HT(AUDIO_DMA, AUDIO_DMA_Stream);
-      LL_DMA_EnableIT_TC(AUDIO_DMA, AUDIO_DMA_Stream);
-#else
-  if (!nextBuffer) {
-    nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer();
-    if (nextBuffer) {
-
-#if defined(AUDIO_MUTE_GPIO)
-      audioUnmute();
-#endif
-      // Disable DMA stream
-      AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN;
-
-      // reset DMA flags
-      AUDIO_DMA->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 |
-                         DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 |
-                         DMA_HIFCR_CFEIF5;
-
-      // set DMA buffer
-      AUDIO_DMA_Stream->M0AR = CONVERT_PTR_UINT(nextBuffer->data);
-      AUDIO_DMA_Stream->NDTR = nextBuffer->size;
-
-      // enable DMA stream and transfer complete interrupt
-      AUDIO_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE;
-
-      // clear underrun flag
-      AUDIO_DAC->SR = DAC_SR_DMAUDR1;
-
-      // enable DAC
-      AUDIO_DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1;
-#endif
+      dac_start_dma();
     } else {
 #if defined(AUDIO_MUTE_GPIO)
       audioMute();
@@ -309,25 +204,8 @@ void audioConsumeCurrentBuffer()
   }
 }
 
-// Sound routines
-void audioInit()
-{
-  dacInit();
-}
-
-void audioEnd()
-{
-  AUDIO_DAC->CR = 0;
-  AUDIO_TIMER->CR1 = 0;
-
-  // Also need to turn off any possible interrupts
-  NVIC_DisableIRQ(AUDIO_TIM_IRQn);
-  NVIC_DisableIRQ(AUDIO_DMA_Stream_IRQn);
-}
-
 extern "C" void AUDIO_DMA_Stream_IRQHandler()
 {
-#if defined(STM32H5) || defined(STM32H7) || defined(STM32H7RS)
   bool stopDMA = false;
   if(stm32_dma_check_ht_flag(AUDIO_DMA, AUDIO_DMA_Stream)) {
     stopDMA = audio_update_dma_buffer(0);
@@ -338,12 +216,45 @@ extern "C" void AUDIO_DMA_Stream_IRQHandler()
   }
 
   if(stopDMA) {
-    LL_DMA_DisableIT_TC(AUDIO_DMA, AUDIO_DMA_Stream);
-    LL_DMA_DisableIT_HT(AUDIO_DMA, AUDIO_DMA_Stream);
-    LL_DMA_DisableStream(AUDIO_DMA, AUDIO_DMA_Stream);
+    dac_close_dma_xfer();
   }
+}
 
-#else
+#else // STM32H5 || STM32H7 || STM32H7RS
+
+#define AUDIO_DAC DAC
+#define DAC_TRIGGER 0 // TIM6
+
+const AudioBuffer * nextBuffer = nullptr;
+
+static void dac_dma_init()
+{
+  stm32_dma_enable_clock(AUDIO_DMA);
+
+  // Disable DMA stream
+  AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN;
+
+  // clear DMA stream flags
+  AUDIO_DMA->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 |
+                     DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5;
+
+  // Chan 7, 16-bit wide, Medium priority, memory increments
+  AUDIO_DMA_Stream->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 |
+                         DMA_SxCR_CHSEL_2 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0 |
+                         DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0;
+
+  // write to DAC channel 1 (12 bits, left-aligned)
+  AUDIO_DMA_Stream->PAR = CONVERT_PTR_UINT(&AUDIO_DAC->DHR12L1);
+
+  // disable direct mode and set FIFO threshold to half
+  AUDIO_DMA_Stream->FCR = DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0;
+
+  NVIC_EnableIRQ(AUDIO_DMA_Stream_IRQn);
+  NVIC_SetPriority(AUDIO_DMA_Stream_IRQn, 7);
+}
+
+static void dac_close_dma_xfer()
+{
   // disable transfer complete interrupt
   AUDIO_DMA_Stream->CR &= ~DMA_SxCR_TCIE;
 
@@ -352,25 +263,127 @@ extern "C" void AUDIO_DMA_Stream_IRQHandler()
                      DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5;
 
   // Disable DMA stream
-  AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN;
+  AUDIO_DMA_Stream->CR &= ~DMA_SxCR_EN;  
+}
+
+static void dac_start_dma_request(const audio_data_t* data, uint16_t length)
+{
+  // set DMA buffer
+  AUDIO_DMA_Stream->M0AR = CONVERT_PTR_UINT(data);
+  AUDIO_DMA_Stream->NDTR = length;
+
+  // enable DMA stream and transfer complete interrupt
+  AUDIO_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE;
+
+  // clear underrun flag
+  AUDIO_DAC->SR = DAC_SR_DMAUDR1;
+
+  // enable DAC
+  AUDIO_DAC->CR |= DAC_CR_EN1 | DAC_CR_DMAEN1;  
+}
+
+void audioConsumeCurrentBuffer()
+{
+  if (!nextBuffer) {
+    nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer();
+    if (nextBuffer) {
+
+#if defined(AUDIO_MUTE_GPIO)
+      audioUnmute();
+#endif
+      dac_close_dma_xfer();
+      dac_start_dma_request(nextBuffer->data, nextBuffer->size);
+    } else {
+#if defined(AUDIO_MUTE_GPIO)
+      audioMute();
+#endif
+    }
+  }
+}
+
+extern "C" void AUDIO_DMA_Stream_IRQHandler()
+{
+  dac_close_dma_xfer();
 
   // get next buffer if any
   if (nextBuffer) audioQueue.buffersFifo.freeNextFilledBuffer();
   nextBuffer = audioQueue.buffersFifo.getNextFilledBuffer();
 
   if (nextBuffer) {
-    AUDIO_DMA_Stream->M0AR = CONVERT_PTR_UINT(nextBuffer->data);
-    AUDIO_DMA_Stream->NDTR = nextBuffer->size;
-
-    // reset DMA flags (again?)
-    AUDIO_DMA->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 |
-                       DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5;
-
-    // enable DMA stream and transfer complete interrupt
-    AUDIO_DMA_Stream->CR |= DMA_SxCR_EN | DMA_SxCR_TCIE;
-
-    // clear underrun flag
-    AUDIO_DAC->SR = DAC_SR_DMAUDR1;
+    dac_start_dma_request(nextBuffer->data, nextBuffer->size);
   }
+}
+
 #endif
+
+// Init timer that triggers the DAC conversion
+// at sampling frequency
+static void dac_trigger_init()
+{
+  stm32_timer_enable_clock(AUDIO_TIMER);
+
+  // set timer to: 10 uS, 100 kHz
+  AUDIO_TIMER->PSC = 0;
+  AUDIO_TIMER->ARR = (PERI1_FREQUENCY * TIMER_MULT_APB1) / 100000 - 1;
+
+  // reset counter
+  AUDIO_TIMER->CNT = 0;
+
+  // set expiry to sample period (1 / sample_rate)
+  AUDIO_TIMER->ARR =
+      (PERI1_FREQUENCY * TIMER_MULT_APB1) / AUDIO_SAMPLE_RATE - 1;
+
+  // Master mode selection
+  //
+  //  000: Reset
+  AUDIO_TIMER->CR2 = 0;
+  //  010: The update event is selected as trigger output (TRGO)
+  //       (used to trigger DAC conversion)
+  AUDIO_TIMER->CR2 = TIM_CR2_MMS_1;
+
+  // enable timer
+  AUDIO_TIMER->CR1 |= TIM_CR1_CEN;
+}
+
+static void dac_periph_init()
+{
+#if defined(LL_APB1_GRP1_PERIPH_DAC12)
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC12);
+#else
+  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC1);
+#endif
+
+  gpio_init_analog(AUDIO_OUTPUT_GPIO);
+
+  // set data registre to silence
+  AUDIO_DAC->DHR12L1 = AUDIO_DATA_SILENCE;
+
+  // clear underrun flag
+  AUDIO_DAC->SR = DAC_SR_DMAUDR1;
+
+  // use TIM6 TRGO as trigger
+  // enable DAC & channel 1 trigger
+  AUDIO_DAC->CR = DAC_CR_TEN1 | DAC_CR_EN1 | DAC_TRIGGER;
+}
+
+// Configure DAC0
+// Not sure why PB14 has not be allocated to the DAC, although it is an EXTRA function
+// So maybe it is automatically done
+void dacInit()
+{  
+#if defined(AUDIO_MUTE_GPIO)
+  // Mute before init anything
+  gpio_init(AUDIO_MUTE_GPIO, GPIO_OUT, GPIO_PIN_SPEED_LOW);
+  set_mute_pin(true);
+#endif
+
+  dac_trigger_init();
+  dac_dma_init();
+  dac_periph_init();
+}
+
+// Sound routines
+void audioInit()
+{
+  dacInit();
 }
diff --git a/radio/src/targets/horus/hal.h b/radio/src/targets/horus/hal.h
index d98bc7691..c6bd46651 100644
--- a/radio/src/targets/horus/hal.h
+++ b/radio/src/targets/horus/hal.h
@@ -911,8 +911,6 @@
   #define AUDIO_OUTPUT_GPIO             GPIO_PIN(GPIOA, 4) // PA.04
   #define AUDIO_DMA_Stream              DMA1_Stream5
   #define AUDIO_DMA_Stream_IRQn         DMA1_Stream5_IRQn
-  #define AUDIO_TIM_IRQn                TIM6_DAC_IRQn
-  #define AUDIO_TIM_IRQHandler          TIM6_DAC_IRQHandler
   #define AUDIO_DMA_Stream_IRQHandler   DMA1_Stream5_IRQHandler
   #define AUDIO_TIMER                   TIM6
   #define AUDIO_DMA                     DMA1
diff --git a/radio/src/targets/pl18/hal.h b/radio/src/targets/pl18/hal.h
index 9da09e827..cf38a6025 100644
--- a/radio/src/targets/pl18/hal.h
+++ b/radio/src/targets/pl18/hal.h
@@ -677,13 +677,9 @@
   #define AUDIO_SPI_MISO_GPIO           GPIO_PIN(GPIOB, 4)  // PB.04
   #define AUDIO_SPI_MOSI_GPIO           GPIO_PIN(GPIOB, 5)  // PB.05
 #else
-  #define AUDIO_RCC_APB1Periph            (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC)
-  #define AUDIO_RCC_AHB1Periph            (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1)
   #define AUDIO_OUTPUT_GPIO               GPIO_PIN(GPIOA, 4)  // PA.04
   #define AUDIO_DMA_Stream                DMA1_Stream5
   #define AUDIO_DMA_Stream_IRQn           DMA1_Stream5_IRQn
-  #define AUDIO_TIM_IRQn                  TIM6_DAC_IRQn
-  #define AUDIO_TIM_IRQHandler            TIM6_DAC_IRQHandler
   #define AUDIO_DMA_Stream_IRQHandler     DMA1_Stream5_IRQHandler
   #define AUDIO_TIMER                     TIM6
   #define AUDIO_DMA                       DMA1
diff --git a/radio/src/targets/stm32h7s78-dk/hal.h b/radio/src/targets/stm32h7s78-dk/hal.h
index 26dcef224..0280abe70 100644
--- a/radio/src/targets/stm32h7s78-dk/hal.h
+++ b/radio/src/targets/stm32h7s78-dk/hal.h
@@ -216,17 +216,6 @@
 #define SD_SDIO_TRANSFER_CLK_DIV SDMMC_NSPEED_CLK_DIV
 
 // Audio
-// #define AUDIO_RCC_APB1Periph            (RCC_APB1Periph_TIM6 | RCC_APB1Periph_DAC)
-// #define AUDIO_RCC_AHB1Periph            (RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_DMA1)
-// #define AUDIO_OUTPUT_GPIO               GPIO_PIN(GPIOA, 4)  // PA.04
-// #define AUDIO_DMA_Stream                DMA1_Stream5
-// #define AUDIO_DMA_Stream_IRQn           DMA1_Stream5_IRQn
-// #define AUDIO_TIM_IRQn                  TIM6_DAC_IRQn
-// #define AUDIO_TIM_IRQHandler            TIM6_DAC_IRQHandler
-// #define AUDIO_DMA_Stream_IRQHandler     DMA1_Stream5_IRQHandler
-// #define AUDIO_TIMER                     TIM6
-// #define AUDIO_DMA                       DMA1
-
 #define AUDIO_SPI SPI6
 
 // I2C Bus
diff --git a/radio/src/targets/taranis/board.cpp b/radio/src/targets/taranis/board.cpp
index f6791914e..04737a36c 100644
--- a/radio/src/targets/taranis/board.cpp
+++ b/radio/src/targets/taranis/board.cpp
@@ -108,7 +108,6 @@ uint16_t getSixPosAnalogValue(uint16_t adcValue)
 
 void boardInit()
 {
-  LL_APB1_GRP1_EnableClock(AUDIO_RCC_APB1Periph);
   LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
 
 #if defined(USB_CHARGE_LED) && !defined(DEBUG)
diff --git a/radio/src/targets/taranis/board.h b/radio/src/targets/taranis/board.h
index 234757c14..29b43becf 100644
--- a/radio/src/targets/taranis/board.h
+++ b/radio/src/targets/taranis/board.h
@@ -224,7 +224,6 @@ void debugPutc(const char c);
 
 // Audio driver
 void audioInit();
-void audioEnd();
 
 #if defined(PCBXLITES)
 #define SHARED_DSC_HEADPHONE_JACK
diff --git a/radio/src/targets/taranis/hal.h b/radio/src/targets/taranis/hal.h
index 4638863a0..f7b0c2735 100644
--- a/radio/src/targets/taranis/hal.h
+++ b/radio/src/targets/taranis/hal.h
@@ -2719,11 +2719,8 @@
 #define SD_SPI_DMA_CHANNEL              LL_DMA_CHANNEL_0
 
 // Audio
-#define AUDIO_RCC_APB1Periph            LL_APB1_GRP1_PERIPH_DAC1
 #define AUDIO_OUTPUT_GPIO               GPIO_PIN(GPIOA, 4)
 #define AUDIO_DMA                       DMA1
-#define AUDIO_TIM_IRQn                  TIM6_DAC_IRQn
-#define AUDIO_TIM_IRQHandler            TIM6_DAC_IRQHandler
 #define AUDIO_DMA_Stream                DMA1_Stream5
 #define AUDIO_DMA_Stream_IRQn           DMA1_Stream5_IRQn
 #define AUDIO_DMA_Stream_IRQHandler     DMA1_Stream5_IRQHandler