diff --git a/radio/src/targets/common/arm/stm32/board_common.h b/radio/src/targets/common/arm/stm32/board_common.h
index c474dc37d..7ddeafa01 100644
--- a/radio/src/targets/common/arm/stm32/board_common.h
+++ b/radio/src/targets/common/arm/stm32/board_common.h
@@ -36,39 +36,39 @@
#endif
#if defined(STM32F4)
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h"
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h"
+ #include "stm32f4xx.h"
+ #include "stm32f4xx_rcc.h"
+ #include "stm32f4xx_syscfg.h"
+ #include "stm32f4xx_gpio.h"
+ #include "stm32f4xx_exti.h"
+ #include "stm32f4xx_tim.h"
+ #include "stm32f4xx_adc.h"
+ #include "stm32f4xx_spi.h"
+ #include "stm32f4xx_i2c.h"
+ #include "stm32f4xx_rtc.h"
+ #include "stm32f4xx_pwr.h"
+ #include "stm32f4xx_dma.h"
+ #include "stm32f4xx_usart.h"
+ #include "stm32f4xx_flash.h"
+ #include "stm32f4xx_dbgmcu.h"
+ #include "misc.h"
#else
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rcc.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_syscfg.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_gpio.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_exti.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_tim.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_adc.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_spi.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_i2c.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_rtc.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_pwr.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dma.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_usart.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_flash.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/stm32f2xx_dbgmcu.h"
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/STM32F2xx_StdPeriph_Driver/inc/misc.h"
+ #include "stm32f2xx.h"
+ #include "stm32f2xx_rcc.h"
+ #include "stm32f2xx_syscfg.h"
+ #include "stm32f2xx_gpio.h"
+ #include "stm32f2xx_exti.h"
+ #include "stm32f2xx_tim.h"
+ #include "stm32f2xx_adc.h"
+ #include "stm32f2xx_spi.h"
+ #include "stm32f2xx_i2c.h"
+ #include "stm32f2xx_rtc.h"
+ #include "stm32f2xx_pwr.h"
+ #include "stm32f2xx_dma.h"
+ #include "stm32f2xx_usart.h"
+ #include "stm32f2xx_flash.h"
+ #include "stm32f2xx_dbgmcu.h"
+ #include "misc.h"
#endif
#if __clang__
diff --git a/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt b/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt
index aafce8b63..c062596d1 100644
--- a/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt
+++ b/radio/src/targets/common/arm/stm32/f4/CMakeLists.txt
@@ -1,10 +1,10 @@
set(CPU_FAMILY STM32)
set(MCU cortex-m4)
set(FPU_FLAGS "-mfloat-abi=hard -mfpu=fpv4-sp-d16")
-set(STM32LIB_DIR ${THIRDPARTY_DIR}/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries)
+set(STM32LIB_DIR ${THIRDPARTY_DIR}/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries)
include_directories(${STM32LIB_DIR}/STM32F4xx_StdPeriph_Driver/inc)
include_directories(${STM32LIB_DIR}/CMSIS/Device/ST/STM32F4xx/Include)
-include_directories(${STM32LIB_DIR}/CMSIS/include)
+include_directories(${STM32LIB_DIR}/CMSIS/Include)
add_definitions(-DSTM32F4)
set(STM32LIB_SRC
${STM32LIB_SRC}
diff --git a/radio/src/targets/common/arm/stm32/usb_conf.h b/radio/src/targets/common/arm/stm32/usb_conf.h
index 9bc6f5f96..fcae1f370 100644
--- a/radio/src/targets/common/arm/stm32/usb_conf.h
+++ b/radio/src/targets/common/arm/stm32/usb_conf.h
@@ -23,9 +23,9 @@
#define _USB_CONF_H_
#if defined(STM32F4)
- #include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+ #include "stm32f4xx.h"
#else
- #include "STM32F2xx_StdPeriph_Lib_V1.1.0/Libraries/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h"
+ #include "stm32f2xx.h"
#endif
/* USB Core and PHY interface configuration.
diff --git a/radio/src/targets/horus/board.h b/radio/src/targets/horus/board.h
index b87e62a3d..bc574a581 100644
--- a/radio/src/targets/horus/board.h
+++ b/radio/src/targets/horus/board.h
@@ -35,10 +35,10 @@ PACK(typedef struct {
extern HardwareOptions hardwareOptions;
#if !defined(LUA_EXPORT_GENERATION)
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h"
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_dma2d.h"
+#include "stm32f4xx_ltdc.h"
+#include "stm32f4xx_fmc.h"
#endif
#define FLASHSIZE 0x200000
diff --git a/radio/src/targets/nv14/board.h b/radio/src/targets/nv14/board.h
index b3f0ee05f..d695ce710 100644
--- a/radio/src/targets/nv14/board.h
+++ b/radio/src/targets/nv14/board.h
@@ -27,10 +27,10 @@
#include "hal.h"
#if !defined(LUA_EXPORT_GENERATION)
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h"
-#include "STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h"
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_dma2d.h"
+#include "stm32f4xx_ltdc.h"
+#include "stm32f4xx_fmc.h"
#endif
#include "touch_driver.h"
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h
deleted file mode 100644
index 8d7fac0f0..000000000
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_const_structs.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date: 17. January 2013
-* $Revision: V1.4.1
-*
-* Project: CMSIS DSP Library
-* Title: arm_const_structs.h
-*
-* Description: This file has constant structs that are initialized for
-* user convenience. For example, some can be given as
-* arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
- 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
- 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
- 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
- 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
- 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
- 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
- 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
- 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
- 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
- };
-
-#endif
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
similarity index 73%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
index 89c096493..9ca6d36b1 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 09-November-2016
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F4xx devices.
@@ -12,20 +12,20 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
- * - To use or not the peripheral�s drivers in application code(i.e.
- * code will be based on direct access to peripheral�s registers
+ * - To use or not the peripheral’s drivers in application code(i.e.
+ * code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_STDPERIPH_DRIVER"
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
+ * - Peripherals registers declarations and bits definition
+ * - Macros to access peripheral’s registers hardware
*
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -53,8 +53,6 @@
#ifndef __STM32F4xx_H
#define __STM32F4xx_H
-#define assert_param(xx)
-
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
@@ -67,24 +65,43 @@
application
*/
-#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
- /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
+ !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
+ /* #define STM32F40_41xxx */ /*!< STM32F405RG, STM32F405VG, STM32F405ZG, STM32F415RG, STM32F415VG, STM32F415ZG,
STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG, STM32F407IE,
STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
- /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
+ /* #define STM32F427_437xx */ /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG, STM32F427II,
STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG, STM32F437II Devices */
- /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
- STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
+ /* #define STM32F429_439xx */ /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI,
+ STM32F429NG, STM32F439NI, STM32F429IG, STM32F429II, STM32F439VG, STM32F439VI,
STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, STM32F439NI,
STM32F439IG and STM32F439II Devices */
- /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC
+ /* #define STM32F401xx */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB, STM32F401VC,
STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CExx, STM32F401RE and STM32F401VE Devices */
- /* #define STM32F411xE */ /*!< STM32F411CD, STM32F411RD, STM32F411VD, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-#endif
+ /* #define STM32F410xx */ /*!< STM32F410Tx, STM32F410Cx and STM32F410Rx */
+
+ /* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+
+ /* #define STM32F412xG */ /*!< STM32F412CEU, STM32F412CGU, STM32F412ZET, STM32F412ZGT, STM32F412ZEJ, STM32F412ZGJ,
+ STM32F412VET, STM32F412VGT, STM32F412VEH, STM32F412VGH, STM32F412RET, STM32F412RGT,
+ STM32F412REY and STM32F412RGY Devices */
+
+ /* #define STM32F413_423xx */ /*!< STM32F413CGU, STM32F413CHU, STM32F413MGY, STM32F413MHY, STM32F413RGT, STM32F413VGT,
+ STM32F413ZGT, STM32F413RHT, STM32F413VHT, STM32F413ZHT, STM32F413VGH, STM32F413ZGJ,
+ STM32F413VHH, STM32F413ZHJ, STM32F423CHU, STM32F423RHT, STM32F423VHT, STM32F423ZHT,
+ STM32F423VHH and STM32F423ZHJ devices */
+
+ /* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC
+ and STM32F446ZE Devices */
+
+ /* #define STM32F469_479xx */ /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG,
+ STM32F479NG, STM32F479AE, STM32F479IE, STM32F479BE, STM32F479NE Devices */
+
+#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_423xx && STM32F446xx && STM32F469_479xx */
/* Old STM32F40XX definition, maintained for legacy purpose */
#ifdef STM32F40XX
@@ -100,9 +117,10 @@
devices, you can define the device in your toolchain compiler preprocessor.
*/
-#if !defined (STM32F40_41xxx) && !defined (STM32F427_437xx) && !defined (STM32F429_439xx) && !defined (STM32F401xx) && !defined (STM32F411xE)
+#if !defined(STM32F40_41xxx) && !defined(STM32F427_437xx) && !defined(STM32F429_439xx) && !defined(STM32F401xx) && !defined(STM32F410xx) && \
+ !defined(STM32F411xE) && !defined(STM32F412xG) && !defined(STM32F413_423xx) && !defined(STM32F446xx) && !defined(STM32F469_479xx)
#error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif
+#endif /* STM32F40_41xxx && STM32F427_437xx && STM32F429_439xx && STM32F401xx && STM32F410xx && STM32F411xE && STM32F412xG && STM32F413_23xx && STM32F446xx && STM32F469_479xx */
#if !defined (USE_STDPERIPH_DRIVER)
/**
@@ -120,12 +138,16 @@
Tip: To avoid modifying this file each time you need to use different HSE, you
can define the HSE value in your toolchain compiler preprocessor.
*/
-
-#if !defined (HSE_VALUE)
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || \
+ defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+ #if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
-
-#endif /* HSE_VALUE */
-
+ #endif /* HSE_VALUE */
+#elif defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ #if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+ #endif /* HSE_VALUE */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Timeout value
@@ -139,17 +161,17 @@
#endif /* HSI_VALUE */
/**
- * @brief STM32F4XX Standard Peripherals Library version number V1.4.0
+ * @brief STM32F4XX Standard Peripherals Library version number V1.8.0
*/
#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x08) /*!< [23:16] sub1 version */
#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
|(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
|(__STM32F4XX_STDPERIPH_VERSION_RC))
-
+
/**
* @}
*/
@@ -203,7 +225,7 @@ typedef enum IRQn
DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@@ -269,7 +291,7 @@ typedef enum IRQn
FPU_IRQn = 81 /*!< FPU global interrupt */
#endif /* STM32F40_41xxx */
-#if defined (STM32F427_437xx)
+#if defined(STM32F427_437xx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@@ -285,7 +307,7 @@ typedef enum IRQn
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
@@ -293,7 +315,7 @@ typedef enum IRQn
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
@@ -339,10 +361,10 @@ typedef enum IRQn
SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
#endif /* STM32F427_437xx */
-#if defined (STM32F429_439xx)
+#if defined(STM32F429_439xx)
CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
@@ -416,8 +438,44 @@ typedef enum IRQn
LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */
#endif /* STM32F429_439xx */
+
+#if defined(STM32F410xx)
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global Interrupt and DAC Global Interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97 /*!< LPTIM1 interrupt */
+#endif /* STM32F410xx */
-#if defined (STM32F401xx) || defined (STM32F411xE)
+#if defined(STM32F401xx) || defined(STM32F411xE)
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
@@ -454,22 +512,309 @@ typedef enum IRQn
I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
-#if defined (STM32F401xx)
+#if defined(STM32F401xx)
SPI4_IRQn = 84 /*!< SPI4 global Interrupt */
#endif /* STM32F411xE */
-#if defined (STM32F411xE)
+#if defined(STM32F411xE)
SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
SPI5_IRQn = 85 /*!< SPI5 global Interrupt */
#endif /* STM32F411xE */
#endif /* STM32F401xx || STM32F411xE */
+#if defined(STM32F469_479xx)
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
+ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
+ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
+ DSI_IRQn = 92 /*!< DSI global Interrupt */
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F446xx)
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FMC_IRQn = 48, /*!< FMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ CEC_IRQn = 93, /*!< QuadSPI global Interrupt */
+ SPDIF_RX_IRQn = 94, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPCI2C Error Interrupt */
+#endif /* STM32F446xx */
+
+#if defined(STM32F412xG)
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_IRQn = 54, /*!< TIM6 global interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96 /*!< FMPI2C1 Error Interrupt */
+#endif /* STM32F412xG */
+
+#if defined(STM32F413_423xx)
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC1&2 global Interrupt */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
+ DFSDM1_FLT0_IRQn = 61, /*!< DFSDM1 Filter 0 global Interrupt */
+ DFSDM1_FLT1_IRQn = 62, /*!< DFSDM1 Filter 1 global Interrupt */
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
+ USART6_IRQn = 71, /*!< USART6 global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ CAN3_TX_IRQn = 74, /*!< CAN3 TX Interrupt */
+ CAN3_RX0_IRQn = 75, /*!< CAN3 RX0 Interrupt */
+ CAN3_RX1_IRQn = 76, /*!< CAN3 RX1 Interrupt */
+ CAN3_SCE_IRQn = 77, /*!< CAN3 SCE Interrupt */
+ RNG_IRQn = 80, /*!< RNG global Interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ UART7_IRQn = 82, /*!< UART7 global interrupt */
+ UART8_IRQn = 83, /*!< UART8 global interrupt */
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
+ SAI1_IRQn = 87, /*!< Serial Audio Interface 1 global interrupt */
+ UART9_IRQn = 88, /*!< UART9 global Interrupt */
+ UART10_IRQn = 89, /*!< UART10 global Interrupt */
+ QUADSPI_IRQn = 92, /*!< QuadSPI global Interrupt */
+ FMPI2C1_EV_IRQn = 95, /*!< FMPI2C1 Event Interrupt */
+ FMPI2C1_ER_IRQn = 96, /*!< FMPI2C1 Error Interrupt */
+ LPTIM1_IRQn = 97, /*!< LP TIM1 interrupt */
+ DFSDM2_FLT0_IRQn = 98, /*!< DFSDM2 Filter 0 global Interrupt */
+ DFSDM2_FLT1_IRQn = 99, /*!< DFSDM2 Filter 1 global Interrupt */
+ DFSDM2_FLT2_IRQn = 100, /*!< DFSDM2 Filter 2 global Interrupt */
+ DFSDM2_FLT3_IRQn = 101 /*!< DFSDM2 Filter 3 global Interrupt */
+#endif /* STM32F413_423xx */
} IRQn_Type;
/**
* @}
*/
-#include "../../../../Include/core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32f4xx.h"
#include
@@ -544,7 +889,7 @@ typedef struct
__IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
__IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
__IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38 */
__IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
__IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
__IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
@@ -625,6 +970,21 @@ typedef struct
CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
} CAN_TypeDef;
+#if defined(STM32F446xx)
+/**
+ * @brief Consumer Electronics Control
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
+ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
+ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
+ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
+ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
+ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
+}CEC_TypeDef;
+#endif /* STM32F446xx */
+
/**
* @brief CRC calculation unit
*/
@@ -660,6 +1020,45 @@ typedef struct
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
} DAC_TypeDef;
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief DFSDM module registers
+ */
+typedef struct
+{
+ __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
+ __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
+ __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
+ __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
+ __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
+ __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
+ __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
+ __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
+ __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
+ __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
+ __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
+ __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
+ __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
+ __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
+ __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
+} DFSDM_Filter_TypeDef;
+
+/**
+ * @brief DFSDM channel configuration registers
+ */
+typedef struct
+{
+ __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
+ __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
+ __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
+ short circuit detector register, Address offset: 0x08 */
+ __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
+ __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
+} DFSDM_Channel_TypeDef;
+
+/* Legacy Defines */
+#define DFSDM_TypeDef DFSDM_Filter_TypeDef
+#endif /* STM32F412xG || STM32F413_423xx */
/**
* @brief Debug MCU
*/
@@ -744,6 +1143,89 @@ typedef struct
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
} DMA2D_TypeDef;
+#if defined(STM32F469_479xx)
+/**
+ * @brief DSI Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
+ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
+ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
+ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
+ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
+ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
+ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
+ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
+ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
+ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
+ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
+ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
+ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
+ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
+ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
+ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
+ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
+ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
+ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
+ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
+ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
+ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
+ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
+ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
+ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
+ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
+ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
+ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
+ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
+ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
+ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
+ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
+ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
+ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
+ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
+ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
+ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
+ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
+ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
+ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
+ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
+ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
+ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
+ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
+ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
+ uint32_t RESERVED5; /*!< Reserved, 0x114 */
+ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
+ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
+ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
+ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
+ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
+ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
+ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
+ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
+ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
+ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
+ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
+ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
+ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
+ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
+ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
+ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
+ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
+ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
+ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
+ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
+ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
+ uint32_t RESERVED9; /*!< Reserved, 0x414 */
+ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
+ uint32_t RESERVED10; /*!< Reserved, 0x42C */
+ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
+} DSI_TypeDef;
+#endif /* STM32F469_479xx */
+
/**
* @brief Ethernet MAC
*/
@@ -847,7 +1329,7 @@ typedef struct
__IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
} FLASH_TypeDef;
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
/**
* @brief Flexible Static Memory Controller
*/
@@ -906,9 +1388,9 @@ typedef struct
__IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */
__IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */
} FSMC_Bank4_TypeDef;
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/**
* @brief Flexible Memory Controller
*/
@@ -980,7 +1462,7 @@ typedef struct
__IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
__IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
} FMC_Bank5_6_TypeDef;
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/**
* @brief General Purpose I/O
@@ -1009,8 +1491,19 @@ typedef struct
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+#if defined (STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+ uint32_t RESERVED; /*!< Reserved, 0x18 */
+ __IO uint32_t CFGR2; /*!< Reserved, 0x1C */
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x24-0x28 */
+ __IO uint32_t CFGR; /*!< SYSCFG Configuration register, Address offset: 0x2C */
+#else /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
__IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
+#endif /* STM32F410xx || defined(STM32F412xG) || defined(STM32F413_423xx) */
+#if defined(STM32F413_423xx)
+ __IO uint32_t MCHDLYCR; /*!< SYSCFG multi-channel delay register, Address offset: 0x30 */
+#endif /* STM32F413_423xx */
} SYSCFG_TypeDef;
/**
@@ -1041,6 +1534,27 @@ typedef struct
uint16_t RESERVED9; /*!< Reserved, 0x26 */
} I2C_TypeDef;
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< FMPI2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< FMPI2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< FMPI2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< FMPI2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< FMPI2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< FMPI2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< FMPI2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< FMPI2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< FMPI2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< FMPI2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< FMPI2C Transmit data register, Address offset: 0x28 */
+}FMPI2C_TypeDef;
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
/**
* @brief Independent WATCHDOG
*/
@@ -1149,6 +1663,8 @@ typedef struct
__IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
__IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
__IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
+ __IO uint32_t CKGATENR; /*!< RCC Clocks Gated Enable Register, Address offset: 0x90 */ /* Only for STM32F412xG, STM32413_423xx and STM32F446xx devices */
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x94 */ /* Only for STM32F410xx, STM32F412xG, STM32413_423xx and STM32F446xx devices */
} RCC_TypeDef;
@@ -1276,6 +1792,66 @@ typedef struct
uint16_t RESERVED8; /*!< Reserved, 0x22 */
} SPI_TypeDef;
+#if defined(STM32F446xx)
+/**
+ * @brief SPDIFRX Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIFRX_TypeDef;
+#endif /* STM32F446xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief SPDIF-RX Interface
+ */
+typedef struct
+{
+ __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
+ __IO uint16_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
+ __IO uint16_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
+ uint16_t RESERVED1; /*!< Reserved, 0x0E */
+ __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
+ __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
+ __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
+ uint16_t RESERVED2; /*!< Reserved, 0x1A */
+} SPDIF_TypeDef;
+#endif /* STM32F446xx */
+
/**
* @brief TIM
*/
@@ -1433,6 +2009,23 @@ typedef struct
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+#endif /* STM32F410xx || STM32F413_423xx */
/**
* @}
*/
@@ -1440,28 +2033,49 @@ typedef struct
/** @addtogroup Peripheral_memory_map
* @{
*/
+
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */
#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */
#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */
+#elif defined(STM32F469_479xx)
+#define SRAM2_BASE ((uint32_t)0x20028000) /*!< SRAM2(16 KB) base address in the alias region */
+#define SRAM3_BASE ((uint32_t)0x20030000) /*!< SRAM3(64 KB) base address in the alias region */
+#elif defined(STM32F413_423xx)
+#define SRAM2_BASE ((uint32_t)0x20040000) /*!< SRAM2(16 KB) base address in the alias region */
+#else /* STM32F411xE || STM32F410xx || STM32F412xG */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */
-
-#if defined (STM32F40_41xxx)
+
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define QSPI_R_BASE ((uint32_t)0xA0001000) /*!< QuadSPI registers base address */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */
#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
+#define SRAM2_BB_BASE ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region */
#define SRAM3_BB_BASE ((uint32_t)0x22400000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#elif defined(STM32F469_479xx)
+#define SRAM2_BB_BASE ((uint32_t)0x22500000) /*!< SRAM2(16 KB) base address in the bit-band region */
+#define SRAM3_BB_BASE ((uint32_t)0x22600000) /*!< SRAM3(64 KB) base address in the bit-band region */
+#elif defined(STM32F413_423xx)
+#define SRAM2_BB_BASE ((uint32_t)0x22800000) /*!< SRAM2(64 KB) base address in the bit-band region */
+#else /* STM32F411xE || STM32F410xx || STM32F412xG */
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx */
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
+#define BKPSRAM_BB_BASE ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
@@ -1481,6 +2095,9 @@ typedef struct
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400)
+#endif /* STM32F410xx || STM32F413_423xx */
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
@@ -1490,6 +2107,9 @@ typedef struct
#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#if defined(STM32F446xx)
+#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000)
+#endif /* STM32F446xx */
#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
@@ -1498,8 +2118,17 @@ typedef struct
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define FMPI2C1_BASE (APB1PERIPH_BASE + 0x6000)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
+#if defined(STM32F413_423xx)
+#define CAN3_BASE (APB1PERIPH_BASE + 0x6C00)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx)
+#define CEC_BASE (APB1PERIPH_BASE + 0x6C00)
+#endif /* STM32F446xx */
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#define UART7_BASE (APB1PERIPH_BASE + 0x7800)
@@ -1510,6 +2139,8 @@ typedef struct
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)
#define USART1_BASE (APB2PERIPH_BASE + 0x1000)
#define USART6_BASE (APB2PERIPH_BASE + 0x1400)
+#define UART9_BASE (APB2PERIPH_BASE + 0x1800U)
+#define UART10_BASE (APB2PERIPH_BASE + 0x1C00U)
#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)
@@ -1527,9 +2158,50 @@ typedef struct
#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)
+#if defined(STM32F446xx)
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00)
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004)
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024)
+#endif /* STM32F446xx */
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104)
+#if defined(STM32F469_479xx)
+#define DSI_BASE (APB2PERIPH_BASE + 0x6C00)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define DFSDM1_BASE (APB2PERIPH_BASE + 0x6000)
+#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00)
+#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20)
+#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40)
+#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60)
+#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100)
+#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180)
+#define DFSDM1_0 ((DFSDM_TypeDef *) DFSDM1_Filter0_BASE)
+#define DFSDM1_1 ((DFSDM_TypeDef *) DFSDM1_Filter1_BASE)
+/* Legacy Defines */
+#define DFSDM0 DFSDM1_0
+#define DFSDM1 DFSDM1_1
+#if defined(STM32F413_423xx)
+#define DFSDM2_BASE (APB2PERIPH_BASE + 0x6400U)
+#define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00U)
+#define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20U)
+#define DFSDM2_Channel2_BASE (DFSDM2_BASE + 0x40U)
+#define DFSDM2_Channel3_BASE (DFSDM2_BASE + 0x60U)
+#define DFSDM2_Channel4_BASE (DFSDM2_BASE + 0x80U)
+#define DFSDM2_Channel5_BASE (DFSDM2_BASE + 0xA0U)
+#define DFSDM2_Channel6_BASE (DFSDM2_BASE + 0xC0U)
+#define DFSDM2_Channel7_BASE (DFSDM2_BASE + 0xE0U)
+#define DFSDM2_Filter0_BASE (DFSDM2_BASE + 0x100U)
+#define DFSDM2_Filter1_BASE (DFSDM2_BASE + 0x180U)
+#define DFSDM2_Filter2_BASE (DFSDM2_BASE + 0x200U)
+#define DFSDM2_Filter3_BASE (DFSDM2_BASE + 0x280U)
+#define DFSDM2_0 ((DFSDM_TypeDef *) DFSDM2_Filter0_BASE)
+#define DFSDM2_1 ((DFSDM_TypeDef *) DFSDM2_Filter1_BASE)
+#define DFSDM2_2 ((DFSDM_TypeDef *) DFSDM2_Filter2_BASE)
+#define DFSDM2_3 ((DFSDM_TypeDef *) DFSDM2_Filter3_BASE)
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
/*!< AHB1 peripherals */
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
@@ -1578,16 +2250,16 @@ typedef struct
#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
/*!< FSMC Bankx registers base address */
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/*!< FMC Bankx registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
@@ -1595,7 +2267,7 @@ typedef struct
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/* Debug MCU registers base address */
#define DBGMCU_BASE ((uint32_t )0xE0042000)
@@ -1606,7 +2278,10 @@ typedef struct
/** @addtogroup Peripheral_declaration
* @{
- */
+ */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
@@ -1622,6 +2297,9 @@ typedef struct
#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#if defined(STM32F446xx)
+#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
+#endif /* STM32F446xx */
#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
@@ -1630,12 +2308,26 @@ typedef struct
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define FMPI2C1 ((FMPI2C_TypeDef *) FMPI2C1_BASE)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#endif /* STM32F410xx || STM32F413_423xx */
#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
+#if defined(STM32F413_423xx)
+#define CAN3 ((CAN_TypeDef *) CAN3_BASE)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx)
+#define CEC ((CEC_TypeDef *) CEC_BASE)
+#endif /* STM32F446xx */
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
+#define UART9 ((USART_TypeDef *) UART9_BASE)
+#define UART10 ((USART_TypeDef *) UART10_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
@@ -1657,9 +2349,39 @@ typedef struct
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#if defined(STM32F446xx)
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
+#endif /* STM32F446xx */
#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
+#if defined(STM32F469_479xx)
+#define DSI ((DSI_TypeDef *)DSI_BASE)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
+#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
+#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
+#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
+#define DFSDM1_Filter0 ((DFSDM_TypeDef *) DFSDM_Filter0_BASE)
+#define DFSDM1_Filter1 ((DFSDM_TypeDef *) DFSDM_Filter1_BASE)
+#if defined(STM32F413_423xx)
+#define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
+#define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
+#define DFSDM2_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel2_BASE)
+#define DFSDM2_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel3_BASE)
+#define DFSDM2_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel4_BASE)
+#define DFSDM2_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel5_BASE)
+#define DFSDM2_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel6_BASE)
+#define DFSDM2_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel7_BASE)
+#define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter0_BASE)
+#define DFSDM2_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter1_BASE)
+#define DFSDM2_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter2_BASE)
+#define DFSDM2_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM2_Filter3_BASE)
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
@@ -1671,9 +2393,7 @@ typedef struct
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
-#if !defined WIN32 && defined __GNUC__
#define CRC ((CRC_TypeDef *) CRC_BASE)
-#endif
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
@@ -1702,22 +2422,22 @@ typedef struct
#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)
#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
@@ -2058,19 +2778,24 @@ typedef struct
#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!© COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h
index 036a40e0e..039cc3d66 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_common_tables.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_common_tables.h
@@ -43,10 +43,6 @@
#include "arm_math.h"
-#ifndef FAST_MATH_TABLE_SIZE
-#define FAST_MATH_TABLE_SIZE 512
-#endif
-
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h
new file mode 100644
index 000000000..726d06eb6
--- /dev/null
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_const_structs.h
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
+*
+* Project: CMSIS DSP Library
+* Title: arm_const_structs.h
+*
+* Description: This file has constant structs that are initialized for
+* user convenience. For example, some can be given as
+* arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in
+* the documentation and/or other materials provided with the
+* distribution.
+* - Neither the name of ARM LIMITED nor the names of its contributors
+* may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+ extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+ extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+ extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h
similarity index 93%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h
index 65304c127..e4b2f62e8 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/arm_math.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/arm_math.h
@@ -1,15 +1,15 @@
/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+* Copyright (C) 2010-2015 ARM Limited. All rights reserved.
*
-* $Date: 17. January 2013
-* $Revision: V1.4.1
+* $Date: 19. March 2015
+* $Revision: V.1.4.5
*
-* Project: CMSIS DSP Library
-* Title: arm_math.h
+* Project: CMSIS DSP Library
+* Title: arm_math.h
*
-* Description: Public header file for CMSIS DSP Library
+* Description: Public header file for CMSIS DSP Library
*
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+* Target Processor: Cortex-M7/Cortex-M4/Cortex-M3/Cortex-M0
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,7 +41,8 @@
/**
\mainpage CMSIS DSP Software Library
*
- * Introduction
+ * Introduction
+ * ------------
*
* This user manual describes the CMSIS DSP software library,
* a suite of common signal processing functions for use on Cortex-M processor based devices.
@@ -61,49 +62,53 @@
* The library has separate functions for operating on 8-bit integers, 16-bit integers,
* 32-bit integer and 32-bit floating-point values.
*
- * Using the Library
+ * Using the Library
+ * ------------
*
* The library installer contains prebuilt versions of the libraries in the Lib folder.
+ * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7)
+ * - arm_cortexM7l_math.lib (Little endian on Cortex-M7)
+ * - arm_cortexM7b_math.lib (Big endian on Cortex-M7)
* - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
* - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
* - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
* - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
* - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
* - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+ * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+)
+ * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+)
*
* The library functions are declared in the public file arm_math.h which is placed in the Include folder.
* Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
+ * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
+ * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or
* ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
*
- * Examples
+ * Examples
+ * --------
*
* The library ships with a number of examples which demonstrate how to use the library functions.
*
- * Toolchain Support
+ * Toolchain Support
+ * ------------
*
- * The library has been developed and tested with MDK-ARM version 4.60.
+ * The library has been developed and tested with MDK-ARM version 5.14.0.0
* The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
*
- * Building the Library
+ * Building the Library
+ * ------------
*
- * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
- * - arm_cortexM0b_math.uvproj
- * - arm_cortexM0l_math.uvproj
- * - arm_cortexM3b_math.uvproj
- * - arm_cortexM3l_math.uvproj
- * - arm_cortexM4b_math.uvproj
- * - arm_cortexM4l_math.uvproj
- * - arm_cortexM4bf_math.uvproj
- * - arm_cortexM4lf_math.uvproj
+ * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder.
+ * - arm_cortexM_math.uvprojx
*
*
- * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
+ * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above.
*
- * Pre-processor Macros
+ * Pre-processor Macros
+ * ------------
*
* Each library project have differant pre-processor macros.
*
@@ -126,15 +131,34 @@
* - ARM_MATH_CMx:
*
* Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
+ * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and
+ * ARM_MATH_CM7 for building the library on cortex-M7.
*
* - __FPU_PRESENT:
*
* Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
*
- * Copyright Notice
+ *
+ * CMSIS-DSP in ARM::CMSIS Pack
+ * -----------------------------
+ *
+ * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories:
+ * |File/Folder |Content |
+ * |------------------------------|------------------------------------------------------------------------|
+ * |\b CMSIS\\Documentation\\DSP | This documentation |
+ * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) |
+ * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions |
+ * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library |
+ *
+ *
+ * Revision History of CMSIS-DSP
+ * ------------
+ * Please refer to \ref ChangeLog_pg.
*
- * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
+ * Copyright Notice
+ * ------------
+ *
+ * Copyright (C) 2010-2015 ARM Limited. All rights reserved.
*/
@@ -266,19 +290,20 @@
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-#if defined (ARM_MATH_CM4)
-#include "core_cm4.h"
+#if defined(ARM_MATH_CM7)
+ #include "core_cm7.h"
+#elif defined (ARM_MATH_CM4)
+ #include "core_cm4.h"
#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
+ #include "core_cm3.h"
#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
+ #include "core_cm0.h"
#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
+ #elif defined (ARM_MATH_CM0PLUS)
#include "core_cm0plus.h"
-#define ARM_MATH_CM0_FAMILY
+ #define ARM_MATH_CM0_FAMILY
#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+ #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS or ARM_MATH_CM0"
#endif
#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
@@ -305,9 +330,13 @@ extern "C"
* @brief Macros required for SINE and COSINE Fast math approximations
*/
-#define TABLE_SIZE 256
-#define TABLE_SPACING_Q31 0x800000
-#define TABLE_SPACING_Q15 0x80
+#define FAST_MATH_TABLE_SIZE 512
+#define FAST_MATH_Q31_SHIFT (32 - 10)
+#define FAST_MATH_Q15_SHIFT (16 - 10)
+#define CONTROLLER_Q31_SHIFT (32 - 9)
+#define TABLE_SIZE 256
+#define TABLE_SPACING_Q31 0x400000
+#define TABLE_SPACING_Q15 0x80
/**
* @brief Macros required for SINE and COSINE Controller functions
@@ -378,16 +407,22 @@ extern "C"
* @brief definition to read/write two 16 bit values.
*/
#if defined __CC_ARM
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED __attribute__((unused))
#elif defined __ICCARM__
-#define CMSIS_UNUSED
-#define __SIMD32_TYPE int32_t __packed
+ #define __SIMD32_TYPE int32_t __packed
+ #define CMSIS_UNUSED
#elif defined __GNUC__
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED __attribute__((unused))
+#elif defined __CSMC__ /* Cosmic */
+ #define __SIMD32_TYPE int32_t
+ #define CMSIS_UNUSED
+#elif defined __TASKING__
+ #define __SIMD32_TYPE __unaligned int32_t
+ #define CMSIS_UNUSED
#else
-#error Unknown compiler
+ #error Unknown compiler
#endif
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
@@ -481,11 +516,12 @@ extern "C"
}
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
-#define __CLZ __clz
-#endif
+//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
+//#define __CLZ __clz
+//#endif
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+//note: function can be removed when all toolchain support __CLZ for Cortex-M0
+#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) )
static __INLINE uint32_t __CLZ(
q31_t data);
@@ -730,8 +766,8 @@ extern "C"
q31_t sum;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = __SSAT(r + s, 16);
s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
@@ -753,8 +789,8 @@ extern "C"
q31_t sum;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = ((r >> 1) + (s >> 1));
s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
@@ -776,8 +812,8 @@ extern "C"
q31_t sum;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = __SSAT(r - s, 16);
s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
@@ -798,8 +834,8 @@ extern "C"
q31_t diff;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = ((r >> 1) - (s >> 1));
s = (((x >> 17) - (y >> 17)) << 16);
@@ -821,8 +857,8 @@ extern "C"
sum =
((sum +
- clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16)));
return sum;
}
@@ -838,8 +874,8 @@ extern "C"
q31_t sum;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = ((r >> 1) - (y >> 17));
s = (((x >> 17) + (s >> 1)) << 16);
@@ -862,8 +898,8 @@ extern "C"
sum =
((sum +
- clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+ clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) +
+ clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16)));
return sum;
}
@@ -879,8 +915,8 @@ extern "C"
q31_t sum;
q31_t r, s;
- r = (short) x;
- s = (short) y;
+ r = (q15_t) x;
+ s = (q15_t) y;
r = ((r >> 1) + (y >> 17));
s = (((x >> 17) - (s >> 1)) << 16);
@@ -898,8 +934,8 @@ extern "C"
q31_t y)
{
- return ((q31_t) (((short) x * (short) (y >> 16)) -
- ((short) (x >> 16) * (short) y)));
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) -
+ ((q15_t) (x >> 16) * (q15_t) y)));
}
/*
@@ -910,8 +946,8 @@ extern "C"
q31_t y)
{
- return ((q31_t) (((short) x * (short) (y >> 16)) +
- ((short) (x >> 16) * (short) y)));
+ return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) +
+ ((q15_t) (x >> 16) * (q15_t) y)));
}
/*
@@ -943,8 +979,8 @@ extern "C"
q31_t sum)
{
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
}
/*
@@ -956,8 +992,8 @@ extern "C"
q31_t sum)
{
- return (sum + ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
}
/*
@@ -969,8 +1005,8 @@ extern "C"
q31_t sum)
{
- return (sum - ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
+ return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) +
+ ((q15_t) x * (q15_t) (y >> 16)));
}
/*
@@ -982,8 +1018,8 @@ extern "C"
q63_t sum)
{
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
+ return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) +
+ ((q15_t) x * (q15_t) y));
}
/*
@@ -995,8 +1031,8 @@ extern "C"
q63_t sum)
{
- return (sum + ((short) (x >> 16) * (short) y)) +
- ((short) x * (short) (y >> 16));
+ return (sum + ((q15_t) (x >> 16) * (q15_t) y)) +
+ ((q15_t) x * (q15_t) (y >> 16));
}
/*
@@ -1410,6 +1446,18 @@ extern "C"
float32_t *pData; /**< points to the data of the matrix. */
} arm_matrix_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point matrix structure.
+ */
+
+ typedef struct
+ {
+ uint16_t numRows; /**< number of rows of the matrix. */
+ uint16_t numCols; /**< number of columns of the matrix. */
+ float64_t *pData; /**< points to the data of the matrix. */
+ } arm_matrix_instance_f64;
+
/**
* @brief Instance structure for the Q15 matrix structure.
*/
@@ -1478,6 +1526,49 @@ extern "C"
const arm_matrix_instance_q31 * pSrcB,
arm_matrix_instance_q31 * pDst);
+ /**
+ * @brief Floating-point, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_f32(
+ const arm_matrix_instance_f32 * pSrcA,
+ const arm_matrix_instance_f32 * pSrcB,
+ arm_matrix_instance_f32 * pDst);
+
+ /**
+ * @brief Q15, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q15(
+ const arm_matrix_instance_q15 * pSrcA,
+ const arm_matrix_instance_q15 * pSrcB,
+ arm_matrix_instance_q15 * pDst,
+ q15_t * pScratch);
+
+ /**
+ * @brief Q31, complex, matrix multiplication.
+ * @param[in] *pSrcA points to the first input matrix structure
+ * @param[in] *pSrcB points to the second input matrix structure
+ * @param[out] *pDst points to output matrix structure
+ * @return The function returns either
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+ */
+
+ arm_status arm_mat_cmplx_mult_q31(
+ const arm_matrix_instance_q31 * pSrcA,
+ const arm_matrix_instance_q31 * pSrcB,
+ arm_matrix_instance_q31 * pDst);
+
/**
* @brief Floating-point matrix transpose.
@@ -1536,7 +1627,7 @@ extern "C"
* @param[in] *pSrcA points to the first input matrix structure
* @param[in] *pSrcB points to the second input matrix structure
* @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
+ * @param[in] *pState points to the array for storing intermediate results
* @return The function returns either
* ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
*/
@@ -1971,12 +2062,14 @@ extern "C"
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q15;
+/* Deprecated */
arm_status arm_cfft_radix2_init_q15(
arm_cfft_radix2_instance_q15 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
+/* Deprecated */
void arm_cfft_radix2_q15(
const arm_cfft_radix2_instance_q15 * S,
q15_t * pSrc);
@@ -1998,12 +2091,14 @@ extern "C"
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q15;
+/* Deprecated */
arm_status arm_cfft_radix4_init_q15(
arm_cfft_radix4_instance_q15 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
+/* Deprecated */
void arm_cfft_radix4_q15(
const arm_cfft_radix4_instance_q15 * S,
q15_t * pSrc);
@@ -2023,12 +2118,14 @@ extern "C"
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix2_instance_q31;
+/* Deprecated */
arm_status arm_cfft_radix2_init_q31(
arm_cfft_radix2_instance_q31 * S,
uint16_t fftLen,
uint8_t ifftFlag,
uint8_t bitReverseFlag);
+/* Deprecated */
void arm_cfft_radix2_q31(
const arm_cfft_radix2_instance_q31 * S,
q31_t * pSrc);
@@ -2048,11 +2145,12 @@ extern "C"
uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
} arm_cfft_radix4_instance_q31;
-
+/* Deprecated */
void arm_cfft_radix4_q31(
const arm_cfft_radix4_instance_q31 * S,
q31_t * pSrc);
+/* Deprecated */
arm_status arm_cfft_radix4_init_q31(
arm_cfft_radix4_instance_q31 * S,
uint16_t fftLen,
@@ -2115,6 +2213,42 @@ extern "C"
const arm_cfft_radix4_instance_f32 * S,
float32_t * pSrc);
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q15_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q15;
+
+void arm_cfft_q15(
+ const arm_cfft_instance_q15 * S,
+ q15_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
+ /**
+ * @brief Instance structure for the fixed-point CFFT/CIFFT function.
+ */
+
+ typedef struct
+ {
+ uint16_t fftLen; /**< length of the FFT. */
+ const q31_t *pTwiddle; /**< points to the Twiddle factor table. */
+ const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
+ uint16_t bitRevLength; /**< bit reversal table length. */
+ } arm_cfft_instance_q31;
+
+void arm_cfft_q31(
+ const arm_cfft_instance_q31 * S,
+ q31_t * p1,
+ uint8_t ifftFlag,
+ uint8_t bitReverseFlag);
+
/**
* @brief Instance structure for the floating-point CFFT/CIFFT function.
*/
@@ -2140,18 +2274,16 @@ extern "C"
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+ const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */
} arm_rfft_instance_q15;
arm_status arm_rfft_init_q15(
arm_rfft_instance_q15 * S,
- arm_cfft_radix4_instance_q15 * S_CFFT,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
@@ -2168,18 +2300,16 @@ extern "C"
typedef struct
{
uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+ uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+ const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */
} arm_rfft_instance_q31;
arm_status arm_rfft_init_q31(
arm_rfft_instance_q31 * S,
- arm_cfft_radix4_instance_q31 * S_CFFT,
uint32_t fftLenReal,
uint32_t ifftFlagR,
uint32_t bitReverseFlag);
@@ -3694,6 +3824,32 @@ void arm_rfft_fast_f32(
} arm_biquad_cascade_df2T_instance_f32;
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
+ float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_stereo_df2T_instance_f32;
+
+
+
+ /**
+ * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+ */
+
+ typedef struct
+ {
+ uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
+ float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
+ float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
+ } arm_biquad_cascade_df2T_instance_f64;
+
+
/**
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in] *S points to an instance of the filter data structure.
@@ -3710,6 +3866,37 @@ void arm_rfft_fast_f32(
uint32_t blockSize);
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_stereo_df2T_f32(
+ const arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ float32_t * pSrc,
+ float32_t * pDst,
+ uint32_t blockSize);
+
+ /**
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in] *S points to an instance of the filter data structure.
+ * @param[in] *pSrc points to the block of input data.
+ * @param[out] *pDst points to the block of output data
+ * @param[in] blockSize number of samples to process.
+ * @return none.
+ */
+
+ void arm_biquad_cascade_df2T_f64(
+ const arm_biquad_cascade_df2T_instance_f64 * S,
+ float64_t * pSrc,
+ float64_t * pDst,
+ uint32_t blockSize);
+
+
/**
* @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in,out] *S points to an instance of the filter data structure.
@@ -3726,6 +3913,38 @@ void arm_rfft_fast_f32(
float32_t * pState);
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_stereo_df2T_init_f32(
+ arm_biquad_cascade_stereo_df2T_instance_f32 * S,
+ uint8_t numStages,
+ float32_t * pCoeffs,
+ float32_t * pState);
+
+
+ /**
+ * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+ * @param[in,out] *S points to an instance of the filter data structure.
+ * @param[in] numStages number of 2nd order stages in the filter.
+ * @param[in] *pCoeffs points to the filter coefficients.
+ * @param[in] *pState points to the state buffer.
+ * @return none
+ */
+
+ void arm_biquad_cascade_df2T_init_f64(
+ arm_biquad_cascade_df2T_instance_f64 * S,
+ uint8_t numStages,
+ float64_t * pCoeffs,
+ float64_t * pState);
+
+
/**
* @brief Instance structure for the Q15 FIR lattice filter.
@@ -5023,6 +5242,19 @@ void arm_rfft_fast_f32(
arm_matrix_instance_f32 * dst);
+ /**
+ * @brief Floating-point matrix inverse.
+ * @param[in] *src points to the instance of the input floating-point matrix structure.
+ * @param[out] *dst points to the instance of the output floating-point matrix structure.
+ * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+ * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+ */
+
+ arm_status arm_mat_inverse_f64(
+ const arm_matrix_instance_f64 * src,
+ arm_matrix_instance_f64 * dst);
+
+
/**
* @ingroup groupController
@@ -5869,7 +6101,7 @@ void arm_rfft_fast_f32(
float32_t in,
float32_t * pOut)
{
- if(in > 0)
+ if(in >= 0.0f)
{
// #if __FPU_USED
@@ -6350,7 +6582,7 @@ void arm_rfft_fast_f32(
void arm_var_q31(
q31_t * pSrc,
uint32_t blockSize,
- q63_t * pResult);
+ q31_t * pResult);
/**
* @brief Variance of the elements of a Q15 vector.
@@ -6363,7 +6595,7 @@ void arm_rfft_fast_f32(
void arm_var_q15(
q15_t * pSrc,
uint32_t blockSize,
- q31_t * pResult);
+ q15_t * pResult);
/**
* @brief Root Mean Square of the elements of a floating-point vector.
@@ -7208,29 +7440,51 @@ void arm_rfft_fast_f32(
/**
* @} end of BilinearInterpolate group
*/
+
-
-#if defined ( __CC_ARM ) //Keil
//SMMLAR
- #define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
+#define multAcc_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
//SMMLSR
- #define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
+#define multSub_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
//SMMULR
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+#define mult_32x32_keep32_R(a, x, y) \
+ a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
+
+//SMMLA
+#define multAcc_32x32_keep32(a, x, y) \
+ a += (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMLS
+#define multSub_32x32_keep32(a, x, y) \
+ a -= (q31_t) (((q63_t) x * y) >> 32)
+
+//SMMUL
+#define mult_32x32_keep32(a, x, y) \
+ a = (q31_t) (((q63_t) x * y ) >> 32)
+
+
+#if defined ( __CC_ARM ) //Keil
//Enter low optimization region - place directly above function definition
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("push") \
+ _Pragma ("O1")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
//Exit low optimization region - place directly after end of function definition
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_EXIT \
+ _Pragma ("pop")
+ #else
+ #define LOW_OPTIMIZATION_EXIT
+ #endif
//Enter low optimization region - place directly above function definition
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
@@ -7239,44 +7493,30 @@ void arm_rfft_fast_f32(
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__ICCARM__) //IAR
- //SMMLA
- #define multAcc_32x32_keep32_R(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
- #define multSub_32x32_keep32_R(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
//Enter low optimization region - place directly above function definition
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
+ #ifdef ARM_MATH_CM4
+ #define LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define LOW_OPTIMIZATION_ENTER
+ #endif
//Exit low optimization region - place directly after end of function definition
#define LOW_OPTIMIZATION_EXIT
//Enter low optimization region - place directly above function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
+ #ifdef ARM_MATH_CM4
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
+ _Pragma ("optimize=low")
+ #else
+ #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+ #endif
//Exit low optimization region - place directly after end of function definition
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
#elif defined(__GNUC__)
- //SMMLA
- #define multAcc_32x32_keep32_R(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
- #define multSub_32x32_keep32_R(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
@@ -7286,12 +7526,23 @@ void arm_rfft_fast_f32(
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+#elif defined(__CSMC__) // Cosmic
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
+#elif defined(__TASKING__) // TASKING
+
+#define LOW_OPTIMIZATION_ENTER
+#define LOW_OPTIMIZATION_EXIT
+#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
+#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
+
#endif
-
-
-
#ifdef __cplusplus
}
#endif
@@ -7299,7 +7550,6 @@ void arm_rfft_fast_f32(
#endif /* _ARM_MATH_H */
-
/**
*
* End of file.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h
similarity index 79%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h
index ab31de0ee..cf2b5d66b 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,8 +68,8 @@
*/
/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
@@ -81,14 +81,18 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
@@ -96,9 +100,16 @@
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -107,26 +118,40 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include /* standard types definitions */
#include /* Core Instruction Access */
#include /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -134,6 +159,10 @@
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
@@ -196,14 +225,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -212,6 +234,19 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -225,6 +260,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -233,16 +272,9 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -251,6 +283,25 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -258,14 +309,17 @@ typedef union
{
struct
{
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
/*@} end of group CMSIS_CORE */
@@ -329,7 +383,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -357,7 +411,7 @@ typedef struct
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
@@ -426,15 +480,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -444,7 +498,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -501,9 +555,9 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
@@ -514,7 +568,7 @@ typedef struct
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -526,7 +580,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -542,7 +596,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -554,7 +608,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -566,7 +620,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -581,12 +635,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
}
@@ -604,10 +660,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -619,10 +677,10 @@ __STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -655,15 +713,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -673,10 +731,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h
similarity index 81%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h
index 5cea74e9a..123cb400a 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm0plus.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm0plus.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,8 +68,8 @@
*/
/* CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
@@ -81,14 +81,18 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
@@ -96,9 +100,16 @@
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -107,26 +118,40 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include /* standard types definitions */
#include /* Core Instruction Access */
#include /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -134,6 +159,10 @@
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
@@ -207,14 +236,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -223,6 +245,19 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -236,6 +271,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -244,16 +283,9 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -262,6 +294,25 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -271,12 +322,18 @@ typedef union
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -344,7 +401,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -372,7 +429,7 @@ typedef struct
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
@@ -447,15 +504,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -465,7 +522,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -495,7 +552,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -505,11 +562,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
@@ -519,7 +576,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -550,7 +607,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -612,9 +669,9 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
@@ -625,7 +682,7 @@ typedef struct
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -637,7 +694,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -653,7 +710,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -665,7 +722,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -677,7 +734,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -692,12 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
}
@@ -715,10 +774,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -730,10 +791,10 @@ __STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -766,15 +827,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -784,10 +845,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h
similarity index 85%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h
index 122c9aa4a..092ee23da 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm3.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm3.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,8 +68,8 @@
*/
/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
__CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
@@ -81,6 +81,11 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
@@ -90,19 +95,21 @@
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -111,6 +118,11 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
@@ -121,21 +133,25 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include /* standard types definitions */
#include /* Core Instruction Access */
#include /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -143,6 +159,10 @@
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM3_REV
@@ -212,13 +232,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@@ -228,6 +242,22 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -241,6 +271,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -249,13 +283,7 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
@@ -267,6 +295,31 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -276,12 +329,18 @@ typedef union
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -312,7 +371,7 @@ typedef struct
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -364,7 +423,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -395,7 +454,7 @@ typedef struct
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#if (__CM3_REV < 0x0201) /* core r2p1 */
@@ -429,7 +488,7 @@ typedef struct
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
@@ -458,7 +517,7 @@ typedef struct
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
@@ -501,7 +560,7 @@ typedef struct
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
@@ -511,7 +570,7 @@ typedef struct
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
@@ -537,7 +596,7 @@ typedef struct
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -563,7 +622,7 @@ typedef struct
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
@@ -574,7 +633,7 @@ typedef struct
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -606,15 +665,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -624,7 +683,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -675,7 +734,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
@@ -703,19 +762,19 @@ typedef struct
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
@@ -725,7 +784,7 @@ typedef struct
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -818,31 +877,31 @@ typedef struct
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
@@ -870,7 +929,7 @@ typedef struct
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -913,11 +972,11 @@ typedef struct
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
@@ -930,7 +989,7 @@ typedef struct
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
@@ -941,7 +1000,7 @@ typedef struct
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
@@ -963,11 +1022,11 @@ typedef struct
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -989,15 +1048,15 @@ typedef struct
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
@@ -1016,15 +1075,15 @@ typedef struct
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
@@ -1060,7 +1119,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -1070,11 +1129,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
@@ -1084,7 +1143,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -1115,7 +1174,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -1172,14 +1231,14 @@ typedef struct
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
@@ -1219,7 +1278,7 @@ typedef struct
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
@@ -1291,13 +1350,13 @@ typedef struct
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1310,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1322,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1334,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1350,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1362,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1374,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1389,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1404,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1425,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -1437,7 +1500,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The function encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
@@ -1446,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1465,7 +1528,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
The function decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
@@ -1474,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1492,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1531,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1571,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}
@@ -1618,10 +1681,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
/*@} end of CMSIS_core_DebugFunctions */
-#endif /* __CORE_CM3_H_DEPENDANT */
-#endif /* __CMSIS_GENERIC */
+
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h
similarity index 85%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h
index 6a29982b6..9749c27d2 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,8 +68,8 @@
*/
/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
__CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
@@ -81,6 +81,11 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
@@ -90,24 +95,21 @@
#define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
-#else
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
#define __STATIC_INLINE static inline
- #define __DSB()
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
*/
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
@@ -121,6 +123,18 @@
#define __FPU_USED 0
#endif
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#if (__FPU_PRESENT == 1)
@@ -145,20 +159,20 @@
#define __FPU_USED 0
#endif
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#define __FPU_USED 0
#endif
#else
#define __FPU_USED 0
#endif
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
#if (__FPU_PRESENT == 1)
#define __FPU_USED 1
#else
@@ -171,9 +185,13 @@
#endif
#include /* standard types definitions */
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-#include "core_cm4_simd.h" /* Compiler specific SIMD Intrinsics */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
#endif /* __CORE_CM4_H_GENERIC */
@@ -182,6 +200,10 @@
#ifndef __CORE_CM4_H_DEPENDANT
#define __CORE_CM4_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM4_REV
@@ -257,13 +279,9 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@@ -273,6 +291,25 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -286,6 +323,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -294,13 +335,9 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
@@ -312,6 +349,34 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -327,6 +392,16 @@ typedef union
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -357,7 +432,7 @@ typedef struct
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -409,7 +484,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -440,7 +515,7 @@ typedef struct
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
@@ -466,7 +541,7 @@ typedef struct
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
@@ -495,7 +570,7 @@ typedef struct
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
@@ -538,7 +613,7 @@ typedef struct
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
@@ -548,7 +623,7 @@ typedef struct
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
@@ -574,7 +649,7 @@ typedef struct
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -596,7 +671,7 @@ typedef struct
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
@@ -612,7 +687,7 @@ typedef struct
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -644,15 +719,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -662,7 +737,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -713,7 +788,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
@@ -741,19 +816,19 @@ typedef struct
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
@@ -763,7 +838,7 @@ typedef struct
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -856,31 +931,31 @@ typedef struct
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
@@ -908,7 +983,7 @@ typedef struct
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -951,11 +1026,11 @@ typedef struct
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
@@ -968,7 +1043,7 @@ typedef struct
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
@@ -979,7 +1054,7 @@ typedef struct
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
@@ -1001,11 +1076,11 @@ typedef struct
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -1027,15 +1102,15 @@ typedef struct
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
@@ -1054,15 +1129,15 @@ typedef struct
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
@@ -1098,7 +1173,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -1108,11 +1183,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
@@ -1122,7 +1197,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -1153,7 +1228,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -1204,7 +1279,7 @@ typedef struct
#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
/* Floating-Point Context Address Register */
#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
@@ -1246,7 +1321,7 @@ typedef struct
#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
/* Media and FP Feature Register 1 */
#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
@@ -1259,7 +1334,7 @@ typedef struct
#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
/*@} end of group CMSIS_FPU */
#endif
@@ -1316,14 +1391,14 @@ typedef struct
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
@@ -1363,7 +1438,7 @@ typedef struct
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
@@ -1440,13 +1515,13 @@ typedef struct
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1459,7 +1534,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1471,8 +1546,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1484,7 +1558,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1500,7 +1574,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1512,7 +1586,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1524,7 +1598,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1539,7 +1613,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1554,10 +1628,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1575,10 +1651,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -1587,7 +1665,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The function encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
@@ -1596,16 +1674,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1615,7 +1693,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
The function decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
@@ -1624,15 +1702,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1642,13 +1720,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1681,15 +1759,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1721,11 +1799,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}
@@ -1768,10 +1846,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
/*@} end of CMSIS_core_DebugFunctions */
-#endif /* __CORE_CM4_H_DEPENDANT */
-#endif /* __CMSIS_GENERIC */
+
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h
similarity index 100%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cm4_simd.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm4_simd.h
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h
new file mode 100755
index 000000000..842e323f6
--- /dev/null
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cm7.h
@@ -0,0 +1,2397 @@
+/**************************************************************************//**
+ * @file core_cm7.h
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \ingroup Cortex_M7
+ @{
+ */
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x07) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0
+ #endif
+ #else
+ #define __FPU_USED 0
+ #endif
+#endif
+
+#include /* standard types definitions */
+#include /* Core Instruction Access */
+#include /* Core Function Access */
+#include /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM7_REV
+ #define __CM7_REV 0x0000
+ #warning "__CM7_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __ICACHE_PRESENT
+ #define __ICACHE_PRESENT 0
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DCACHE_PRESENT
+ #define __DCACHE_PRESENT 0
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __DTCM_PRESENT
+ #define __DTCM_PRESENT 0
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 3
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ IO Type Qualifiers are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16 /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[1];
+ __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
+ __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
+ __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
+ __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED3[93];
+ __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
+ uint32_t RESERVED4[15];
+ __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */
+ uint32_t RESERVED5[1];
+ __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
+ uint32_t RESERVED6[1];
+ __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
+ __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
+ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
+ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
+ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
+ __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
+ __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
+ __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
+ uint32_t RESERVED7[6];
+ __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */
+ __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */
+ __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */
+ __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */
+ __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */
+ uint32_t RESERVED8[1];
+ __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/* Cache Level ID register */
+#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */
+
+/* Cache Type register */
+#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
+
+/* Cache Size ID Register */
+#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
+
+/* Cache Size Selection Register */
+#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register */
+#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register*/
+#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Registers */
+#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register */
+#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register */
+#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */
+
+/* AHBS control register */
+#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register */
+#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1];
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1];
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1];
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+ uint32_t RESERVED3[981];
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/** \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2];
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55];
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131];
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759];
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1];
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39];
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8];
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/** \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+ __I uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ The function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ The function reads the priority grouping field from the NVIC Interrupt Controller.
+
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/** \brief Enable External Interrupt
+
+ The function enables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Disable External Interrupt
+
+ The function disables a device-specific interrupt in the NVIC interrupt controller.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Pending Interrupt
+
+ The function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Pending Interrupt
+
+ The function sets the pending bit of an external interrupt.
+
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ The function clears the pending bit of an external interrupt.
+
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/** \brief Get Active Interrupt
+
+ The function reads the active register in NVIC and returns the active bit.
+
+ \param [in] IRQn Interrupt number.
+
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/** \brief Set Interrupt Priority
+
+ The function sets the priority of an interrupt.
+
+ \note The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if((int32_t)IRQn < 0) {
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/** \brief Get Interrupt Priority
+
+ The function reads the priority of an interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority. Value is aligned automatically to the implemented
+ priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
+ else {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/** \brief Encode Priority
+
+ The function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ The function decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/** \brief System Reset
+
+ The function initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ########################## FPU functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions
+ \brief Function that provides FPU type.
+ @{
+ */
+
+/**
+ \fn uint32_t SCB_GetFPUType(void)
+ \brief get FPU type
+ \returns
+ - \b 0: No FPU
+ - \b 1: Single precision FPU
+ - \b 2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+ uint32_t mvfr0;
+
+ mvfr0 = SCB->MVFR0;
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
+ return 2UL; // Double + Single precision FPU
+ } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
+ return 1UL; // Single precision FPU
+ } else {
+ return 0UL; // No FPU
+ }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ########################## Cache functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions
+ \brief Functions that configure Instruction and Data cache.
+ @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
+#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ )
+
+
+/** \brief Enable I-Cache
+
+ The function turns on I-Cache
+ */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL; // invalidate I-Cache
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable I-Cache
+
+ The function turns off I-Cache
+ */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
+ SCB->ICIALLU = 0UL; // invalidate I-Cache
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate I-Cache
+
+ The function invalidates I-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+ #if (__ICACHE_PRESENT == 1)
+ __DSB();
+ __ISB();
+ SCB->ICIALLU = 0UL;
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Enable D-Cache
+
+ The function turns on D-Cache
+ */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+ __DSB();
+
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Disable D-Cache
+
+ The function turns off D-Cache
+ */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
+
+ do { // clean & invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Invalidate D-Cache
+
+ The function invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean D-Cache
+
+ The function cleans D-Cache
+ */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // clean D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCSW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/** \brief Clean & Invalidate D-Cache
+
+ The function cleans and Invalidates D-Cache
+ */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+ #if (__DCACHE_PRESENT == 1)
+ uint32_t ccsidr, sshift, wshift, sw;
+ uint32_t sets, ways;
+
+ SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache
+ ccsidr = SCB->CCSIDR;
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+ sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+ wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
+
+ __DSB();
+
+ do { // clean & invalidate D-Cache
+ uint32_t tmpways = ways;
+ do {
+ sw = ((tmpways << wshift) | (sets << sshift));
+ SCB->DCCISW = sw;
+ } while(tmpways--);
+ } while(sets--);
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Invalidate by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t)addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Clean by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/**
+ \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
+ \brief D-Cache Clean and Invalidate by address
+ \param[in] addr address (aligned to 32-byte boundary)
+ \param[in] dsize size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+ #if (__DCACHE_PRESENT == 1)
+ int32_t op_size = dsize;
+ uint32_t op_addr = (uint32_t) addr;
+ uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
+
+ __DSB();
+
+ while (op_size > 0) {
+ SCB->DCCIMVAC = op_addr;
+ op_addr += linesize;
+ op_size -= (int32_t)linesize;
+ }
+
+ __DSB();
+ __ISB();
+ #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts.
+
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+
+ \note When the variable __Vendor_SysTickConfig is set to 1, then the
+ function SysTick_Config is not included. In this case, the file device.h
+ must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/** \brief ITM Send Character
+
+ The function transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+
+ \param [in] ch Character to transmit.
+
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ The function inputs a character via the external variable \ref ITM_RxBuffer.
+
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h
similarity index 91%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h
index 0a18fafc3..b6ad0a4c5 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmFunc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmFunc.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -198,7 +198,7 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
}
-#if (__CORTEX_M >= 0x03)
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief Enable FIQ
@@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xff);
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@@ -267,10 +281,10 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
__regFaultMask = (faultMask & (uint32_t)1);
}
-#endif /* (__CORTEX_M >= 0x03) */
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-#if (__CORTEX_M == 0x04)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@@ -303,19 +317,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
#endif
}
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
@@ -530,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
return(result);
}
@@ -547,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v
}
+/** \brief Set Base Priority with condition
+
+ This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
@@ -576,7 +591,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t
#endif /* (__CORTEX_M >= 0x03) */
-#if (__CORTEX_M == 0x04)
+#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
/** \brief Get FPSCR
@@ -616,21 +631,34 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fps
#endif
}
-#endif /* (__CORTEX_M == 0x04) */
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
-
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
-
#endif /* __CORE_CMFUNC_H */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h
similarity index 61%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h
index d213f0eed..fca425c51 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_cmInstr.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmInstr.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2014 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -89,24 +89,33 @@
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-#define __ISB() __isb(0xF)
-
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-#define __DSB() __dsb(0xF)
-
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-#define __DMB() __dmb(0xF)
-
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0)
/** \brief Reverse byte order (32 bit)
@@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __BKPT(value) __breakpoint(value)
-#if (__CORTEX_M >= 0x03)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -180,12 +187,42 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse
\return Reversed value
*/
-#define __RBIT __rbit
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+ return(result);
+}
+#endif
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
/** \brief LDR Exclusive (8 bit)
- This function performs a exclusive LDR command for 8 bit value.
+ This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
@@ -195,7 +232,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief LDR Exclusive (16 bit)
- This function performs a exclusive LDR command for 16 bit values.
+ This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
@@ -205,7 +242,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief LDR Exclusive (32 bit)
- This function performs a exclusive LDR command for 32 bit values.
+ This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
@@ -215,7 +252,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (8 bit)
- This function performs a exclusive STR command for 8 bit values.
+ This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -227,7 +264,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (16 bit)
- This function performs a exclusive STR command for 16 bit values.
+ This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -239,7 +276,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/** \brief STR Exclusive (32 bit)
- This function performs a exclusive STR command for 32 bit values.
+ This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
@@ -279,29 +316,83 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __USAT __usat
-/** \brief Count leading zeros
+/** \brief Rotate Right with Extend (32 bit)
- This function counts the number of leading zeros of a data value.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
+ \param [in] value Value to rotate
+ \return Rotated value
*/
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+/** \brief LDRT Unprivileged (8 bit)
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
-#include
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
+/** \brief LDRT Unprivileged (16 bit)
-#include
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
@@ -322,7 +413,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
@@ -333,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
@@ -344,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
@@ -354,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
@@ -366,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
- __ASM volatile ("isb");
+ __ASM volatile ("isb 0xF":::"memory");
}
@@ -377,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
- __ASM volatile ("dsb");
+ __ASM volatile ("dsb 0xF":::"memory");
}
@@ -388,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
- __ASM volatile ("dmb");
+ __ASM volatile ("dmb 0xF":::"memory");
}
@@ -401,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
@@ -421,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
@@ -437,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
@@ -458,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
\param [in] value Number of Bits to rotate
\return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
- return (op1 >> op2) | (op1 << (32 - op2));
+ return (op1 >> op2) | (op1 << (32 - op2));
}
@@ -475,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
#define __BKPT(value) __ASM volatile ("bkpt "#value)
-#if (__CORTEX_M >= 0x03)
-
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
@@ -484,23 +573,48 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1,
\param [in] value Value to reverse
\return Reversed value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
+
+ result = value; // r will be reversed bits of v; first get LSB of v
+ for (value >>= 1; value; value >>= 1)
+ {
+ result <<= 1;
+ result |= value & 1;
+ s--;
+ }
+ result <<= s; // shift when v's highest bits are zero
+#endif
+ return(result);
}
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
+
/** \brief LDR Exclusive (8 bit)
- This function performs a exclusive LDR command for 8 bit value.
+ This function executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
@@ -512,18 +626,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
- return(result);
+ return ((uint8_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (16 bit)
- This function performs a exclusive LDR command for 16 bit values.
+ This function executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
@@ -535,18 +649,18 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
- return(result);
+ return ((uint16_t) result); /* Add explicit type cast here */
}
/** \brief LDR Exclusive (32 bit)
- This function performs a exclusive LDR command for 32 bit values.
+ This function executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
@@ -557,50 +671,50 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
/** \brief STR Exclusive (8 bit)
- This function performs a exclusive STR command for 8 bit values.
+ This function executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
- This function performs a exclusive STR command for 16 bit values.
+ This function executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
- This function performs a exclusive STR command for 32 bit values.
+ This function executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
@@ -614,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
This function removes the exclusive lock which is created by LDREX.
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
@@ -652,35 +766,149 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
})
-/** \brief Count leading zeros
+/** \brief Rotate Right with Extend (32 bit)
- This function counts the number of leading zeros of a data value.
+ This function moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
+ \param [in] value Value to rotate
+ \return Rotated value
*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
{
- uint32_t result;
+ uint32_t result;
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
-#endif /* (__CORTEX_M >= 0x03) */
+
+/** \brief LDRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged LDRT instruction for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+/** \brief LDRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged LDRT instruction for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/** \brief LDRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged LDRT instruction for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/** \brief STRT Unprivileged (8 bit)
+
+ This function executes a Unprivileged STRT instruction for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (16 bit)
+
+ This function executes a Unprivileged STRT instruction for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/** \brief STRT Unprivileged (32 bit)
+
+ This function executes a Unprivileged STRT instruction for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
-
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h
new file mode 100755
index 000000000..7b8e37fff
--- /dev/null
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_cmSimd.h
@@ -0,0 +1,697 @@
+/**************************************************************************//**
+ * @file core_cmSimd.h
+ * @brief CMSIS Cortex-M SIMD Header File
+ * @version V4.10
+ * @date 18. March 2015
+ *
+ * @note
+ *
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2014 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32) ) >> 32))
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ // Little endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else // Big endian
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#include
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+#include
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+/* not yet supported */
+
+
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
+/* Cosmic specific functions */
+#include
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h
similarity index 81%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h
index 1a2a0f2e3..44cb02747 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc000.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc000.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,12 +68,12 @@
*/
/* CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_SC (0) /*!< Cortex secure core */
+#define __CORTEX_SC (000) /*!< Cortex secure core */
#if defined ( __CC_ARM )
@@ -81,14 +81,18 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
@@ -96,9 +100,16 @@
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -107,26 +118,40 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include /* standard types definitions */
#include /* Core Instruction Access */
#include /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_SC000_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -134,6 +159,10 @@
#ifndef __CORE_SC000_H_DEPENDANT
#define __CORE_SC000_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC000_REV
@@ -202,14 +231,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -218,6 +240,19 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -231,6 +266,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -239,16 +278,9 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
@@ -257,6 +289,25 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -264,14 +315,17 @@ typedef union
{
struct
{
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
/*@} end of group CMSIS_CORE */
@@ -320,7 +374,7 @@ typedef struct
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
uint32_t RESERVED1[154];
- __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
@@ -337,7 +391,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -365,7 +419,7 @@ typedef struct
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
@@ -408,13 +462,6 @@ typedef struct
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-/* SCB Security Features Register Definitions */
-#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
-#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
-
-#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
-#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
-
/*@} end of group CMSIS_SCB */
@@ -434,7 +481,7 @@ typedef struct
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -466,15 +513,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -484,7 +531,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -514,7 +561,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -524,11 +571,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
@@ -538,7 +585,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -569,7 +616,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -632,9 +679,9 @@ typedef struct
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
+#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
+#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
+#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
/** \brief Enable External Interrupt
@@ -645,7 +692,7 @@ typedef struct
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -657,7 +704,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -673,7 +720,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+ return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -685,7 +732,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+ NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -697,7 +744,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -712,12 +759,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ if((int32_t)(IRQn) < 0) {
+ SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+ NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ }
}
@@ -735,10 +784,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
+ if((int32_t)(IRQn) < 0) {
+ return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -750,10 +801,10 @@ __STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -786,15 +837,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -804,10 +855,10 @@ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h
similarity index 84%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h
index cc34d6fc0..7e40672a9 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/CMSIS/Include/core_sc300.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/CMSIS/Include/core_sc300.h
@@ -1,13 +1,13 @@
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
+ * @version V4.10
+ * @date 18. March 2015
*
* @note
*
******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
+/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@@ -39,13 +39,13 @@
#pragma system_include /* treat file as system include file for MISRA check */
#endif
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
#ifdef __cplusplus
extern "C" {
#endif
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
@@ -68,12 +68,12 @@
*/
/* CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
__SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-#define __CORTEX_SC (300) /*!< Cortex secure core */
+#define __CORTEX_SC (300) /*!< Cortex secure core */
#if defined ( __CC_ARM )
@@ -81,24 +81,35 @@
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
+ #define __STATIC_INLINE static inline
+
#endif
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
+/** __FPU_USED indicates whether an FPU is used or not.
+ This core does not support an FPU at all
*/
#define __FPU_USED 0
@@ -107,26 +118,40 @@
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI__VFP_SUPPORT____
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
+
+#elif defined ( __CSMC__ ) /* Cosmic */
+ #if ( __CSMC__ & 0x400) // FPU present for parser
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
#endif
#include /* standard types definitions */
#include /* Core Instruction Access */
#include /* Core Function Access */
+#ifdef __cplusplus
+}
+#endif
+
#endif /* __CORE_SC300_H_GENERIC */
#ifndef __CMSIS_GENERIC
@@ -134,6 +159,10 @@
#ifndef __CORE_SC300_H_DEPENDANT
#define __CORE_SC300_H_DEPENDANT
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __SC300_REV
@@ -203,13 +232,7 @@ typedef union
{
struct
{
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
@@ -219,6 +242,22 @@ typedef union
uint32_t w; /*!< Type used for word access */
} APSR_Type;
+/* APSR Register Definitions */
+#define APSR_N_Pos 31 /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30 /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29 /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28 /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27 /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
@@ -232,6 +271,10 @@ typedef union
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
@@ -240,13 +283,7 @@ typedef union
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
@@ -258,6 +295,31 @@ typedef union
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31 /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29 /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28 /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24 /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
/** \brief Union type to access the Control Registers (CONTROL).
*/
@@ -267,12 +329,18 @@ typedef union
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
/*@} end of group CMSIS_CORE */
@@ -303,7 +371,7 @@ typedef struct
/* Software Triggered Interrupt Register Definitions */
#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
/*@} end of group CMSIS_NVIC */
@@ -339,6 +407,8 @@ typedef struct
__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
uint32_t RESERVED0[5];
__IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+ uint32_t RESERVED1[129];
+ __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
@@ -355,7 +425,7 @@ typedef struct
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
@@ -386,7 +456,7 @@ typedef struct
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Vector Table Offset Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
@@ -415,7 +485,7 @@ typedef struct
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
@@ -444,7 +514,7 @@ typedef struct
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
@@ -487,7 +557,7 @@ typedef struct
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
@@ -497,7 +567,7 @@ typedef struct
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
@@ -523,7 +593,7 @@ typedef struct
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
@@ -545,7 +615,7 @@ typedef struct
/* Interrupt Controller Type Register Definitions */
#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
/*@} end of group CMSIS_SCnotSCB */
@@ -577,15 +647,15 @@ typedef struct
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
@@ -595,7 +665,7 @@ typedef struct
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
@@ -646,7 +716,7 @@ typedef struct
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
@@ -674,19 +744,19 @@ typedef struct
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
@@ -696,7 +766,7 @@ typedef struct
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
@@ -789,31 +859,31 @@ typedef struct
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
/* DWT CPI Count Register Definitions */
#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
/* DWT Exception Overhead Count Register Definitions */
#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
/* DWT Sleep Count Register Definitions */
#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
/* DWT LSU Count Register Definitions */
#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
/* DWT Folded-instruction Count Register Definitions */
#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
/* DWT Comparator Mask Register Definitions */
#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
/* DWT Comparator Function Register Definitions */
#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
@@ -841,7 +911,7 @@ typedef struct
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
/*@}*/ /* end of group CMSIS_DWT */
@@ -884,11 +954,11 @@ typedef struct
/* TPI Asynchronous Clock Prescaler Register Definitions */
#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
/* TPI Selected Pin Protocol Register Definitions */
#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
/* TPI Formatter and Flush Status Register Definitions */
#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
@@ -901,7 +971,7 @@ typedef struct
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
/* TPI Formatter and Flush Control Register Definitions */
#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
@@ -912,7 +982,7 @@ typedef struct
/* TPI TRIGGER Register Definitions */
#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
/* TPI Integration ETM Data Register Definitions (FIFO0) */
#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
@@ -934,11 +1004,11 @@ typedef struct
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
/* TPI ITATBCTR2 Register Definitions */
#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
/* TPI Integration ITM Data Register Definitions (FIFO1) */
#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
@@ -960,15 +1030,15 @@ typedef struct
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
/* TPI ITATBCTR0 Register Definitions */
#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
/* TPI Integration Mode Control Register Definitions */
#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
/* TPI DEVID Register Definitions */
#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
@@ -987,15 +1057,15 @@ typedef struct
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
/*@}*/ /* end of group CMSIS_TPI */
@@ -1031,7 +1101,7 @@ typedef struct
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
@@ -1041,11 +1111,11 @@ typedef struct
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
@@ -1055,7 +1125,7 @@ typedef struct
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
@@ -1086,7 +1156,7 @@ typedef struct
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
@@ -1143,14 +1213,14 @@ typedef struct
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
@@ -1190,7 +1260,7 @@ typedef struct
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
@@ -1262,13 +1332,13 @@ typedef struct
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
@@ -1281,7 +1351,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
*/
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
}
@@ -1293,7 +1363,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1305,7 +1375,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1321,7 +1391,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1333,7 +1403,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1345,7 +1415,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
}
@@ -1360,7 +1430,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
@@ -1375,10 +1445,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ if((int32_t)IRQn < 0) {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
}
@@ -1396,10 +1468,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ if((int32_t)IRQn < 0) {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
+ }
else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
+ }
}
@@ -1408,7 +1482,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
The function encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
@@ -1417,16 +1491,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
@@ -1436,7 +1510,7 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
The function decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
@@ -1445,15 +1519,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
@@ -1463,13 +1537,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1) { __NOP(); } /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
@@ -1502,15 +1576,15 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
}
#endif
@@ -1542,11 +1616,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable
*/
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
{
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
+ while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
+ ITM->PORT[0].u8 = (uint8_t)ch;
}
return (ch);
}
@@ -1589,10 +1663,13 @@ __STATIC_INLINE int32_t ITM_CheckChar (void) {
/*@} end of CMSIS_core_DebugFunctions */
-#endif /* __CORE_SC300_H_DEPENDANT */
-#endif /* __CMSIS_GENERIC */
+
#ifdef __cplusplus
}
#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
index bb61b4010..3d05713bf 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file misc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the miscellaneous
* firmware library functions (add-on to CMSIS functions).
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
index 2ac904d21..6efce5184 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_adc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the ADC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -325,13 +325,13 @@ typedef struct
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_18 ((uint8_t)0x12)
-#if defined (STM32F40_41xxx)
+#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_18)
-#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE */
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#define ADC_Channel_Vbat ((uint8_t)ADC_Channel_18)
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
index 790e50027..67b3b611e 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_can.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the CAN firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -46,9 +46,14 @@
*/
/* Exported types ------------------------------------------------------------*/
-
+#if defined(STM32F413_423xx)
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+ ((PERIPH) == CAN2) || \
+ ((PERIPH) == CAN3))
+#else
#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
((PERIPH) == CAN2))
+#endif /* STM32F413_423xx */
/**
* @brief CAN init structure definition
@@ -594,9 +599,17 @@ void CAN_DeInit(CAN_TypeDef* CANx);
/* Initialization and Configuration functions *********************************/
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+#if defined(STM32F413_423xx)
+void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+#else
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+#endif /* STM32F413_423xx */
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+#if defined(STM32F413_423xx)
+void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber);
+#else
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
+#endif /* STM32F413_423xx */
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
similarity index 95%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
index 9fb34f9e3..58bc88569 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_crc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the CRC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
index 2d70d8b2b..33212ae67 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_cryp.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the Cryptographic
* processor(CRYP) firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
index 13ce2e80b..0bea63362 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_dac.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the DAC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
similarity index 95%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
index 971cd60b3..9a7536ca4 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the DBGMCU firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -34,7 +34,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
index fa7150090..d15020281 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_dcmi.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the DCMI firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
index 0536d02c5..3c0c38969 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_dma.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the DMA firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h
index 4c065a5a5..b661311a9 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma2d.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_dma2d.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the DMA2D firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -69,11 +69,11 @@ typedef struct
uint32_t DMA2D_OutputGreen; /*!< configures the green value of the output image.
This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is slected
- - from 0x00 to 0xFF if RGB888 color mode is slected
- - from 0x00 to 0x2F if RGB565 color mode is slected
- - from 0x00 to 0x1F if ARGB1555 color mode is slected
- - from 0x00 to 0x0F if ARGB4444 color mode is slected */
+ - from 0x00 to 0xFF if ARGB8888 color mode is selected
+ - from 0x00 to 0xFF if RGB888 color mode is selected
+ - from 0x00 to 0x2F if RGB565 color mode is selected
+ - from 0x00 to 0x1F if ARGB1555 color mode is selected
+ - from 0x00 to 0x0F if ARGB4444 color mode is selected */
uint32_t DMA2D_OutputRed; /*!< configures the red value of the output image.
This parameter must range:
@@ -85,9 +85,9 @@ typedef struct
uint32_t DMA2D_OutputAlpha; /*!< configures the alpha channel of the output color.
This parameter must range:
- - from 0x00 to 0xFF if ARGB8888 color mode is slected
- - from 0x00 to 0x01 if ARGB1555 color mode is slected
- - from 0x00 to 0x0F if ARGB4444 color mode is slected */
+ - from 0x00 to 0xFF if ARGB8888 color mode is selected
+ - from 0x00 to 0x01 if ARGB1555 color mode is selected
+ - from 0x00 to 0x0F if ARGB4444 color mode is selected */
uint32_t DMA2D_OutputMemoryAdd; /*!< Specifies the memory address. This parameter
must be range from 0x00000000 to 0xFFFFFFFF. */
@@ -98,7 +98,7 @@ typedef struct
uint32_t DMA2D_NumberOfLine; /*!< Configures the number of line of the area to be transfered.
This parameter must range from 0x0000 to 0xFFFF */
- uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transfered.
+ uint32_t DMA2D_PixelPerLine; /*!< Configures the number pixel per line of the area to be transferred.
This parameter must range from 0x0000 to 0x3FFF */
} DMA2D_InitTypeDef;
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
similarity index 95%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
index 15eea4881..e89061608 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_exti.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the EXTI firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -124,7 +124,9 @@ typedef struct
#define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
+
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
@@ -139,7 +141,7 @@ typedef struct
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
- ((LINE) == EXTI_Line22))
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
/**
* @}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
similarity index 96%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
index ea850387c..bae424d35 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_flash.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the FLASH
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -166,26 +166,35 @@ typedef enum
((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) ||\
((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F469_479xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x081FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined (STM32F40_41xxx)
+#if defined (STM32F40_41xxx) || defined(STM32F412xG)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG */
#if defined (STM32F401xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
#endif /* STM32F401xx */
-#if defined (STM32F411xE)
+#if defined (STM32F411xE) || defined (STM32F446xx)
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) ||\
(((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
-#endif /* STM32F411xE */
+#endif /* STM32F411xE || STM32F446xx */
+#if defined (STM32F410xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
+#endif /* STM32F410xx */
+
+#if defined(STM32F413_423xx)
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0817FFFF)) ||\
+ (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7BDF)))
+#endif /* STM32F413_423xx */
/**
* @}
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h
similarity index 96%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h
index 8ac175aed..562b5b180 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash_ramfunc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_flash_ramfunc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h
index d071b1ab5..c66aab4ab 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fmc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_fmc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the FMC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
index deb0b0d24..bf9aefad6 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_fsmc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the FSMC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
similarity index 77%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
index e7a9456ed..4c7195540 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_gpio.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the GPIO firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -248,13 +248,18 @@ typedef struct
#define GPIO_AF_TAMPER ((uint8_t)0x00) /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
#define GPIO_AF_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */
+#endif /* STM32F446xx */
/**
* @brief AF 1 selection
*/
#define GPIO_AF_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
-
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define GPIO_AF_LPTIM ((uint8_t)0x01) /* LPTIM Alternate Function mapping */
+#endif /* STM32F410xx || STM32F413_423xx */
/**
* @brief AF 2 selection
*/
@@ -269,20 +274,31 @@ typedef struct
#define GPIO_AF_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define GPIO_AF_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define GPIO_AF_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
-
+#if defined(STM32F446xx)
+#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF3_DFSDM2 ((uint8_t)0x03) /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 4 selection
*/
#define GPIO_AF_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
+#if defined(STM32F446xx)
+#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define GPIO_AF_FMPI2C ((uint8_t)0x04) /* FMPI2C Alternate Function mapping */
+#endif /* STM32F410xx || STM32F446xx */
/**
* @brief AF 5 selection
*/
#define GPIO_AF_SPI1 ((uint8_t)0x05) /* SPI1/I2S1 Alternate Function mapping */
#define GPIO_AF_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
-#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE Devices) */
+#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping (Only for STM32F411xE and STM32F413_423xx Devices) */
#define GPIO_AF_SPI4 ((uint8_t)0x05) /* SPI4/I2S4 Alternate Function mapping */
#define GPIO_AF_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
@@ -291,10 +307,18 @@ typedef struct
* @brief AF 6 selection
*/
#define GPIO_AF_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
-#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F411xE Devices) */
+#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping (Only for STM32F410xx Devices) */
+#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping (Only for STM32F411xE Devices) */
-#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F411xE Devices) */
+#define GPIO_AF6_SPI5 ((uint8_t)0x06) /* SPI5 Alternate Function mapping (Only for STM32F410xx/STM32F411xE Devices) */
#define GPIO_AF_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
+#define GPIO_AF_I2S2ext ((uint8_t)0x06) /* I2S2ext_SD Alternate Function mapping (only for STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM1 Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF6_DFSDM2 ((uint8_t)0x06) /* DFSDM2 Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 7 selection
@@ -303,6 +327,10 @@ typedef struct
#define GPIO_AF_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3/I2S3ext Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF7_DFSDM2 ((uint8_t)0x07) /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF7_SAI1 ((uint8_t)0x07) /* SAI1 Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 7 selection Legacy
@@ -317,6 +345,15 @@ typedef struct
#define GPIO_AF_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define GPIO_AF_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define GPIO_AF_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF8_USART3 ((uint8_t)0x08) /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1 ((uint8_t)0x08) /* DFSDM Alternate Function mapping */
+#define GPIO_AF8_CAN1 ((uint8_t)0x08) /* CAN1 Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F446xx)
+#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
+#define GPIO_AF_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
+#endif /* STM32F446xx */
/**
* @brief AF 9 selection
@@ -326,31 +363,60 @@ typedef struct
#define GPIO_AF_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
-
-#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
-#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE Devices) */
+#define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping (Only for STM32F401xx/STM32F410xx/STM32F411xE/STM32F412xG/STM32F413_423xx Devices) */
+#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping (Only for STM32F401xx/STM32F411xE/STM32F412xG and STM32F413_423xx Devices) */
+#if defined(STM32F446xx)
+#define GPIO_AF9_SAI2 ((uint8_t)0x09) /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF9_FMPI2C ((uint8_t)0x09) /* FMPI2C Alternate Function mapping (Only for STM32F410xx Devices) */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
/**
* @brief AF 10 selection
*/
#define GPIO_AF_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
#define GPIO_AF_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
-
+#if defined(STM32F446xx)
+#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
+#endif /* STM32F446xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* QuadSPI Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define GPIO_AF10_FMC ((uint8_t)0xA) /* FMC Alternate Function mapping */
+#define GPIO_AF10_DFSDM1 ((uint8_t)0xA) /* DFSDM Alternate Function mapping */
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define GPIO_AF10_DFSDM2 ((uint8_t)0x0A) /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_SAI1 ((uint8_t)0x0A) /* SAI1 Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 11 selection
*/
#define GPIO_AF_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF11_UART4 ((uint8_t)0x0B) /* UART4 Alternate Function mapping */
+#define GPIO_AF11_UART5 ((uint8_t)0x0B) /* UART5 Alternate Function mapping */
+#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
+#define GPIO_AF11_UART10 ((uint8_t)0x0B) /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3 ((uint8_t)0x0B) /* CAN3 Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 12 selection
*/
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define GPIO_AF_FSMC ((uint8_t)0xC) /* FSMC Alternate Function mapping */
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
#define GPIO_AF_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
#define GPIO_AF_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF_SDIO ((uint8_t)0xC) /* SDIO Alternate Function mapping */
@@ -359,19 +425,23 @@ typedef struct
* @brief AF 13 selection
*/
#define GPIO_AF_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
-
+#if defined(STM32F469_479xx)
+#define GPIO_AF_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
+#endif /* STM32F469_479xx */
/**
* @brief AF 14 selection
*/
-
#define GPIO_AF_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
+#if defined(STM32F413_423xx)
+#define GPIO_AF14_RNG ((uint8_t)0x0E) /* RNG Alternate Function mapping */
+#endif /* STM32F413_423xx */
/**
* @brief AF 15 selection
*/
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
@@ -392,7 +462,7 @@ typedef struct
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_FSMC))
#endif /* STM32F40_41xxx */
-#if defined (STM32F401xx)
+#if defined(STM32F401xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
@@ -409,11 +479,15 @@ typedef struct
((AF) == GPIO_AF_EVENTOUT) || ((AF) == GPIO_AF_SPI4))
#endif /* STM32F401xx */
-#if defined (STM32F411xE)
+#if defined(STM32F411xE)
#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 13) && ((AF) != 14))
#endif /* STM32F411xE */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F410xx)
+#define IS_GPIO_AF(AF) (((AF) < 10) || ((AF) == 15))
+#endif /* STM32F410xx */
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_TIM14) || \
((AF) == GPIO_AF_MCO) || ((AF) == GPIO_AF_TAMPER) || \
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
@@ -437,7 +511,23 @@ typedef struct
((AF) == GPIO_AF_FMC) || ((AF) == GPIO_AF_SAI1) || \
((AF) == GPIO_AF_LTDC))
#endif /* STM32F427_437xx || STM32F429_439xx */
-
+
+#if defined(STM32F412xG)
+#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F412xG */
+
+#if defined(STM32F413_423xx)
+#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 13))
+#endif /* STM32F413_423xx */
+
+#if defined(STM32F446xx)
+#define IS_GPIO_AF(AF) (((AF) < 16) && ((AF) != 11) && ((AF) != 14))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469_479xx)
+#define IS_GPIO_AF(AF) ((AF) < 16)
+#endif /* STM32F469_479xx */
+
/**
* @}
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
index 6994e1b9f..28b2d6ba6 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_hash.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the HASH
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
index c8d1a3698..ade420d7f 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_i2c.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the I2C firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -78,11 +78,9 @@ typedef struct
/** @defgroup I2C_Exported_Constants
* @{
*/
-
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
((PERIPH) == I2C2) || \
((PERIPH) == I2C3))
-
/** @defgroup I2C_Digital_Filter
* @{
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
index 44d25432b..b8c75fead 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_iwdg.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the IWDG
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h
similarity index 96%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h
index 8e76c5281..260cd3f0f 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_ltdc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_ltdc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the LTDC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -69,24 +69,24 @@ typedef struct
width. This parameter must range from 0x000 to 0xFFF. */
uint32_t LTDC_VerticalSync; /*!< configures the number of Vertical synchronization
- heigh. This parameter must range from 0x000 to 0x7FF. */
+ height. This parameter must range from 0x000 to 0x7FF. */
uint32_t LTDC_AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must range from LTDC_HorizontalSync to 0xFFF. */
- uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch heigh.
+ uint32_t LTDC_AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must range from LTDC_VerticalSync to 0x7FF. */
uint32_t LTDC_AccumulatedActiveW; /*!< configures the accumulated active width. This parameter
must range from LTDC_AccumulatedHBP to 0xFFF. */
- uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active heigh. This parameter
+ uint32_t LTDC_AccumulatedActiveH; /*!< configures the accumulated active height. This parameter
must range from LTDC_AccumulatedVBP to 0x7FF. */
uint32_t LTDC_TotalWidth; /*!< configures the total width. This parameter
must range from LTDC_AccumulatedActiveW to 0xFFF. */
- uint32_t LTDC_TotalHeigh; /*!< configures the total heigh. This parameter
+ uint32_t LTDC_TotalHeigh; /*!< configures the total height. This parameter
must range from LTDC_AccumulatedActiveH to 0x7FF. */
uint32_t LTDC_BackgroundRedValue; /*!< configures the background red value.
@@ -156,13 +156,15 @@ typedef struct
/**
* @brief LTDC Position structure definition
*/
-
typedef struct
{
uint32_t LTDC_POSX; /*!< Current X Position */
uint32_t LTDC_POSY; /*!< Current Y Position */
} LTDC_PosTypeDef;
+/**
+ * @brief LTDC RGB structure definition
+ */
typedef struct
{
uint32_t LTDC_BlueWidth; /*!< Blue width */
@@ -170,6 +172,9 @@ typedef struct
uint32_t LTDC_RedWidth; /*!< Red width */
} LTDC_RGBTypeDef;
+/**
+ * @brief LTDC Color Keying structure definition
+ */
typedef struct
{
uint32_t LTDC_ColorKeyBlue; /*!< Configures the color key blue value.
@@ -182,6 +187,9 @@ typedef struct
This parameter must range from 0x00 to 0xFF. */
} LTDC_ColorKeying_InitTypeDef;
+/**
+ * @brief LTDC CLUT structure definition
+ */
typedef struct
{
uint32_t LTDC_CLUTAdress; /*!< Configures the CLUT address.
@@ -198,9 +206,8 @@ typedef struct
} LTDC_CLUT_InitTypeDef;
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup LTDC_Exported_Constants
- * @}
+ * @{
*/
/** @defgroup LTDC_SYNC
@@ -218,11 +225,10 @@ typedef struct
#define IS_LTDC_AAH(AAH) ((AAH) <= LTDC_VerticalSYNC)
#define IS_LTDC_TOTALW(TOTALW) ((TOTALW) <= LTDC_HorizontalSYNC)
#define IS_LTDC_TOTALH(TOTALH) ((TOTALH) <= LTDC_VerticalSYNC)
-
/**
* @}
*/
-
+
/** @defgroup LTDC_HSPolarity
* @{
*/
@@ -230,12 +236,11 @@ typedef struct
#define LTDC_HSPolarity_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
#define IS_LTDC_HSPOL(HSPOL) (((HSPOL) == LTDC_HSPolarity_AL) || \
- ((HSPOL) == LTDC_HSPolarity_AH))
-
+ ((HSPOL) == LTDC_HSPolarity_AH))
/**
* @}
*/
-
+
/** @defgroup LTDC_VSPolarity
* @{
*/
@@ -244,11 +249,10 @@ typedef struct
#define IS_LTDC_VSPOL(VSPOL) (((VSPOL) == LTDC_VSPolarity_AL) || \
((VSPOL) == LTDC_VSPolarity_AH))
-
/**
* @}
*/
-
+
/** @defgroup LTDC_DEPolarity
* @{
*/
@@ -257,7 +261,6 @@ typedef struct
#define IS_LTDC_DEPOL(DEPOL) (((DEPOL) == LTDC_VSPolarity_AL) || \
((DEPOL) == LTDC_DEPolarity_AH))
-
/**
* @}
*/
@@ -270,7 +273,6 @@ typedef struct
#define IS_LTDC_PCPOL(PCPOL) (((PCPOL) == LTDC_PCPolarity_IPC) || \
((PCPOL) == LTDC_PCPolarity_IIPC))
-
/**
* @}
*/
@@ -283,71 +285,58 @@ typedef struct
#define IS_LTDC_RELOAD(RELOAD) (((RELOAD) == LTDC_IMReload) || \
((RELOAD) == LTDC_VBReload))
-
/**
* @}
*/
-
+
/** @defgroup LTDC_Back_Color
* @{
- */
-
+ */
#define LTDC_Back_Color ((uint32_t)0x000000FF)
#define IS_LTDC_BackBlueValue(BBLUE) ((BBLUE) <= LTDC_Back_Color)
#define IS_LTDC_BackGreenValue(BGREEN) ((BGREEN) <= LTDC_Back_Color)
#define IS_LTDC_BackRedValue(BRED) ((BRED) <= LTDC_Back_Color)
-
/**
* @}
*/
-
+
/** @defgroup LTDC_Position
* @{
*/
-
#define LTDC_POS_CY LTDC_CPSR_CYPOS
#define LTDC_POS_CX LTDC_CPSR_CXPOS
#define IS_LTDC_GET_POS(POS) (((POS) <= LTDC_POS_CY))
-
-
/**
* @}
*/
-
+
/** @defgroup LTDC_LIPosition
* @{
*/
-
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
-
/**
* @}
*/
-
+
/** @defgroup LTDC_CurrentStatus
* @{
*/
-
#define LTDC_CD_VDES LTDC_CDSR_VDES
#define LTDC_CD_HDES LTDC_CDSR_HDES
#define LTDC_CD_VSYNC LTDC_CDSR_VSYNCS
#define LTDC_CD_HSYNC LTDC_CDSR_HSYNCS
-
#define IS_LTDC_GET_CD(CD) (((CD) == LTDC_CD_VDES) || ((CD) == LTDC_CD_HDES) || \
((CD) == LTDC_CD_VSYNC) || ((CD) == LTDC_CD_HSYNC))
-
-
/**
* @}
- */
+ */
/** @defgroup LTDC_Interrupts
* @{
- */
-
+ */
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TERR LTDC_IER_TERRIE
@@ -358,24 +347,21 @@ typedef struct
/**
* @}
*/
-
+
/** @defgroup LTDC_Flag
* @{
*/
-
#define LTDC_FLAG_LI LTDC_ISR_LIF
#define LTDC_FLAG_FU LTDC_ISR_FUIF
#define LTDC_FLAG_TERR LTDC_ISR_TERRIF
#define LTDC_FLAG_RR LTDC_ISR_RRIF
-
#define IS_LTDC_FLAG(FLAG) (((FLAG) == LTDC_FLAG_LI) || ((FLAG) == LTDC_FLAG_FU) || \
((FLAG) == LTDC_FLAG_TERR) || ((FLAG) == LTDC_FLAG_RR))
-
/**
* @}
*/
-
+
/** @defgroup LTDC_Pixelformat
* @{
*/
@@ -396,39 +382,32 @@ typedef struct
/**
* @}
*/
-
+
/** @defgroup LTDC_BlendingFactor1
* @{
*/
-
#define LTDC_BlendingFactor1_CA ((uint32_t)0x00000400)
#define LTDC_BlendingFactor1_PAxCA ((uint32_t)0x00000600)
#define IS_LTDC_BlendingFactor1(BlendingFactor1) (((BlendingFactor1) == LTDC_BlendingFactor1_CA) || ((BlendingFactor1) == LTDC_BlendingFactor1_PAxCA))
-
/**
* @}
*/
-
+
/** @defgroup LTDC_BlendingFactor2
* @{
*/
-
#define LTDC_BlendingFactor2_CA ((uint32_t)0x00000005)
#define LTDC_BlendingFactor2_PAxCA ((uint32_t)0x00000007)
#define IS_LTDC_BlendingFactor2(BlendingFactor2) (((BlendingFactor2) == LTDC_BlendingFactor2_CA) || ((BlendingFactor2) == LTDC_BlendingFactor2_PAxCA))
-
-
/**
* @}
*/
-
-
+
/** @defgroup LTDC_LAYER_Config
* @{
*/
-
#define LTDC_STOPPosition ((uint32_t)0x0000FFFF)
#define LTDC_STARTPosition ((uint32_t)0x00000FFF)
@@ -447,26 +426,20 @@ typedef struct
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_ColorFrameBuffer)
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LineNumber)
-
-
-
/**
* @}
*/
-
+
/** @defgroup LTDC_colorkeying_Config
* @{
*/
-
#define LTDC_colorkeyingConfig ((uint32_t)0x000000FF)
#define IS_LTDC_CKEYING(CKEYING) ((CKEYING) <= LTDC_colorkeyingConfig)
-
-
/**
* @}
*/
-
+
/** @defgroup LTDC_CLUT_Config
* @{
*/
@@ -477,7 +450,6 @@ typedef struct
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
-
/* Function used to set the LTDC configuration to the default reset state *****/
void LTDC_DeInit(void);
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
similarity index 78%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
index 2b4336821..8e46f7089 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_pwr.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the PWR firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -102,6 +102,27 @@
/**
* @}
*/
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup PWR_Wake_Up_Pin
+ * @{
+ */
+#define PWR_WakeUp_Pin1 ((uint32_t)0x00)
+#define PWR_WakeUp_Pin2 ((uint32_t)0x01)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define PWR_WakeUp_Pin3 ((uint32_t)0x02)
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
+ ((PIN) == PWR_WakeUp_Pin2))
+#else /* STM32F410xx || STM32F412xG */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
+ ((PIN) == PWR_WakeUp_Pin3))
+#endif /* STM32F446xx */
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
/** @defgroup PWR_STOP_mode_entry
* @{
@@ -171,17 +192,29 @@ void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_PVDCmd(FunctionalState NewState);
-/* WakeUp pins configuration functions ****************************************/
+/* WakeUp pins configuration functions ****************************************/
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
void PWR_WakeUpPinCmd(FunctionalState NewState);
-
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx)
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
/* Main and Backup Regulators configuration functions *************************/
void PWR_BackupRegulatorCmd(FunctionalState NewState);
void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
void PWR_OverDriveCmd(FunctionalState NewState);
void PWR_OverDriveSWCmd(FunctionalState NewState);
void PWR_UnderDriveCmd(FunctionalState NewState);
+
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
+void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
+void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
+
+#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
+#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
/* FLASH Power Down configuration functions ***********************************/
void PWR_FlashPowerDownCmd(FunctionalState NewState);
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
similarity index 56%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
index c70da591a..c3d4cad3c 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_rcc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
- * @brief This file contains all the functions prototypes for the RCC firmware library.
+ * @version V1.8.0
+ * @date 04-November-2016
+ * @brief This file contains all the functions prototypes for the RCC firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -34,7 +34,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -82,30 +82,9 @@ typedef struct
* @}
*/
-/** @defgroup RCC_PLL_Clock_Source
+/** @defgroup RCC_PLLSAIDivR_Factor
* @{
*/
-#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE))
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
-#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
-#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
-
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-#define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
-
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
-#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
-#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
-
#define RCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
#define RCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
@@ -114,7 +93,50 @@ typedef struct
((VALUE) == RCC_PLLSAIDivR_Div4) ||\
((VALUE) == RCC_PLLSAIDivR_Div8) ||\
((VALUE) == RCC_PLLSAIDivR_Div16))
-
+/**
+ * @}
+ */
+
+/** @defgroup RCC_PLL_Clock_Source
+ * @{
+ */
+#define RCC_PLLSource_HSI ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE ((uint32_t)0x00400000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+ ((SOURCE) == RCC_PLLSource_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+#define IS_RCC_PLLI2SM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63))
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#if defined(STM32F446xx)
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
+#elif defined(STM32F412xG) || defined(STM32F413_423xx)
+#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#else
+#endif /* STM32F446xx */
+#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#endif /* STM32F446xx || STM32F469_479xx */
+#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
+#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+
+#if defined(STM32F413_423xx)
+#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
+#endif /* STM32F413_423xx */
/**
* @}
*/
@@ -122,12 +144,28 @@ typedef struct
/** @defgroup RCC_System_Clock_Source
* @{
*/
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLPCLK ((uint32_t)0x00000002)
+#define RCC_SYSCLKSource_PLLRCLK ((uint32_t)0x00000003)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+ ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLPCLK) || \
+ ((SOURCE) == RCC_SYSCLKSource_PLLRCLK))
+/* Add legacy definition */
+#define RCC_SYSCLKSource_PLLCLK RCC_SYSCLKSource_PLLPCLK
+#endif /* STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
((SOURCE) == RCC_SYSCLKSource_HSE) || \
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
/**
* @}
*/
@@ -273,7 +311,122 @@ typedef struct
/**
* @}
*/
-
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
+ * @{
+ */
+#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
+#define RCC_LPTIM1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+
+#define IS_RCC_LPTIM1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
+ ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+/* Legacy Defines */
+#define IS_RCC_LPTIM1_SOURCE IS_RCC_LPTIM1_CLOCKSOURCE
+
+#if defined(STM32F410xx)
+/**
+ * @}
+ */
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
+ * @{
+ */
+#define RCC_I2SAPBCLKSOURCE_PLLR ((uint32_t)0x00000000)
+#define RCC_I2SAPBCLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR) || ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT) || \
+ ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup RCC_I2S_Clock_Source
+ * @{
+ */
+#define RCC_I2SCLKSource_PLLI2S ((uint32_t)0x00)
+#define RCC_I2SCLKSource_Ext ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SCLKSource_PLL ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_I2S1SRC_0 | RCC_DCKCFGR_I2S1SRC_1)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSource_PLLI2S) || ((SOURCE) == RCC_I2SCLKSource_Ext) || \
+ ((SOURCE) == RCC_I2SCLKSource_PLL) || ((SOURCE) == RCC_I2SCLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_I2S_APBBus
+ * @{
+ */
+#define RCC_I2SBus_APB1 ((uint8_t)0x00)
+#define RCC_I2SBus_APB2 ((uint8_t)0x01)
+#define IS_RCC_I2S_APBx(BUS) (((BUS) == RCC_I2SBus_APB1) || ((BUS) == RCC_I2SBus_APB2))
+/**
+ * @}
+ */
+#if defined(STM32F446xx)
+/** @defgroup RCC_SAI_Clock_Source
+ * @{
+ */
+#define RCC_SAICLKSource_PLLSAI ((uint32_t)0x00)
+#define RCC_SAICLKSource_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAICLKSource_PLL ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAICLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1SRC_0 | RCC_DCKCFGR_SAI1SRC_1)
+
+#define IS_RCC_SAICLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAICLKSource_PLLSAI) || ((SOURCE) == RCC_SAICLKSource_PLLI2S) || \
+ ((SOURCE) == RCC_SAICLKSource_PLL) || ((SOURCE) == RCC_SAICLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_Instance
+ * @{
+ */
+#define RCC_SAIInstance_SAI1 ((uint8_t)0x00)
+#define RCC_SAIInstance_SAI2 ((uint8_t)0x01)
+#define IS_RCC_SAI_INSTANCE(BUS) (((BUS) == RCC_SAIInstance_SAI1) || ((BUS) == RCC_SAIInstance_SAI2))
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+
+/** @defgroup RCC_SAI_BlockA_Clock_Source
+ * @{
+ */
+#define RCC_SAIACLKSource_PLLI2S_R ((uint32_t)0x00000000)
+#define RCC_SAIACLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
+#define RCC_SAIACLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
+#define RCC_SAIACLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
+
+#define IS_RCC_SAIACLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIACLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIACLKSource_I2SCKIN) || \
+ ((SOURCE) == RCC_SAIACLKSource_PLLR) || ((SOURCE) == RCC_SAIACLKSource_HSI_HSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_SAI_BlockB_Clock_Source
+ * @{
+ */
+#define RCC_SAIBCLKSource_PLLI2S_R ((uint32_t)0x00000000)
+#define RCC_SAIBCLKSource_I2SCKIN ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
+#define RCC_SAIBCLKSource_PLLR ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
+#define RCC_SAIBCLKSource_HSI_HSE ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
+
+#define IS_RCC_SAIBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SAIBCLKSource_PLLI2S_R) || ((SOURCE) == RCC_SAIBCLKSource_I2SCKIN) || \
+ ((SOURCE) == RCC_SAIBCLKSource_PLLR) || ((SOURCE) == RCC_SAIBCLKSource_HSI_HSE))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
/** @defgroup RCC_I2S_Clock_Source
* @{
*/
@@ -312,6 +465,7 @@ typedef struct
/**
* @}
*/
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
/** @defgroup RCC_TIM_PRescaler_Selection
* @{
@@ -323,7 +477,151 @@ typedef struct
/**
* @}
*/
-
+
+#if defined(STM32F469_479xx)
+/** @defgroup RCC_DSI_Clock_Source_Selection
+ * @{
+ */
+#define RCC_DSICLKSource_PHY ((uint8_t)0x00)
+#define RCC_DSICLKSource_PLLR ((uint8_t)0x01)
+#define IS_RCC_DSI_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_DSICLKSource_PHY) || \
+ ((CLKSOURCE) == RCC_DSICLKSource_PLLR))
+/**
+ * @}
+ */
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/** @defgroup RCC_SDIO_Clock_Source_Selection
+ * @{
+ */
+#define RCC_SDIOCLKSource_48MHZ ((uint8_t)0x00)
+#define RCC_SDIOCLKSource_SYSCLK ((uint8_t)0x01)
+#define IS_RCC_SDIO_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SDIOCLKSource_48MHZ) || \
+ ((CLKSOURCE) == RCC_SDIOCLKSource_SYSCLK))
+/**
+ * @}
+ */
+
+
+/** @defgroup RCC_48MHZ_Clock_Source_Selection
+ * @{
+ */
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_48MHZCLKSource_PLL ((uint8_t)0x00)
+#define RCC_48MHZCLKSource_PLLSAI ((uint8_t)0x01)
+#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_48MHZCLKSource_PLL) || \
+ ((CLKSOURCE) == RCC_48MHZCLKSource_PLLSAI))
+#endif /* STM32F446xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_CK48CLKSOURCE_PLLQ ((uint8_t)0x00)
+#define RCC_CK48CLKSOURCE_PLLI2SQ ((uint8_t)0x01) /* Only for STM32F412xG and STM32F413_423xx Devices */
+#define IS_RCC_48MHZ_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLQ) || \
+ ((CLKSOURCE) == RCC_CK48CLKSOURCE_PLLI2SQ))
+#endif /* STM32F412xG || STM32F413_423xx */
+/**
+ * @}
+ */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCC_SPDIFRX_Clock_Source_Selection
+ * @{
+ */
+#define RCC_SPDIFRXCLKSource_PLLR ((uint8_t)0x00)
+#define RCC_SPDIFRXCLKSource_PLLI2SP ((uint8_t)0x01)
+#define IS_RCC_SPDIFRX_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLR) || \
+ ((CLKSOURCE) == RCC_SPDIFRXCLKSource_PLLI2SP))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_CEC_Clock_Source_Selection
+ * @{
+ */
+#define RCC_CECCLKSource_HSIDiv488 ((uint8_t)0x00)
+#define RCC_CECCLKSource_LSE ((uint8_t)0x01)
+#define IS_RCC_CEC_CLOCKSOURCE(CLKSOURCE) (((CLKSOURCE) == RCC_CECCLKSource_HSIDiv488) || \
+ ((CLKSOURCE) == RCC_CECCLKSource_LSE))
+/**
+ * @}
+ */
+
+/** @defgroup RCC_AHB1_ClockGating
+ * @{
+ */
+#define RCC_AHB1ClockGating_APB1Bridge ((uint32_t)0x00000001)
+#define RCC_AHB1ClockGating_APB2Bridge ((uint32_t)0x00000002)
+#define RCC_AHB1ClockGating_CM4DBG ((uint32_t)0x00000004)
+#define RCC_AHB1ClockGating_SPARE ((uint32_t)0x00000008)
+#define RCC_AHB1ClockGating_SRAM ((uint32_t)0x00000010)
+#define RCC_AHB1ClockGating_FLITF ((uint32_t)0x00000020)
+#define RCC_AHB1ClockGating_RCC ((uint32_t)0x00000040)
+
+#define IS_RCC_AHB1_CLOCKGATING(PERIPH) ((((PERIPH) & 0xFFFFFF80) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+#endif /* STM32F446xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/** @defgroup RCC_FMPI2C1_Clock_Source
+ * @{
+ */
+#define RCC_FMPI2C1CLKSource_APB1 ((uint32_t)0x00)
+#define RCC_FMPI2C1CLKSource_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSource_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+
+#define IS_RCC_FMPI2C1_CLOCKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSource_APB1) || ((SOURCE) == RCC_FMPI2C1CLKSource_SYSCLK) || \
+ ((SOURCE) == RCC_FMPI2C1CLKSource_HSI))
+/**
+ * @}
+ */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/** @defgroup RCC_DFSDM_Clock_Source
+ * @{
+ */
+#define RCC_DFSDMCLKSource_APB ((uint8_t)0x00)
+#define RCC_DFSDMCLKSource_SYS ((uint8_t)0x01)
+#define IS_RCC_DFSDMCLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDMCLKSource_APB) || ((SOURCE) == RCC_DFSDMCLKSource_SYS))
+
+/* Legacy Defines */
+#define RCC_DFSDM1CLKSource_APB RCC_DFSDMCLKSource_APB
+#define RCC_DFSDM1CLKSource_SYS RCC_DFSDMCLKSource_SYS
+#define IS_RCC_DFSDM1CLK_SOURCE IS_RCC_DFSDMCLK_SOURCE
+/**
+ * @}
+ */
+
+/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+#define IS_RCC_DFSDM1ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2))
+
+/* Legacy Defines */
+#define IS_RCC_DFSDMACLK_SOURCE IS_RCC_DFSDM1ACLK_SOURCE
+/**
+ * @}
+ */
+
+#if defined(STM32F413_423xx)
+/** @defgroup RCC_DFSDM_Audio_Clock_Source RCC DFSDM Audio Clock Source
+ * @{
+ */
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 ((uint32_t)0x00000000)
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
+#define IS_RCC_DFSDM2ACLK_SOURCE(SOURCE) (((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1) || ((SOURCE) == RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2))
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+
/** @defgroup RCC_AHB1_Peripherals
* @{
*/
@@ -354,10 +652,12 @@ typedef struct
#define RCC_AHB1Periph_ETH_MAC_PTP ((uint32_t)0x10000000)
#define RCC_AHB1Periph_OTG_HS ((uint32_t)0x20000000)
#define RCC_AHB1Periph_OTG_HS_ULPI ((uint32_t)0x40000000)
-
-#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x810BE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD1FE800) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81106800) == 0x00) && ((PERIPH) != 0x00))
+#if defined(STM32F410xx)
+#define RCC_AHB1Periph_RNG ((uint32_t)0x80000000)
+#endif /* STM32F410xx */
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x010BE800) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0x51FE800) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x01106800) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
@@ -369,7 +669,9 @@ typedef struct
#define RCC_AHB2Periph_DCMI ((uint32_t)0x00000001)
#define RCC_AHB2Periph_CRYP ((uint32_t)0x00000010)
#define RCC_AHB2Periph_HASH ((uint32_t)0x00000020)
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
#define RCC_AHB2Periph_RNG ((uint32_t)0x00000040)
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
#define RCC_AHB2Periph_OTG_FS ((uint32_t)0x00000080)
#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
/**
@@ -379,15 +681,28 @@ typedef struct
/** @defgroup RCC_AHB3_Peripherals
* @{
*/
-#if defined (STM32F40_41xxx)
+#if defined(STM32F40_41xxx)
#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
#endif /* STM32F40_41xxx */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
-#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx)
+#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
#endif /* STM32F427_437xx || STM32F429_439xx */
-#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_AHB3Periph_FMC ((uint32_t)0x00000001)
+#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_AHB3Periph_FSMC ((uint32_t)0x00000001)
+#define RCC_AHB3Periph_QSPI ((uint32_t)0x00000002)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFC) == 0x00) && ((PERIPH) != 0x00))
+#endif /* STM32F412xG || STM32F413_423xx */
+
/**
* @}
*/
@@ -404,9 +719,15 @@ typedef struct
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+#define RCC_APB1Periph_LPTIM1 ((uint32_t)0x00000200)
+#endif /* STM32F410xx || STM32F413_423xx */
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
+#if defined(STM32F446xx)
+#define RCC_APB1Periph_SPDIFRX ((uint32_t)0x00010000)
+#endif /* STM32F446xx */
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
@@ -414,13 +735,22 @@ typedef struct
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_I2C3 ((uint32_t)0x00800000)
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+#define RCC_APB1Periph_FMPI2C1 ((uint32_t)0x01000000)
+#endif /* STM32F410xx || STM32F446xx || STM32F413_423xx*/
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
+#if defined(STM32F413_423xx)
+#define RCC_APB1Periph_CAN3 ((uint32_t)0x08000000)
+#endif /* STM32F413_423xx */
+#if defined(STM32F446xx)
+#define RCC_APB1Periph_CEC ((uint32_t)0x08000000)
+#endif /* STM32F446xx */
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
#define RCC_APB1Periph_UART7 ((uint32_t)0x40000000)
#define RCC_APB1Periph_UART8 ((uint32_t)0x80000000)
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x09013600) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x00003600) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
@@ -440,21 +770,39 @@ typedef struct
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_SPI4 ((uint32_t)0x00002000)
#define RCC_APB2Periph_SYSCFG ((uint32_t)0x00004000)
+#define RCC_APB2Periph_EXTIT ((uint32_t)0x00008000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00010000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00020000)
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00040000)
#define RCC_APB2Periph_SPI5 ((uint32_t)0x00100000)
#define RCC_APB2Periph_SPI6 ((uint32_t)0x00200000)
#define RCC_APB2Periph_SAI1 ((uint32_t)0x00400000)
+#if defined(STM32F446xx) || defined(STM32F469_479xx)
+#define RCC_APB2Periph_SAI2 ((uint32_t)0x00800000)
+#endif /* STM32F446xx || STM32F469_479xx */
#define RCC_APB2Periph_LTDC ((uint32_t)0x04000000)
+#if defined(STM32F469_479xx)
+#define RCC_APB2Periph_DSI ((uint32_t)0x08000000)
+#endif /* STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+#define RCC_APB2Periph_DFSDM1 ((uint32_t)0x01000000)
+#endif /* STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+#define RCC_APB2Periph_DFSDM2 ((uint32_t)0x02000000)
+#define RCC_APB2Periph_UART9 ((uint32_t)0x02000040)
+#define RCC_APB2Periph_UART10 ((uint32_t)0x00000080)
+#endif /* STM32F413_423xx */
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFB8880CC) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFB8886CC) == 0x00) && ((PERIPH) != 0x00))
+/* Legacy Defines */
+#define RCC_APB2Periph_DFSDM RCC_APB2Periph_DFSDM1
+
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF008000C) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xF208860C) == 0x00) && ((PERIPH) != 0x00))
/**
* @}
*/
-
+
/** @defgroup RCC_MCO1_Clock_Source_Prescaler
* @{
*/
@@ -538,7 +886,7 @@ typedef struct
/* Exported functions --------------------------------------------------------*/
/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
+void RCC_DeInit(void);
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
void RCC_HSEConfig(uint8_t RCC_HSE);
@@ -547,21 +895,43 @@ void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+
void RCC_PLLCmd(FunctionalState NewState);
-#if defined (STM32F40_41xxx) || defined (STM32F401xx)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
-#elif defined (STM32F411xE)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
-#elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
-void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
-#else
-#endif /* STM32F40_41xxx || STM32F401xx */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
void RCC_PLLI2SCmd(FunctionalState NewState);
-void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+
+#if defined(STM32F40_41xxx) || defined(STM32F401xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
+#endif /* STM32F40_41xxx || STM32F401xx */
+#if defined(STM32F411xE)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM);
+#endif /* STM32F411xE */
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR);
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR);
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
void RCC_PLLSAICmd(FunctionalState NewState);
+#if defined(STM32F469_479xx)
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+#endif /* STM32F469_479xx */
+#if defined(STM32F446xx)
+void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ);
+#endif /* STM32F446xx */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
@@ -578,11 +948,35 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
-void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
-void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
-void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource);
+#if defined(STM32F446xx)
+void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource);
+#endif /* STM32F446xx */
+#if defined(STM32F413_423xx)
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource);
void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ);
+void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ);
+
+#if defined(STM32F413_423xx)
+void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR);
+void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR);
+#endif /* STM32F413_423xx */
+
void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR);
void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler);
@@ -604,8 +998,50 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalStat
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_LSEModeConfig(uint8_t Mode);
+/* Features available only for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices */
+void RCC_LSEModeConfig(uint8_t RCC_Mode);
+/* Features available only for STM32F469_479xx devices */
+#if defined(STM32F469_479xx)
+void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F469_479xx */
+
+/* Features available only for STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices */
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource);
+void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+/* Features available only for STM32F446xx devices */
+#if defined(STM32F446xx)
+void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState);
+void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource);
+void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource);
+#endif /* STM32F446xx */
+
+/* Features available only for STM32F410xx/STM32F412xG/STM32F446xx devices */
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+/* Features available only for STM32F410xx devices */
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource);
+#if defined(STM32F410xx)
+void RCC_MCO1Cmd(FunctionalState NewState);
+void RCC_MCO2Cmd(FunctionalState NewState);
+#endif /* STM32F410xx */
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+void RCC_DFSDMCLKConfig(uint32_t RCC_DFSDMCLKSource);
+void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource);
+#if defined(STM32F413_423xx)
+void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource);
+#endif /* STM32F413_423xx */
+/* Legacy Defines */
+#define RCC_DFSDM1CLKConfig RCC_DFSDMCLKConfig
+#endif /* STM32F412xG || STM32F413_423xx */
/* Interrupts and flags management functions **********************************/
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
similarity index 89%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
index 58b468d9c..aa8e26dad 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_rng.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the Random
* Number Generator(RNG) firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -44,7 +44,7 @@
/** @addtogroup RNG
* @{
*/
-
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -102,6 +102,7 @@ FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
void RNG_ClearFlag(uint8_t RNG_FLAG);
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
void RNG_ClearITPendingBit(uint8_t RNG_IT);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
#ifdef __cplusplus
}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
index de3c06be8..ec6f6fd41 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_rtc.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the RTC firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -449,7 +449,7 @@ typedef struct
*/
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
+#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibration
period is 16s, else 2exp19 RTCCLK seconds */
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
period is 8s, else 2exp18 RTCCLK seconds */
@@ -527,7 +527,7 @@ typedef struct
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
+ consecutive samples at the active level. */
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
((FILTER) == RTC_TamperFilter_2Sample) || \
((FILTER) == RTC_TamperFilter_4Sample) || \
@@ -591,8 +591,9 @@ typedef struct
/** @defgroup RTC_Tamper_Pins_Definitions
* @{
*/
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
-#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
+#define RTC_Tamper_1 RTC_TAFCR_TAMP1E
+#define RTC_Tamper_2 RTC_TAFCR_TAMP2E
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1) || ((TAMPER) == RTC_Tamper_2))
/**
* @}
@@ -601,10 +602,13 @@ typedef struct
/** @defgroup RTC_Tamper_Pin_Selection
* @{
*/
-#define RTC_TamperPin_PC13 ((uint32_t)0x00000000)
-#define RTC_TamperPin_PI8 ((uint32_t)0x00010000)
-#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
- ((PIN) == RTC_TamperPin_PI8))
+#define RTC_TamperPin_Default ((uint32_t)0x00000000)
+#define RTC_TamperPin_Pos1 ((uint32_t)0x00010000)
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_Default) || \
+ ((PIN) == RTC_TamperPin_Pos1))
+/* Legacy Defines */
+#define RTC_TamperPin_PC13 RTC_TamperPin_Default
+#define RTC_TamperPin_PI8 RTC_TamperPin_Pos1
/**
* @}
*/
@@ -616,6 +620,7 @@ typedef struct
#define RTC_TimeStampPin_PI8 ((uint32_t)0x00020000)
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
((PIN) == RTC_TimeStampPin_PI8))
+
/**
* @}
*/
@@ -716,6 +721,7 @@ typedef struct
*/
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
+#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
@@ -734,7 +740,7 @@ typedef struct
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
+ ((FLAG) == RTC_FLAG_TAMP2F) ||((FLAG) == RTC_FLAG_SHPF))
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
/**
* @}
@@ -749,12 +755,13 @@ typedef struct
#define RTC_IT_ALRA ((uint32_t)0x00001000)
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
+#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1))
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
+ ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF90FFF) == (uint32_t)RESET))
/**
* @}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h
similarity index 89%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h
index a7805d570..5e7fbe371 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sai.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_sai.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the SAI
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -44,7 +44,9 @@
/** @addtogroup SAI
* @{
*/
-
+#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \
+ defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \
+ defined (STM32F413_423xx)
/* Exported types ------------------------------------------------------------*/
/**
@@ -72,6 +74,12 @@ typedef struct
uint32_t SAI_Synchro; /*!< Specifies SAI Block synchronization
This parameter can be a value of @ref SAI_Block_Synchronization */
+
+ uint32_t SAI_SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
+ for BlockA and BlockB
+ This parameter can be a value of @ref SAI_Block_SyncExt
+ @note: If both audio blocks of same SAI are used, this parameter has
+ to be set to the same value for each audio block */
uint32_t SAI_OUTDRIV; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@@ -153,11 +161,22 @@ typedef struct
* @{
*/
+#if defined(STM32F446xx)
+#define IS_SAI_PERIPH(PERIPH) (((PERIPH) == SAI1) || ((PERIPH) == SAI2))
+
+#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
+ ((PERIPH) == SAI1_Block_B) || \
+ ((PERIPH) == SAI2_Block_A) || \
+ ((PERIPH) == SAI2_Block_B))
+#endif /* STM32F446xx */
+
+#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE) || defined(STM32F413_423xx) || defined (STM32F469_479xx)
+
#define IS_SAI_PERIPH(PERIPH) ((PERIPH) == SAI1)
#define IS_SAI_BLOCK_PERIPH(PERIPH) (((PERIPH) == SAI1_Block_A) || \
((PERIPH) == SAI1_Block_B))
-
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F413_423xx || STM32F469_479xx */
/** @defgroup SAI_Block_Mode
* @{
@@ -238,12 +257,27 @@ typedef struct
#define SAI_Asynchronous ((uint32_t)0x00000000)
#define SAI_Synchronous ((uint32_t)SAI_xCR1_SYNCEN_0)
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
- ((SYNCHRO) == SAI_Asynchronous))
+#define SAI_Synchronous_Ext ((uint32_t)SAI_xCR1_SYNCEN_1)
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_Synchronous) || \
+ ((SYNCHRO) == SAI_Asynchronous) || \
+ ((SYNCHRO) == SAI_Synchronous_Ext))
/**
* @}
*/
+/** @defgroup SAI_Block_SyncExt SAI External synchronisation
+ * @{
+ */
+#define SAI_SyncExt_Disable ((uint32_t)0x00000000)
+#define SAI_SyncExt_OutBlockA_Enable ((uint32_t)SAI_GCR_SYNCOUT_0)
+#define SAI_SyncExt_OutBlockB_Enable ((uint32_t)SAI_GCR_SYNCOUT_1)
+#define IS_SAI_BLOCK_SYNCEXT(SYNCHRO) (((SYNCHRO) == SAI_SyncExt_Disable) || \
+ ((SYNCHRO) == SAI_SyncExt_OutBlockA_Enable)|| \
+ ((SYNCHRO) == SAI_SyncExt_OutBlockB_Enable))
+/**
+ * @}
+ */
+
/** @defgroup SAI_Block_Output_Drive
* @{
*/
@@ -577,7 +611,10 @@ void SAI_MuteModeCmd(SAI_Block_TypeDef* SAI_Block_x, FunctionalState NewState);
void SAI_MuteValueConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteValue);
void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_MuteCounter);
void SAI_FlushFIFO(SAI_Block_TypeDef* SAI_Block_x);
-
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx)
+void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */
/* Data transfers functions ***************************************************/
void SAI_SendData(SAI_Block_TypeDef* SAI_Block_x, uint32_t Data);
uint32_t SAI_ReceiveData(SAI_Block_TypeDef* SAI_Block_x);
@@ -594,18 +631,19 @@ void SAI_ClearITPendingBit(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_IT);
FunctionalState SAI_GetCmdStatus(SAI_Block_TypeDef* SAI_Block_x);
uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
#ifdef __cplusplus
}
#endif
#endif /*__STM32F4xx_SAI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
index 485362ed1..dc6c2e9ef 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_sdio.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the SDIO firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
index fda14d687..a1436f658 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_spi.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the SPI
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
similarity index 59%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
index efbf5b2bd..dbbe87b3a 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_syscfg.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the SYSCFG firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -47,10 +47,116 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
-
/** @defgroup SYSCFG_Exported_Constants
* @{
*/
+#if defined(STM32F413_423xx)
+/** @defgroup BITSTREAM_CLOCK Bit Stream clock source selection
+ * @{
+ */
+#define BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
+#define BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
+/**
+ * @}
+ */
+
+/** @defgroup MCHDLY_CLOCK MCHDLY Clock enable
+ * @{
+ */
+#define MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN
+#define MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection
+ * @{
+ */
+#define DFSDM2_CKIN_PAD (uint32_t)0x00000000
+#define DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
+#define DFSDM1_CKIN_PAD (uint32_t)0x00000000
+#define DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection
+ * @{
+ */
+#define DFSDM2_CKOUT_DFSDM2 (uint32_t)0x00000000
+#define DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
+#define DFSDM1_CKOUT_DFSDM1 (uint32_t)0x00000000U
+#define DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0
+ * @{
+ */
+#define DATAIN0_DFSDM2_PAD (uint32_t)0x00000000
+#define DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL
+#define DATAIN0_DFSDM1_PAD (uint32_t)0x00000000
+#define DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2
+ * @{
+ */
+#define DATAIN2_DFSDM2_PAD (uint32_t)0x00000000
+#define DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL
+#define DATAIN2_DFSDM1_PAD (uint32_t)0x00000000
+#define DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4
+ * @{
+ */
+#define DATAIN4_DFSDM2_PAD (uint32_t)0x00000000
+#define DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6
+ * @{
+ */
+#define DATAIN6_DFSDM2_PAD (uint32_t)0x00000000
+#define DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN
+ * @{
+ */
+#define DFSDM1_CLKIN0_TIM4OC2 (uint32_t)0x00000000
+#define DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
+#define DFSDM1_CLKIN1_TIM4OC1 (uint32_t)0x00000000
+#define DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
+/**
+ * @}
+ */
+
+/** @defgroup DFSDM_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN
+ * @{
+ */
+#define DFSDM2_CLKIN0_TIM3OC4 (uint32_t)0x00000000
+#define DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
+#define DFSDM2_CLKIN1_TIM3OC3 (uint32_t)0x00000000
+#define DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
+#define DFSDM2_CLKIN2_TIM3OC2 (uint32_t)0x00000000
+#define DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
+#define DFSDM2_CLKIN3_TIM3OC1 (uint32_t)0x00000000
+#define DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
+/**
+ * @}
+ */
+#endif /* STM32F413_423xx */
/** @defgroup SYSCFG_EXTI_Port_Sources
* @{
@@ -132,26 +238,30 @@
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
#define SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
-#if defined (STM32F40_41xxx)
+#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define SYSCFG_MemoryRemap_FMC ((uint8_t)0x02)
#endif /* STM32F427_437xx || STM32F429_439xx */
-#if defined (STM32F40_41xxx)
+#if defined (STM32F446xx) || defined (STM32F469_479xx)
+#define SYSCFG_MemoryRemap_ExtMEM ((uint8_t)0x02)
+#endif /* STM32F446xx || STM32F469_479xx */
+
+#if defined (STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FSMC))
-#endif /* STM32F40_41xxx */
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx */
-#if defined (STM32F401xx) || defined (STM32F411xE)
+#if defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
((REMAP) == SYSCFG_MemoryRemap_SRAM))
-#endif /* STM32F401xx || STM32F411xE */
+#endif /* STM32F401xx || STM32F410xx || STM32F411xE */
#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
@@ -160,7 +270,22 @@
((REMAP) == SYSCFG_MemoryRemap_SDRAM) || \
((REMAP) == SYSCFG_MemoryRemap_FMC))
#endif /* STM32F427_437xx || STM32F429_439xx */
-
+
+#if defined (STM32F446xx) || defined (STM32F469_479xx)
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_ExtMEM) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+ ((REMAP) == SYSCFG_MemoryRemap_SDRAM))
+#endif /* STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVDL
+#define SYSCFG_Break_HardFault SYSCFG_CFGR2_CLL
+
+#define IS_SYSCFG_LOCK_CONFIG(BREAK) (((BREAK) == SYSCFG_Break_PVD) || \
+ ((BREAK) == SYSCFG_Break_HardFault))
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
/**
* @}
*/
@@ -185,14 +310,29 @@
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
-void SYSCFG_DeInit(void);
+void SYSCFG_DeInit(void);
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
void SYSCFG_MemorySwappingBank(FunctionalState NewState);
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface);
void SYSCFG_CompensationCellCmd(FunctionalState NewState);
FlagStatus SYSCFG_GetCompensationCellStatus(void);
-
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+#if defined(STM32F413_423xx)
+void DFSDM_BitstreamClock_SourceSelection(uint32_t source);
+void DFSDM_DisableDelayClock(uint32_t MCHDLY);
+void DFSDM_EnableDelayClock(uint32_t MCHDLY);
+void DFSDM_ClockIn_SourceSelection(uint32_t source);
+void DFSDM_ClockOut_SourceSelection(uint32_t source);
+void DFSDM_DataIn0_SourceSelection(uint32_t source);
+void DFSDM_DataIn2_SourceSelection(uint32_t source);
+void DFSDM_DataIn4_SourceSelection(uint32_t source);
+void DFSDM_DataIn6_SourceSelection(uint32_t source);
+void DFSDM1_BitStreamClk_Config(uint32_t source);
+void DFSDM2_BitStreamClk_Config(uint32_t source);
+#endif /* STM32F413_423xx */
#ifdef __cplusplus
}
#endif
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
index 7254cb334..a6fe07d23 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_tim.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the TIM firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
index 2dbdede9a..ca341a82b 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_usart.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the USART
* firmware library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -35,7 +35,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
-#include "../../CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h"
+#include "stm32f4xx.h"
/** @addtogroup STM32F4xx_StdPeriph_Driver
* @{
@@ -72,7 +72,7 @@ typedef struct
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
- uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+ uint16_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
@@ -114,7 +114,9 @@ typedef struct
((PERIPH) == UART5) || \
((PERIPH) == USART6) || \
((PERIPH) == UART7) || \
- ((PERIPH) == UART8))
+ ((PERIPH) == UART8) || \
+ ((PERIPH) == UART9) || \
+ ((PERIPH) == UART10))
#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
((PERIPH) == USART2) || \
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
similarity index 96%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
index acd7850e4..6a7cf1b13 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
@@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f4xx_wwdg.h
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file contains all the functions prototypes for the WWDG firmware
* library.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
index dc7d808c9..7f905418e 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file misc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides all the miscellaneous firmware functions (add-on
* to CMSIS functions).
*
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
index 50d0248a4..b292105fc 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_adc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and Configuration (in addition to ADC multi mode
@@ -85,7 +85,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -652,7 +652,7 @@ void ADC_VBATCmd(FunctionalState NewState)
(++) Activate the continuous Mode (*)
(++) Activate the Discontinuous Mode
-@@- Please Note that the following features for regular channels
- are configurated using the ADC_Init() function :
+ are configured using the ADC_Init() function :
(+@@) scan mode activation
(+@@) continuous mode activation (**)
(+@@) External trigger source
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
similarity index 87%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
index 5a82b4ab1..e11936d24 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_can.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Controller area network (CAN) peripheral:
* + Initialization and Configuration
@@ -31,7 +31,7 @@
(++) Configure these CAN pins in alternate function mode by calling
the function GPIO_Init();
- (#) Initialise and configure the CAN using CAN_Init() and
+ (#) Initialize and configure the CAN using CAN_Init() and
CAN_FilterInit() functions.
(#) Transmit the desired CAN frame using CAN_Transmit() function.
@@ -42,7 +42,7 @@
(#) Cancel the transmission of a CAN frame using CAN_CancelTransmit()
function.
- (#) Receive a CAN frame using CAN_Recieve() function.
+ (#) Receive a CAN frame using CAN_Receive() function.
(#) Release the receive FIFOs using CAN_FIFORelease() function.
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -160,7 +160,8 @@ static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
/**
* @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None.
*/
void CAN_DeInit(CAN_TypeDef* CANx)
@@ -175,21 +176,40 @@ void CAN_DeInit(CAN_TypeDef* CANx)
/* Release CAN1 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
}
- else
+#if defined(STM32F413_423xx)
+ else if(CANx == CAN2)
{
/* Enable CAN2 reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
/* Release CAN2 from reset state */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
}
+
+ else /* CAN3 available only for STM32F413_423xx */
+ {
+ /* Enable CAN3 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, ENABLE);
+ /* Release CAN3 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN3, DISABLE);
+ }
+#else
+ else
+ {
+ /* Enable CAN2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+ /* Release CAN2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+ }
+#endif /* STM32F413_423xx */
}
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
* the configuration information for the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval Constant indicates initialization succeed which will be
* CAN_InitStatus_Failed or CAN_InitStatus_Success.
*/
@@ -323,6 +343,101 @@ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
return InitStatus;
}
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param CANx: where x can be 1 or 3 to select the CAN peripheral.
+ * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
+ * contains the configuration information.
+ * @retval None
+ */
+void CAN_FilterInit(CAN_TypeDef* CANx, CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+ uint32_t filter_number_bit_pos = 0;
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+ filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+ /* Initialisation mode for the filter */
+ CANx->FMR |= FMR_FINIT;
+
+ /* Filter Deactivation */
+ CANx->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* Filter Scale */
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+ {
+ /* 16-bit scale for the filter */
+ CANx->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+ {
+ /* 32-bit scale for the filter */
+ CANx->FS1R |= filter_number_bit_pos;
+ /* 32-bit identifier or First 32-bit identifier */
+ CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ CANx->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
+ ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+ (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+ {
+ /*Id/Mask mode for the filter*/
+ CANx->FM1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ CANx->FM1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter FIFO assignment */
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CANx->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+ }
+
+ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ CANx->FFA1R |= (uint32_t)filter_number_bit_pos;
+ }
+
+ /* Filter activation */
+ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+ {
+ CANx->FA1R |= filter_number_bit_pos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CANx->FMR &= ~FMR_FINIT;
+}
+#else
/**
* @brief Configures the CAN reception filter according to the specified
* parameters in the CAN_FilterInitStruct.
@@ -415,6 +530,7 @@ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
/* Leave the initialisation mode for the filter */
CAN1->FMR &= ~FMR_FINIT;
}
+#endif /* STM32F413_423xx */
/**
* @brief Fills each CAN_InitStruct member with its default value.
@@ -459,6 +575,29 @@ void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
CAN_InitStruct->CAN_Prescaler = 1;
}
+#if defined(STM32F413_423xx)
+/**
+ * @brief Select the start bank filter for slave CAN.
+ * @param CANx: where x can be 1 or 3 to select the CAN peripheral.
+ * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
+ * @retval None
+ */
+void CAN_SlaveStartBank(CAN_TypeDef* CANx, uint8_t CAN_BankNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+
+ /* Enter Initialisation mode for the filter */
+ CANx->FMR |= FMR_FINIT;
+
+ /* Select the start slave bank */
+ CANx->FMR &= (uint32_t)0xFFFFC0F1 ;
+ CANx->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+
+ /* Leave Initialisation mode for the filter */
+ CANx->FMR &= ~FMR_FINIT;
+}
+#else
/**
* @brief Select the start bank filter for slave CAN.
* @param CAN_BankNumber: Select the start slave bank filter from 1..27.
@@ -479,14 +618,15 @@ void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
/* Leave Initialisation mode for the filter */
CAN1->FMR &= ~FMR_FINIT;
}
-
+#endif /* STM32F413_423xx */
/**
* @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param NewState: new state of the CAN peripheral.
* This parameter can be: ENABLE (CAN reception/transmission is frozen
* during debug. Reception FIFOs can still be accessed/controlled normally)
* or DISABLE (CAN is working during debug).
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
@@ -512,11 +652,12 @@ void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
* @brief Enables or disables the CAN Time TriggerOperation communication mode.
* @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
* sent over the CAN bus.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
* When enabled, Time stamp (TIME[15:0]) value is sent in the last two
* data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
+ * in data byte 7.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
@@ -568,8 +709,9 @@ void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
/**
* @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval The number of the mailbox that is used for transmission or
* CAN_TxStatus_NoMailBox if there is no empty mailbox.
*/
@@ -640,8 +782,9 @@ uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
/**
* @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param TransmitMailbox: the number of the mailbox that is used for transmission.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
* CAN_TxStatus_Failed in an other case.
*/
@@ -695,8 +838,9 @@ uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
/**
* @brief Cancels a transmit request.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param Mailbox: Mailbox number.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
@@ -740,10 +884,11 @@ void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
/**
* @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
* @param RxMessage: pointer to a structure receive frame which contains CAN Id,
* CAN DLC, CAN data and FMI number.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
@@ -791,8 +936,9 @@ void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
/**
* @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
@@ -814,8 +960,9 @@ void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
/**
* @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval NbMessage : which is the number of pending message.
*/
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
@@ -946,7 +1093,8 @@ uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
/**
* @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
*/
uint8_t CAN_Sleep(CAN_TypeDef* CANx)
@@ -971,7 +1119,8 @@ uint8_t CAN_Sleep(CAN_TypeDef* CANx)
/**
* @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
*/
uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
@@ -1025,7 +1174,7 @@ uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
/**
* @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1 or 2 to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @retval Error code:
* - CAN_ERRORCODE_NoErr: No Error
* - CAN_ERRORCODE_StuffErr: Stuff Error
@@ -1058,7 +1207,8 @@ uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
* decremented by 1 or reset to 120 if its value was higher than 128.
* When the counter value exceeds 127, the CAN controller enters the
* error passive state.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval CAN Receive Error Counter.
*/
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
@@ -1078,7 +1228,8 @@ uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
/**
* @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval LSB of the 9-bit CAN Transmit Error Counter.
*/
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
@@ -1120,7 +1271,7 @@ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
(++) CAN_FLAG_RQCP0,
(++) CAN_FLAG_RQCP1,
(++) CAN_FLAG_RQCP2 : Request completed MailBoxes 0, 1 and 2 Flags
- Set when when the last request (transmit or abort)
+ Set when the last request (transmit or abort)
has been performed.
(+) Receive Flags
@@ -1265,7 +1416,7 @@ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
*/
/**
* @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg CAN_IT_TME: Transmit mailbox empty Interrupt
@@ -1283,6 +1434,7 @@ uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
* @arg CAN_IT_LEC: Last error code Interrupt
* @arg CAN_IT_ERR: Error Interrupt
* @param NewState: new state of the CAN interrupts.
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -1306,7 +1458,7 @@ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
}
/**
* @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to check.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
@@ -1323,7 +1475,8 @@ void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
* @arg CAN_FLAG_EWG: Error Warning Flag
* @arg CAN_FLAG_EPV: Error Passive Flag
* @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
+ * @arg CAN_FLAG_LEC: Last error code Flag
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval The new state of CAN_FLAG (SET or RESET).
*/
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
@@ -1411,7 +1564,7 @@ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
/**
* @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_FLAG: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
@@ -1423,7 +1576,8 @@ FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
* @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
* @arg CAN_FLAG_WKU: Wake up Flag
* @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
+ * @arg CAN_FLAG_LEC: Last error code Flag
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
@@ -1467,7 +1621,7 @@ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
/**
* @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_IT: specifies the CAN interrupt source to check.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty Interrupt
@@ -1484,6 +1638,7 @@ void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
* @arg CAN_IT_BOF: Bus-off Interrupt
* @arg CAN_IT_LEC: Last error code Interrupt
* @arg CAN_IT_ERR: Error Interrupt
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval The current state of CAN_IT (SET or RESET).
*/
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
@@ -1573,7 +1728,7 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
/**
* @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
+ * @param CANx: where x can be 1,2 or 3 to select the CAN peripheral.
* @param CAN_IT: specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg CAN_IT_TME: Transmit mailbox empty Interrupt
@@ -1587,7 +1742,8 @@ ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
* @arg CAN_IT_EPV: Error passive Interrupt
* @arg CAN_IT_BOF: Bus-off Interrupt
* @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
+ * @arg CAN_IT_ERR: Error Interrupt
+ * @note CAN3 peripheral is available only for STM32F413_423xx devices
* @retval None
*/
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
similarity index 96%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
index ac420eceb..de0148eaa 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_crc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides all the CRC firmware functions.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
index 548caec8c..be75b7120 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Cryptographic processor (CRYP) peripheral:
* + Initialization and Configuration functions
@@ -20,7 +20,7 @@
(#) Enable the CRYP controller clock using
RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
- (#) Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
+ (#) Initialize the CRYP using CRYP_Init(), CRYP_KeyInit() and if needed
CRYP_IVInit().
(#) Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
@@ -143,7 +143,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -590,12 +590,12 @@ ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
/**
* @brief Restores the CRYP peripheral Context.
- * @note Since teh DMA transfer is stopped in CRYP_SaveContext() function,
+ * @note Since the DMA transfer is stopped in CRYP_SaveContext() function,
* after restoring the context, you have to enable the DMA again (if the
* DMA was previously used).
* @param CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
* the repository for saved context.
- * @note The data that were saved during context saving must be rewrited into
+ * @note The data that were saved during context saving must be rewritten into
* the IN FIFO.
* @retval None
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
index af8d7d1ed..c02fef76e 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_aes.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides high level functions to encrypt and decrypt an
* input message using AES in ECB/CBC/CTR/GCM/CCM modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
@@ -34,7 +34,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -224,7 +224,7 @@ ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -427,7 +427,7 @@ ErrorStatus CRYP_AES_CBC(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -598,7 +598,7 @@ ErrorStatus CRYP_AES_CTR(uint8_t Mode, uint8_t InitVectors[16], uint8_t *Key,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -790,7 +790,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -838,7 +838,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -900,7 +900,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -967,7 +967,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1015,7 +1015,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1077,7 +1077,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1116,7 +1116,7 @@ ErrorStatus CRYP_AES_GCM(uint8_t Mode, uint8_t InitVectors[16],
* This parameter can be one of the following values:
* @arg MODE_ENCRYPT: Encryption
* @arg MODE_DECRYPT: Decryption
- * @param Nonce: the nounce used for AES algorithm. It shall be unique for each processing.
+ * @param Nonce: the nonce used for AES algorithm. It shall be unique for each processing.
* @param Key: Key used for AES algorithm.
* @param Keysize: length of the Key, must be a 128, 192 or 256.
* @param Input: pointer to the Input buffer.
@@ -1346,7 +1346,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1394,7 +1394,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1457,7 +1457,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1535,7 +1535,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1583,7 +1583,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1646,7 +1646,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
the CRYP peripheral (please check the device sales type. */
return(ERROR);
}
@@ -1667,7 +1667,7 @@ ErrorStatus CRYP_AES_CCM(uint8_t Mode,
{
}
- /* Read the Authentaication TAG (MAC) in the IN FIFO */
+ /* Read the Authentification TAG (MAC) in the IN FIFO */
temptag[0] = CRYP_DataOut();
temptag[1] = CRYP_DataOut();
temptag[2] = CRYP_DataOut();
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
similarity index 78%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
index 04d5e95a6..c32137b2f 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_cryp_des.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides high level functions to encrypt and decrypt an
* input message using DES in ECB/CBC modes.
* It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
@@ -27,7 +27,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -140,45 +140,47 @@ ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
+ the CRYP peripheral (please check the device sales type. */
+ status = ERROR;
}
- for(i=0; ((i© COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -149,44 +149,46 @@ ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input,
if(CRYP_GetCmdStatus() == DISABLE)
{
- /* The CRYP peripheral clock is not enabled or the device doesn't embedd
- the CRYP peripheral (please check the device sales type. */
- return(ERROR);
+ /* The CRYP peripheral clock is not enabled or the device doesn't embed
+ the CRYP peripheral (please check the device sales type. */
+ status = ERROR;
}
- for(i=0; ((i© COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
index 4cc691f48..4ed40dc91 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
@@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f4xx_dbgmcu.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides all the DBGMCU firmware functions.
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
index 0993dd6ac..af9c42c24 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dcmi.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the DCMI peripheral:
* + Initialization and Configuration
@@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
index 046f7950e..43f9fcad3 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Direct Memory Access controller (DMA):
* + Initialization and Configuration
@@ -29,7 +29,7 @@
data formats, Circular or Normal mode, Stream Priority level, Source and Destination
Incrementation mode, FIFO mode and its Threshold (if needed), Burst
mode for Source and/or Destination (if needed) using the DMA_Init() function.
- To avoid filling unneccessary fields, you can call DMA_StructInit() function
+ To avoid filling unnecessary fields, you can call DMA_StructInit() function
to initialize a given structure with default values (reset values), the modify
only necessary fields
(ie. Source and Destination addresses, Transfer size and Data Formats).
@@ -103,7 +103,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -692,7 +692,7 @@ uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
[..]
Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is
- stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
+ stopped) to modify on of the target Memories addresses or to check which Memory target is currently
used:
(+) void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx,
uint32_t MemoryBaseAddr, uint32_t DMA_MemoryTarget);
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c
index 6869aab8f..f38b71c21 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma2d.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_dma2d.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the DMA2D controller (DMA2D) peripheral:
* + Initialization and configuration
@@ -37,7 +37,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -252,7 +252,7 @@ void DMA2D_StartTransfer(void)
}
/**
- * @brief Aboart the DMA2D transfer.
+ * @brief Abort the DMA2D transfer.
* @param
* @retval None
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
index 433a8bf3a..2ab0201a3 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
@@ -2,10 +2,10 @@
******************************************************************************
* @file stm32f4xx_exti.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
+ * functionalities of the EXTI peripheral:
* + Initialization and Configuration
* + Interrupts and flags management
*
@@ -25,6 +25,7 @@
(#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
(#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
(#) EXTI line 22 is connected to the RTC Wakeup event
+ (#) EXTI line 23 is connected to the LPTIM Wakeup event
##### How to use this driver #####
===============================================================================
@@ -46,7 +47,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
index c077b6bca..17f897715 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the FLASH peripheral:
* + FLASH Interface configuration
@@ -51,7 +51,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -179,7 +179,7 @@
+-------------------------------------------------------------------------------------+
[..]
- For STM32F411xE devices
+ For STM32F410xx/STM32F411xE devices
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
@@ -224,7 +224,7 @@
(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 60MHz.
(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
[..]
- On STM32F411xE devices:
+ On STM32F410xx/STM32F411xE devices:
(++) when VOS[1:0] = '0x01' Scale 3 mode, the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10' Scale 2 mode, the maximum value of fHCLK is 84MHz.
(++) when VOS[1:0] = '0x11' Scale 1 mode, the maximum value of fHCLK is 100MHz.
@@ -266,8 +266,8 @@
* @arg FLASH_Latency_14: FLASH Fourteen Latency cycles
* @arg FLASH_Latency_15: FLASH Fifteen Latency cycles
*
- * @note For STM32F405xx/407xx, STM32F415xx/417xx and STM32F401xx/411xE devices this parameter
- * can be a value between FLASH_Latency_0 and FLASH_Latency_7.
+ * @note For STM32F405xx/407xx, STM32F415xx/417xx, STM32F401xx/411xE/STM32F412xG and STM32F413_423xx devices
+ * this parameter can be a value between FLASH_Latency_0 and FLASH_Latency_7.
*
* @note For STM32F42xxx/43xxx devices this parameter can be a value between
* FLASH_Latency_0 and FLASH_Latency_15.
@@ -435,7 +435,7 @@ void FLASH_Lock(void)
/**
* @brief Erases a specified FLASH Sector.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param FLASH_Sector: The Sector number to be erased.
@@ -449,9 +449,15 @@ void FLASH_Lock(void)
* For STM32F401xx devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_5.
*
- * For STM32F411xE devices this parameter can be a value between
+ * For STM32F411xE and STM32F412xG devices this parameter can be a value between
* FLASH_Sector_0 and FLASH_Sector_7.
*
+ * For STM32F410xx devices this parameter can be a value between
+ * FLASH_Sector_0 and FLASH_Sector_4.
+ *
+ * For STM32F413_423xx devices this parameter can be a value between
+ * FLASH_Sector_0 and FLASH_Sector_15.
+ *
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V,
@@ -517,7 +523,7 @@ FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
/**
* @brief Erases all FLASH Sectors.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param VoltageRange: The device voltage range which defines the erase parallelism.
@@ -562,7 +568,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
if(status == FLASH_COMPLETE)
{
/* if the previous operation is completed, proceed to erase all sectors */
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= (FLASH_CR_MER1 | FLASH_CR_MER2);
@@ -573,9 +579,9 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= ~(FLASH_CR_MER1 | FLASH_CR_MER2);
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
+#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
FLASH->CR |= FLASH_CR_MER;
@@ -586,7 +592,7 @@ FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_CR_MER);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
+#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx || STM32F446xx */
}
/* Return the Erase Status */
@@ -731,7 +737,7 @@ FLASH_Status FLASH_EraseAllBank2Sectors(uint8_t VoltageRange)
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V and an External Vpp is present.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
@@ -773,7 +779,7 @@ FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
*
* @note This function must be used when the device voltage range is from 2.7V to 3.6V.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
@@ -815,7 +821,7 @@ FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
* @brief Programs a half word (16-bit) at a specified address.
* @note This function must be used when the device voltage range is from 2.1V to 3.6V.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
@@ -857,7 +863,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
* @brief Programs a byte (8-bit) at a specified address.
* @note This function can be used within all the device supply voltage ranges.
*
- * @note If an erase and a program operations are requested simustaneously,
+ * @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
@@ -1113,7 +1119,8 @@ void FLASH_OB_PCROPSelectionConfig(uint8_t OB_PcROP)
* @brief Enables or disables the read/write protection (PCROP) of the desired
* sectors, for the first 1 MB of the Flash.
*
- * @note This function can be used only for STM32F42xxx/43xxx and STM32F401xx/411xE devices.
+ * @note This function can be used only for STM32F42xxx/43xxx , STM32F401xx/411xE
+ * STM32F412xG and STM32F413_423xx devices.
*
* @param OB_PCROP: specifies the sector(s) to be read/write protected or unprotected.
* This parameter can be one of the following values:
@@ -1245,15 +1252,15 @@ void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
if(status == FLASH_COMPLETE)
{
-#if defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
-#endif /* STM32F427_437xx || STM32F429_439xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
-#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
+#if defined(STM32F40_41xxx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F446xx)
/* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F);
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
+#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx */
/* Update User Option Byte */
*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp)));
@@ -1547,7 +1554,7 @@ FLASH_Status FLASH_GetStatus(void)
}
else
{
- if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
+ if((FLASH->SR & (uint32_t)0xE0) != (uint32_t)0x00)
{
flashstatus = FLASH_ERROR_PROGRAM;
}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c
similarity index 97%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c
index 11e81b643..2b02dfccb 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash_ramfunc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_flash_ramfunc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief FLASH RAMFUNC module driver.
* This file provides a FLASH firmware functions which should be
* executed from internal SRAM
@@ -37,7 +37,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c
similarity index 79%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c
index fd81167eb..1b68c106d 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fmc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the FMC peripheral:
* + Interface with SRAM, PSRAM, NOR and OneNAND memories
@@ -15,7 +15,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -162,7 +162,7 @@ void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
*/
void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
{
- uint32_t tmpr = 0;
+ uint32_t tmpr = 0, tmpbcr = 0, tmpbwr = 0;
/* Check the parameters */
assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
@@ -187,23 +187,34 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
+ /* Get the BTCR register value */
+ tmpbcr = FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank];
+
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
+ tmpbcr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
+ FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
+ FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
+ FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
+ FMC_BCR1_ASYNCWAIT| FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN));
+
/* NOR/SRAM Bank control register configuration */
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
- FMC_NORSRAMInitStruct->FMC_MemoryType |
- FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
- FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
- FMC_NORSRAMInitStruct->FMC_WrapMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
- FMC_NORSRAMInitStruct->FMC_WriteOperation |
- FMC_NORSRAMInitStruct->FMC_WaitSignal |
- FMC_NORSRAMInitStruct->FMC_ExtendedMode |
- FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
- FMC_NORSRAMInitStruct->FMC_WriteBurst |
- FMC_NORSRAMInitStruct->FMC_ContinousClock;
+ tmpbcr |= (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
+ FMC_NORSRAMInitStruct->FMC_MemoryType |
+ FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
+ FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
+ FMC_NORSRAMInitStruct->FMC_WrapMode |
+ FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
+ FMC_NORSRAMInitStruct->FMC_WriteOperation |
+ FMC_NORSRAMInitStruct->FMC_WaitSignal |
+ FMC_NORSRAMInitStruct->FMC_ExtendedMode |
+ FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
+ FMC_NORSRAMInitStruct->FMC_WriteBurst |
+ FMC_NORSRAMInitStruct->FMC_ContinousClock;
+
+ FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] = tmpbcr;
-
if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
{
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
@@ -222,12 +233,12 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
/* NOR/SRAM Bank timing register configuration */
FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
(uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision << 20) |
+ (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency << 24) |
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
/* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
@@ -235,17 +246,23 @@ void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
- assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
+ assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration));
assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
- FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
+ /* Get the BWTR register value */
+ tmpbwr = FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
+ tmpbwr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
+ FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
+
+ tmpbwr |= (uint32_t)(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4)|
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
+ (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode);
+
+ FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = tmpbwr;
}
else
{
@@ -278,8 +295,8 @@ void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)&FMC_DefaultTimingStruct;
+ FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FMC_DefaultTimingStruct);
+ FMC_NORSRAMInitStruct->FMC_WriteTimingStruct = (FMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FMC_DefaultTimingStruct);
}
/**
@@ -417,28 +434,74 @@ void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
+
+ if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppcr = FMC_Bank2->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppcr = FMC_Bank3->PCR3;
+ }
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmppcr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
+ FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
+ FMC_PCR2_TAR | FMC_PCR2_ECCPS));
+
/* Set the tmppcr value according to FMC_NANDInitStruct parameters */
- tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FMC_NANDInitStruct->FMC_MemoryDataWidth |
- FMC_NANDInitStruct->FMC_ECC |
- FMC_NANDInitStruct->FMC_ECCPageSize |
- (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
- (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
- tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+ tmppcr |= (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
+ PCR_MEMORYTYPE_NAND |
+ FMC_NANDInitStruct->FMC_MemoryDataWidth |
+ FMC_NANDInitStruct->FMC_ECC |
+ FMC_NANDInitStruct->FMC_ECCPageSize |
+ (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
+ (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
+
+ if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppmem = FMC_Bank2->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppmem = FMC_Bank3->PMEM3;
+ }
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmppmem &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
+ FMC_PMEM2_MEMHIZ2));
+
+ /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
+ tmppmem |= (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppatt = FMC_Bank2->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppatt = FMC_Bank3->PATT3;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmppatt &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
+ FMC_PATT2_ATTHIZ2));
+
+ /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
+ tmppatt |= (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
{
/* FMC_Bank2_NAND registers configuration */
@@ -653,6 +716,9 @@ void FMC_PCCARDDeInit(void)
*/
void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
{
+ /* temporary registers */
+ uint32_t tmppcr = 0, tmpmem = 0, tmppatt = 0, tmppio = 0;
+
/* Check the parameters */
assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
@@ -672,29 +738,65 @@ void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
+ /* Get PCCARD control register value */
+ tmppcr = FMC_Bank4->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmppcr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
+ FMC_PCR4_PWID));
+
/* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
- FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
- FMC_NAND_MemoryDataWidth_16b |
- (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
- (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
-
+ tmppcr |= (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
+ FMC_NAND_MemoryDataWidth_16b |
+ (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
+ (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
+
+ FMC_Bank4->PCR4 = tmppcr;
+
+ /* Get PCCARD common space timing register value */
+ tmpmem = FMC_Bank4->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmpmem &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
+ FMC_PMEM4_MEMHIZ4));
+
/* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
- FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
+ tmpmem |= (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
+
+ FMC_Bank4->PMEM4 = tmpmem;
+
+ /* Get PCCARD timing parameters */
+ tmppatt = FMC_Bank4->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmppatt &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
+ FMC_PATT4_ATTHIZ4));
+
/* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
- FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
+ tmppatt |= (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ FMC_Bank4->PATT4 = tmppatt;
+
+ /* Get FMC_PCCARD device timing parameters */
+ tmppio = FMC_Bank4->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmppio &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
+ FMC_PIO4_IOHIZ4));
+
/* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
- FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
+ tmppio |= (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
+ (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
+
+ FMC_Bank4->PIO4 = tmppio;
}
/**
@@ -824,10 +926,7 @@ void FMC_SDRAMDeInit(uint32_t FMC_Bank)
void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
{
/* temporary registers */
- uint32_t tmpr1 = 0;
- uint32_t tmpr2 = 0;
- uint32_t tmpr3 = 0;
- uint32_t tmpr4 = 0;
+ uint32_t tmpr1 = 0, tmpr2 = 0, tmpr3 = 0, tmpr4 = 0;
/* Check the parameters */
@@ -852,16 +951,24 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
+ /* Get SDRAM register value */
+ tmpr1 = FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
/* SDRAM bank control register configuration */
- tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
- FMC_SDRAMInitStruct->FMC_RowBitsNumber |
- FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
- FMC_SDRAMInitStruct->FMC_InternalBankNumber |
- FMC_SDRAMInitStruct->FMC_CASLatency |
- FMC_SDRAMInitStruct->FMC_WriteProtection |
- FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+ tmpr1 |= (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
+ FMC_SDRAMInitStruct->FMC_RowBitsNumber |
+ FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
+ FMC_SDRAMInitStruct->FMC_InternalBankNumber |
+ FMC_SDRAMInitStruct->FMC_CASLatency |
+ FMC_SDRAMInitStruct->FMC_WriteProtection |
+ FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
{
@@ -869,9 +976,17 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
}
else /* SDCR2 "don't care" bits configuration */
{
- tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
+ /* Get SDCR register value */
+ tmpr3 = FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM];
+
+ /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
+ tmpr3 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
+ FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
+ FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
+
+ tmpr3 |= (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
+ FMC_SDRAMInitStruct->FMC_ReadBurst |
+ FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
@@ -879,25 +994,49 @@ void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
/* SDRAM bank timing register configuration */
if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
{
- tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
+ /* Get SDTR register value */
+ tmpr2 = FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr2 |= (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
}
else /* SDTR "don't care bits configuration */
{
- tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
-
- tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
+ /* Get SDTR register value */
+ tmpr2 = FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr2 |= (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
+
+ /* Get SDTR register value */
+ tmpr4 = FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM];
+
+ /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
+ tmpr4 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
+ FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
+ FMC_SDTR1_TRCD));
+
+ tmpr4 |= (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
+ (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
similarity index 82%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
index 38c23a584..32612ba0f 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_fsmc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the FSMC peripheral:
* + Interface with SRAM, PSRAM, NOR and OneNAND memories
@@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -155,6 +155,8 @@ void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
*/
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
{
+ uint32_t tmpbcr = 0, tmpbtr = 0, tmpbwr = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
@@ -176,10 +178,20 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
-
+
+ /* Get the BTCR register value */
+ tmpbcr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank];
+
+ /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
+ WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */
+ tmpbcr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \
+ FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \
+ FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \
+ FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \
+ FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CBURSTRW));
+
/* Bank1 NOR/SRAM control register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+ tmpbcr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
@@ -191,13 +203,24 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbcr;
+
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
{
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
}
+
+ /* Get the BTCR register value */
+ tmpbtr = FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
+ tmpbtr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \
+ FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \
+ FSMC_BTR1_ACCMOD));
+
/* Bank1 NOR/SRAM timing register configuration */
- FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+ tmpbtr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
@@ -205,23 +228,31 @@ void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
-
+ FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = tmpbtr;
+
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
{
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
- assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
- assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+ assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration));
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
- FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
- (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
- (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+
+ /* Get the BWTR register value */
+ tmpbwr = FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank];
+
+ /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, and ACCMOD bits */
+ tmpbwr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \
+ FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD));
+
+ tmpbwr |= (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+ (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+
+ FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = tmpbwr;
}
else
{
@@ -251,8 +282,8 @@ void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
- FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
- FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)&FSMC_DefaultTimingStruct;
+ FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct);
+ FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct = (FSMC_NORSRAMTimingInitTypeDef*)((uint32_t)&FSMC_DefaultTimingStruct);
}
/**
@@ -391,26 +422,72 @@ void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppcr = FSMC_Bank2->PCR2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppcr = FSMC_Bank3->PCR3;
+ }
+
+ /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
+ tmppcr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \
+ FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
+ FSMC_PCR2_TAR | FSMC_PCR2_ECCPS));
+
/* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
- tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
- FSMC_NANDInitStruct->FSMC_ECC |
- FSMC_NANDInitStruct->FSMC_ECCPageSize |
- (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
- (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
-
+ tmppcr |= (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+ PCR_MEMORYTYPE_NAND |
+ FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+ FSMC_NANDInitStruct->FSMC_ECC |
+ FSMC_NANDInitStruct->FSMC_ECCPageSize |
+ (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+ (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppmem = FSMC_Bank2->PMEM2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppmem = FSMC_Bank3->PMEM3;
+ }
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmppmem &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \
+ FSMC_PMEM2_MEMHIZ2));
+
/* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
- tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
+ tmppmem |= (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+ {
+ /* Get the NAND bank 2 register value */
+ tmppatt = FSMC_Bank2->PATT2;
+ }
+ else
+ {
+ /* Get the NAND bank 3 register value */
+ tmppatt = FSMC_Bank2->PATT2;
+ }
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmppatt &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \
+ FSMC_PATT2_ATTHIZ2));
+
/* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+ tmppatt |= (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
{
@@ -626,6 +703,8 @@ void FSMC_PCCARDDeInit(void)
*/
void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
{
+ uint32_t tmppcr4 = 0, tmppmem4 = 0, tmppatt4 = 0, tmppio4 = 0;
+
/* Check the parameters */
assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
@@ -645,29 +724,65 @@ void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+ /* Get PCCARD control register value */
+ tmppcr4 = FSMC_Bank4->PCR4;
+
+ /* Clear TAR, TCLR, PWAITEN and PWID bits */
+ tmppcr4 &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
+ FSMC_PCR4_PWID));
+
/* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
- FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
- FSMC_MemoryDataWidth_16b |
- (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
- (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
-
+ tmppcr4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+ FSMC_MemoryDataWidth_16b |
+ (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+ (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+
+ FSMC_Bank4->PCR4 = tmppcr4;
+
+ /* Get PCCARD common space timing register value */
+ tmppmem4 = FSMC_Bank4->PMEM4;
+
+ /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
+ tmppmem4 &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \
+ FSMC_PMEM4_MEMHIZ4));
+
/* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
- FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
+ tmppmem4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ FSMC_Bank4->PMEM4 = tmppmem4;
+
+ /* Get PCCARD timing parameters */
+ tmppatt4 = FSMC_Bank4->PATT4;
+
+ /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
+ tmppatt4 &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \
+ FSMC_PATT4_ATTHIZ4));
+
/* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
- FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
-
+ tmppatt4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ FSMC_Bank4->PATT4 = tmppatt4;
+
+ /* Get FSMC_PCCARD device timing parameters */
+ tmppio4 = FSMC_Bank4->PIO4;
+
+ /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
+ tmppio4 &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \
+ FSMC_PIO4_IOHIZ4));
+
/* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
- FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
- (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+ tmppio4 |= (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+ (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+
+ FSMC_Bank4->PIO4 = tmppio4;
}
/**
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
index 0523e5051..c3485cc65 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_gpio.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the GPIO peripheral:
* + Initialization and Configuration
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
index 880889542..0be685d2d 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the HASH / HMAC Processor (HASH) peripheral:
* - Initialization and Configuration functions
@@ -23,7 +23,7 @@
(#) Enable the HASH controller clock using
RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
- (#) Initialise the HASH using HASH_Init() function.
+ (#) Initialize the HASH using HASH_Init() function.
(#) Reset the HASH processor core, so that the HASH will be ready
to compute he message digest of a new message by using HASH_Reset() function.
@@ -78,7 +78,7 @@
[..]To compute the HMAC, four different phases are required:
- (#) Initialise the HASH using HASH_Init() function to do HMAC
+ (#) Initialize the HASH using HASH_Init() function to do HMAC
operation.
(#) The key (to be used for the inner hash function) is then given to the core.
@@ -102,7 +102,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
index 0a5f1da06..ab374a0fe 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_md5.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides high level functions to compute the HASH MD5 and
* HMAC MD5 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
@@ -26,7 +26,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
index c595ef8bc..fa9261b68 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_hash_sha1.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides high level functions to compute the HASH SHA1 and
* HMAC SHA1 Digest of an input message.
* It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
@@ -26,7 +26,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
index 456efc072..28a0084ed 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_i2c.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Inter-integrated circuit (I2C)
* + Initialization and Configuration
@@ -71,7 +71,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -330,7 +330,7 @@ void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
/**
* @brief Enables or disables the Analog filter of I2C peripheral.
*
- * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+ * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices.
*
* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
* @param NewState: new state of the Analog filter.
@@ -359,7 +359,7 @@ void I2C_AnalogFilterCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
/**
* @brief Configures the Digital noise filter of I2C peripheral.
*
- * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx and STM32F411xE devices.
+ * @note This function can be used only for STM32F42xxx/STM3243xxx, STM32F401xx, STM32F410xx and STM32F411xE devices.
*
* @param I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
* @param I2C_DigitalFilter: Coefficient of digital noise filter.
@@ -556,12 +556,12 @@ void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
- /* Enable generall call */
+ /* Enable general call */
I2Cx->CR1 |= I2C_CR1_ENGC;
}
else
{
- /* Disable generall call */
+ /* Disable general call */
I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
}
}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
index 4adc69b36..7d131c645 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_iwdg.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Independent watchdog (IWDG) peripheral:
* + Prescaler and Counter configuration
@@ -64,7 +64,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c
index ded1928a8..490860450 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_ltdc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_ltdc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the LTDC controller (LTDC) peripheral:
* + Initialization and configuration
@@ -38,14 +38,14 @@
(++) If needed, configure the default color and the blending factors
respectively in the LTDC_LxDCCR and LTDC_LxBFCR registers
- (++) If needed, Dithering and color keying can be be enabled respectively
+ (++) If needed, Dithering and color keying can be enabled respectively
in the LTDC_GCR and LTDC_LxCKCR registers. It can be also enabled
on the fly.
(#) Enable Layer1/2 and if needed the CLUT in the LTDC_LxCR register
(#) Reload the shadow registers to active register through
the LTDC_SRCR register.
- -@- All layer parameters can be be modified on the fly except the CLUT.
+ -@- All layer parameters can be modified on the fly except the CLUT.
The new configuration has to be either reloaded immediately
or during vertical blanking period by configuring the LTDC_SRCR register.
(#) Call the LTDC_Cmd() to enable the LTDC controller.
@@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -686,7 +686,7 @@ void LTDC_CLUTInit(LTDC_Layer_TypeDef* LTDC_Layerx, LTDC_CLUT_InitTypeDef* LTDC_
void LTDC_CLUTStructInit(LTDC_CLUT_InitTypeDef* LTDC_CLUT_InitStruct)
{
- /*!< Initialize the CLUT adress and RGB values */
+ /*!< Initialize the CLUT address and RGB values */
LTDC_CLUT_InitStruct->LTDC_CLUTAdress = 0x00;
LTDC_CLUT_InitStruct->LTDC_BlueValue = 0x00;
LTDC_CLUT_InitStruct->LTDC_GreenValue = 0x00;
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
similarity index 84%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
index 1c797825d..8201cb10d 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_pwr.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Backup Domain Access
@@ -17,7 +17,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -79,6 +79,17 @@
#define ODSWEN_BitNumber 0x11
#define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
+/* Alias word address of MRUDS bit */
+#define MRUDS_BitNumber 0x0B
+#define CR_MRUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRUDS_BitNumber * 4))
+
+/* Alias word address of LPUDS bit */
+#define LPUDS_BitNumber 0x0A
+#define CR_LPUDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPUDS_BitNumber * 4))
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
+
+#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
/* Alias word address of MRLVDS bit */
#define MRLVDS_BitNumber 0x0B
#define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
@@ -86,13 +97,28 @@
/* Alias word address of LPLVDS bit */
#define LPLVDS_BitNumber 0x0A
#define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
+#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
/* --- CSR Register ---*/
-
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
/* Alias word address of EWUP bit */
#define CSR_OFFSET (PWR_OFFSET + 0x04)
#define EWUP_BitNumber 0x08
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F469_479xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/* Alias word address of EWUP2 bit */
+#define CSR_OFFSET (PWR_OFFSET + 0x04)
+#define EWUP1_BitNumber 0x08
+#define CSR_EWUP1_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP1_BitNumber * 4))
+#define EWUP2_BitNumber 0x07
+#define CSR_EWUP2_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+#define EWUP3_BitNumber 0x06
+#define CSR_EWUP3_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP2_BitNumber * 4))
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
/* Alias word address of BRE bit */
#define BRE_BitNumber 0x09
@@ -115,8 +141,8 @@
*/
/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
+ * @brief Backup Domain Access function
+ *
@verbatim
===============================================================================
##### Backup Domain Access function #####
@@ -167,8 +193,8 @@ void PWR_BackupAccessCmd(FunctionalState NewState)
*/
/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
+ * @brief PVD configuration functions
+ *
@verbatim
===============================================================================
##### PVD configuration functions #####
@@ -240,8 +266,8 @@ void PWR_PVDCmd(FunctionalState NewState)
*/
/** @defgroup PWR_Group3 WakeUp pin configuration functions
- * @brief WakeUp pin configuration functions
- *
+ * @brief WakeUp pin configuration functions
+ *
@verbatim
===============================================================================
##### WakeUp pin configuration functions #####
@@ -249,12 +275,13 @@ void PWR_PVDCmd(FunctionalState NewState)
[..]
(+) WakeUp pin is used to wakeup the system from Standby mode. This pin is
forced in input pull down configuration and is active on rising edges.
- (+) There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
-
+ (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+ (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+ (++) For STM32F410xx/STM32F412xG/STM32F413_423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
@endverbatim
* @{
*/
-
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
/**
* @brief Enables or disables the WakeUp Pin functionality.
* @param NewState: new state of the WakeUp Pin functionality.
@@ -268,14 +295,49 @@ void PWR_WakeUpPinCmd(FunctionalState NewState)
*(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Enables or disables the WakeUp Pin functionality.
+ * @param PWR_WakeUpPinx: specifies the WakeUp Pin.
+ * This parameter can be one of the following values:
+ * @arg PWR_WakeUp_Pin1: WKUP1 pin is used for wakeup from Standby mode.
+ * @arg PWR_WakeUp_Pin2: WKUP2 pin is used for wakeup from Standby mode.
+ * @arg PWR_WakeUp_Pin3: WKUP3 pin is used for wakeup from Standby mode.(only for STM32F410xx, STM32F412xG and STM32F413_423xx Devices)
+ * @param NewState: new state of the WakeUp Pin functionality.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_PWR_WAKEUP_PIN(NewState));
+ if(PWR_WakeUpPinx == PWR_WakeUp_Pin1) /* PWR_WakeUp_Pin1 */
+ {
+ *(__IO uint32_t *) CSR_EWUP1_BB = (uint32_t)NewState;
+ }
+#if defined(STM32F410xx)|| defined(STM32F412xG) || defined(STM32F413_423xx)
+ else if(PWR_WakeUpPinx == PWR_WakeUp_Pin3) /* PWR_WakeUp_Pin3 */
+ {
+ *(__IO uint32_t *) CSR_EWUP3_BB = (uint32_t)NewState;
+ }
+#endif /* STM32F410xx */
+ else /* PWR_WakeUp_Pin2 */
+ {
+ *(__IO uint32_t *) CSR_EWUP2_BB = (uint32_t)NewState;
+ }
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
/**
* @}
*/
/** @defgroup PWR_Group4 Main and Backup Regulators configuration functions
- * @brief Main and Backup Regulators configuration functions
- *
+ * @brief Main and Backup Regulators configuration functions
+ *
@verbatim
===============================================================================
##### Main and Backup Regulators configuration functions #####
@@ -477,12 +539,63 @@ void PWR_UnderDriveCmd(FunctionalState NewState)
}
}
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
+/**
+ * @brief Enables or disables the Main Regulator under drive mode.
+ *
+ * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
+ *
+ * @param NewState: new state of the Main Regulator Under Drive mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)ENABLE;
+ }
+ else
+ {
+ *(__IO uint32_t *) CR_MRUDS_BB = (uint32_t)DISABLE;
+ }
+}
+
+/**
+ * @brief Enables or disables the Low Power Regulator under drive mode.
+ *
+ * @note This mode is only available for STM32F427_437xx/STM32F429_439xx/STM32F446xx devices.
+ *
+ * @param NewState: new state of the Low Power Regulator Under Drive mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)ENABLE;
+ }
+ else
+ {
+ *(__IO uint32_t *) CR_LPUDS_BB = (uint32_t)DISABLE;
+ }
+}
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
+
+#if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
/**
* @brief Enables or disables the Main Regulator low voltage mode.
*
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices.
*
- * @param NewState: new state of the Under Drive mode.
+ * @param NewState: new state of the Main Regulator Low Voltage mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -504,9 +617,9 @@ void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState)
/**
* @brief Enables or disables the Low Power Regulator low voltage mode.
*
- * @note This mode is only available for STM32F401xx/STM32F411xx devices.
+ * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412xG/STM32F413_423xx devices.
*
- * @param NewState: new state of the Under Drive mode.
+ * @param NewState: new state of the Low Power Regulator Low Voltage mode.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
@@ -524,14 +637,15 @@ void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
}
}
+#endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
/**
* @}
*/
/** @defgroup PWR_Group5 FLASH Power Down configuration functions
- * @brief FLASH Power Down configuration functions
- *
+ * @brief FLASH Power Down configuration functions
+ *
@verbatim
===============================================================================
##### FLASH Power Down configuration functions #####
@@ -565,8 +679,8 @@ void PWR_FlashPowerDownCmd(FunctionalState NewState)
*/
/** @defgroup PWR_Group6 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
+ * @brief Low Power modes configuration functions
+ *
@verbatim
===============================================================================
##### Low Power modes configuration functions #####
@@ -832,8 +946,8 @@ void PWR_EnterSTANDBYMode(void)
*/
/** @defgroup PWR_Group7 Flags management functions
- * @brief Flags management functions
- *
+ * @brief Flags management functions
+ *
@verbatim
===============================================================================
##### Flags management functions #####
@@ -866,7 +980,7 @@ void PWR_EnterSTANDBYMode(void)
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
* is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
- * switcching is ready (STM32F42xxx/43xxx devices)
+ * switching is ready (STM32F42xxx/43xxx devices)
* @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
* is enabled in Stop mode (STM32F42xxx/43xxx devices)
* @retval The new state of PWR_FLAG (SET or RESET).
@@ -915,9 +1029,9 @@ void PWR_ClearFlag(uint32_t PWR_FLAG)
}
#endif /* STM32F427_437xx || STM32F429_439xx */
-#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F411xE)
+#if defined (STM32F40_41xxx) || defined (STM32F401xx) || defined (STM32F410xx) || defined (STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
PWR->CR |= PWR_FLAG << 2;
-#endif /* STM32F40_41xxx || STM32F401xx || STM32F411xE */
+#endif /* STM32F40_41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
}
/**
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
similarity index 68%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
index 202afaf75..823c1ba06 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rcc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Reset and clock control (RCC) peripheral:
* + Internal/external clocks, PLL, CSS and MCO configuration
@@ -11,7 +11,7 @@
* + Peripheral clocks configuration
* + Interrupts and flags management
*
- @verbatim
+ @verbatim
===============================================================================
##### RCC specific features #####
===============================================================================
@@ -26,19 +26,19 @@
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
[..]
- Once the device started from reset, the user application has to:
+ Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+ derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
@endverbatim
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -116,6 +116,18 @@
#define DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
#define TIMPRE_BitNumber 0x18
#define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
+ #if defined(STM32F410xx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER 0x8
+#define RCC_CFGR_MCO1EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO1EN_BIT_NUMBER * 4))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER 0x9
+#define RCC_CFGR_MCO2EN_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_MCO2EN_BIT_NUMBER * 4))
+#endif /* STM32F410xx */
/* ---------------------- RCC registers bit mask ------------------------ */
/* CFGR register bit mask */
#define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF)
@@ -138,7 +150,7 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
-static const __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
@@ -153,7 +165,7 @@ static const __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3
@verbatim
===================================================================================
##### Internal and external clocks, PLL, CSS and MCO configuration functions #####
- ===================================================================================
+ ===================================================================================
[..]
This section provide functions allowing to configure the internal/external clocks,
PLLs, CSS and MCO pins.
@@ -179,7 +191,7 @@ static const __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3
of STM32F429x/439x devices.
(#) PLLSAI clocked by (HSI or HSE), used to generate an accurate clock to SAI
- interface and LCD TFT controller available only for STM32F42xxx/43xxx devices.
+ interface and LCD TFT controller available only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
(#) CSS (Clock security system), once enable and if a HSE clock failure occurs
(HSE used directly or through PLL as System clock source), the System clock
@@ -218,26 +230,35 @@ void RCC_DeInit(void)
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
- /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42/43xxx devices) bits */
+ /* Reset HSEON, CSSON, PLLON, PLLI2S and PLLSAI(STM32F42xxx/43xxx/446xx/469xx/479xx devices) bits */
RCC->CR &= (uint32_t)0xEAF6FFFF;
-
+
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F413_423xx) || defined(STM32F469_479xx)
/* Reset PLLI2SCFGR register */
RCC->PLLI2SCFGR = 0x20003000;
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F413_423xx || STM32F469_479xx */
- /* Reset PLLSAICFGR register, only available for STM32F42/43xxx devices */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+ /* Reset PLLSAICFGR register, only available for STM32F42xxx/43xxx/446xx/469xx/479xx devices */
RCC->PLLSAICFGR = 0x24003000;
-
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
+
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
- /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx devices */
- RCC->DCKCFGR = 0x00000000;
+ /* Disable Timers clock prescalers selection, only available for STM32F42/43xxx and STM32F413_423xx devices */
+ RCC->DCKCFGR = 0x00000000;
+
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+ /* Disable LPTIM and FMPI2C clock prescalers selection, only available for STM32F410xx and STM32F413_423xx devices */
+ RCC->DCKCFGR2 = 0x00000000;
+#endif /* STM32F410xx || STM32F413_423xx */
}
/**
@@ -424,6 +445,7 @@ void RCC_LSICmd(FunctionalState NewState)
*(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
}
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/**
* @brief Configures the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
@@ -441,9 +463,64 @@ void RCC_LSICmd(FunctionalState NewState)
* of 2 MHz to limit PLL jitter.
*
* @param PLLN: specifies the multiplication factor for PLL VCO output clock
- * This parameter must be a number between 192 and 432.
+ * This parameter must be a number between 50 and 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLP: specifies the division factor for main system clock (SYSCLK)
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ * @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
+ * the System clock frequency.
+ *
+ * @param PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * This parameter must be a number between 4 and 15.
+ *
+ * @param PLLR: specifies the division factor for I2S, SAI, SYSTEM, SPDIF in STM32F446xx devices
+ * This parameter must be a number between 2 and 7.
+ *
+ * @note If the USB OTG FS is used in your application, you have to set the
+ * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+ * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+ * correctly.
+ *
+ * @retval None
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ, uint32_t PLLR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+ assert_param(IS_RCC_PLLM_VALUE(PLLM));
+ assert_param(IS_RCC_PLLN_VALUE(PLLN));
+ assert_param(IS_RCC_PLLP_VALUE(PLLP));
+ assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
+ assert_param(IS_RCC_PLLR_VALUE(PLLR));
+
+ RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
+ (PLLQ << 24) | (PLLR << 28);
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
+/**
+ * @brief Configures the main PLL clock source, multiplication and division factors.
+ * @note This function must be used only when the main PLL is disabled.
+ *
+ * @param RCC_PLLSource: specifies the PLL entry clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
+ * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
+ * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
+ *
+ * @param PLLM: specifies the division factor for PLL VCO input clock
+ * This parameter must be a number between 0 and 63.
+ * @note You have to set the PLLM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLL jitter.
+ *
+ * @param PLLN: specifies the multiplication factor for PLL VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
*
* @param PLLP: specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
@@ -471,6 +548,7 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_
RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
(PLLQ << 24);
}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
/**
* @brief Enables or disables the main PLL.
@@ -489,7 +567,7 @@ void RCC_PLLCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
}
-#if defined (STM32F40_41xxx) || defined (STM32F401xx)
+#if defined(STM32F40_41xxx) || defined(STM32F401xx)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
@@ -501,9 +579,9 @@ void RCC_PLLCmd(FunctionalState NewState)
* RCC_PLLConfig function )
*
* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
+ * This parameter must be a number between 50 and 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
+ * output frequency is between 100 and 432 MHz.
*
* @param PLLI2SR: specifies the division factor for I2S clock
* This parameter must be a number between 2 and 7.
@@ -520,8 +598,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
}
+#endif /* STM32F40_41xxx || STM32F401xx */
-#elif defined (STM32F411xE)
+#if defined(STM32F411xE)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
@@ -538,9 +617,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
* of 2 MHz to limit PLLI2S jitter.
*
* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
+ * This parameter must be a number between 50 and 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
+ * output frequency is between 100 and 432 MHz.
*
* @param PLLI2SR: specifies the division factor for I2S clock
* This parameter must be a number between 2 and 7.
@@ -558,8 +637,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28) | PLLI2SM;
}
+#endif /* STM32F411xE */
-#elif defined (STM32F427_437xx) || defined (STM32F429_439xx)
+#if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/**
* @brief Configures the PLLI2S clock multiplication and division factors.
*
@@ -570,9 +650,9 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
* RCC_PLLConfig function )
*
* @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
- * This parameter must be a number between 192 and 432.
+ * This parameter must be a number between 50 and 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
+ * output frequency is between 100 and 432 MHz.
*
* @param PLLI2SQ: specifies the division factor for SAI1 clock
* This parameter must be a number between 2 and 15.
@@ -581,7 +661,6 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR, uint32_t PLLI2SM)
* This parameter must be a number between 2 and 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
- * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
*
* @retval None
*/
@@ -594,8 +673,55 @@ void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SQ, uint32_t PLLI2SR)
RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SQ << 24) | (PLLI2SR << 28);
}
-#else
-#endif /* STM32F40_41xxx || STM32F401xx */
+#endif /* STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+
+#if defined(STM32F412xG ) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the PLLI2S clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F446xx devices
+ *
+ * @note This function must be used only when the PLLI2S is disabled.
+ * @note PLLI2S clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLI2SM: specifies the division factor for PLLI2S VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLI2S jitter.
+ *
+ * @param PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLI2SP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param PLLI2SQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLI2SR: specifies the division factor for I2S clock
+ * This parameter must be a number between 2 and 7.
+ * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+ * on the I2S clock frequency.
+ * @note the PLLI2SR parameter is only available with STM32F42xxx/43xxx devices.
+ *
+ * @retval None
+ */
+void RCC_PLLI2SConfig(uint32_t PLLI2SM, uint32_t PLLI2SN, uint32_t PLLI2SP, uint32_t PLLI2SQ, uint32_t PLLI2SR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SM));
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+ assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SP));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SQ));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
+
+ RCC->PLLI2SCFGR = PLLI2SM | (PLLI2SN << 6) | (((PLLI2SP >> 1) -1) << 16) | (PLLI2SQ << 24) | (PLLI2SR << 28);
+}
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
/**
* @brief Enables or disables the PLLI2S.
@@ -610,6 +736,86 @@ void RCC_PLLI2SCmd(FunctionalState NewState)
*(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
}
+#if defined(STM32F469_479xx)
+/**
+ * @brief Configures the PLLSAI clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F469_479xx devices
+ *
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}..
+ *
+ * @param PLLSAIQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @param PLLSAIR: specifies the division factor for LTDC clock
+ * This parameter must be a number between 2 and 7.
+ *
+ * @retval None
+ */
+void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ, uint32_t PLLSAIR)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
+ assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
+
+ RCC->PLLSAICFGR = (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24) | (PLLSAIR << 28);
+}
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Configures the PLLSAI clock multiplication and division factors.
+ *
+ * @note This function can be used only for STM32F446xx devices
+ *
+ * @note This function must be used only when the PLLSAI is disabled.
+ * @note PLLSAI clock source is common with the main PLL (configured in
+ * RCC_PLLConfig function )
+ *
+ * @param PLLSAIM: specifies the division factor for PLLSAI VCO input clock
+ * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+ * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+ * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+ * of 2 MHz to limit PLLSAI jitter.
+ *
+ * @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
+ * This parameter must be a number between 50 and 432.
+ * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
+ * output frequency is between 100 and 432 MHz.
+ *
+ * @param PLLSAIP: specifies the division factor for PLL 48Mhz clock output
+ * This parameter must be a number in the range {2, 4, 6, or 8}.
+ *
+ * @param PLLSAIQ: specifies the division factor for SAI1 clock
+ * This parameter must be a number between 2 and 15.
+ *
+ * @retval None
+ */
+void RCC_PLLSAIConfig(uint32_t PLLSAIM, uint32_t PLLSAIN, uint32_t PLLSAIP, uint32_t PLLSAIQ)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIM));
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIP));
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
+
+ RCC->PLLSAICFGR = PLLSAIM | (PLLSAIN << 6) | (((PLLSAIP >> 1) -1) << 16) | (PLLSAIQ << 24);
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
/**
* @brief Configures the PLLSAI clock multiplication and division factors.
*
@@ -620,9 +826,9 @@ void RCC_PLLI2SCmd(FunctionalState NewState)
* RCC_PLLConfig function )
*
* @param PLLSAIN: specifies the multiplication factor for PLLSAI VCO output clock
- * This parameter must be a number between 192 and 432.
+ * This parameter must be a number between 50 and 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
- * output frequency is between 192 and 432 MHz.
+ * output frequency is between 100 and 432 MHz.
*
* @param PLLSAIQ: specifies the division factor for SAI1 clock
* This parameter must be a number between 2 and 15.
@@ -637,14 +843,16 @@ void RCC_PLLSAIConfig(uint32_t PLLSAIN, uint32_t PLLSAIQ, uint32_t PLLSAIR)
/* Check the parameters */
assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIN));
assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIR));
-
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIQ));
+
RCC->PLLSAICFGR = (PLLSAIN << 6) | (PLLSAIQ << 24) | (PLLSAIR << 28);
}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
/**
* @brief Enables or disables the PLLSAI.
*
- * @note This function can be used only for STM32F42xxx/43xxx devices
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices
*
* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
* @param NewState: new state of the PLLSAI. This parameter can be: ENABLE or DISABLE.
@@ -708,9 +916,13 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
/* Select MCO1 clock source and prescaler */
tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
-
+
/* Store the new value */
- RCC->CFGR = tmpreg;
+ RCC->CFGR = tmpreg;
+
+#if defined(STM32F410xx)
+ RCC_MCO1Cmd(ENABLE);
+#endif /* STM32F410xx */
}
/**
@@ -719,7 +931,8 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
* @param RCC_MCO2Source: specifies the clock source to output.
* This parameter can be one of the following values:
* @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410xx devices
* @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
* @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
* @param RCC_MCO2Div: specifies the MCO2 prescaler.
@@ -729,6 +942,8 @@ void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
* @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
* @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
* @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
+ * @note For STM32F410xx devices to output I2SCLK clock on MCO2 you should have
+ * at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
* @retval None
*/
void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
@@ -746,9 +961,13 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
/* Select MCO2 clock source and prescaler */
tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
-
+
/* Store the new value */
- RCC->CFGR = tmpreg;
+ RCC->CFGR = tmpreg;
+
+#if defined(STM32F410xx)
+ RCC_MCO2Cmd(ENABLE);
+#endif /* STM32F410xx */
}
/**
@@ -790,77 +1009,77 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
(#) For STM32F405xx/407xx and STM32F415xx/417xx devices, the maximum frequency
of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz. Depending
on the device voltage range, the maximum frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
+ +-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
+ | |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|150< HCLK <= 168|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |154 < HCLK <= 168|140 < HCLK <= 160|
- +---------------|----------------|----------------|-----------------|-----------------+
- (#) For STM32F42xxx/43xxx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
+ +---------------|----------------|----------------|-----------------|-----------------+
+ (#) For STM32F42xxx/43xxx/469xx/479xx devices, the maximum frequency of the SYSCLK and HCLK is 180 MHz,
PCLK2 90 MHz and PCLK1 45 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
+ +-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
+ | |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |66 < HCLK <= 88 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|88 < HCLK <= 110 |80 < HCLK <= 100 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
- |---------------|----------------|----------------|-----------------|-----------------|
- |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |5WS(6CPU cycle)|120< HCLK <= 180|120< HCLK <= 144|110 < HCLK <= 132|100 < HCLK <= 120|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |6WS(7CPU cycle)| NA |144< HCLK <= 168|132 < HCLK <= 154|120 < HCLK <= 140|
+ |---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA |168< HCLK <= 180|154 < HCLK <= 176|140 < HCLK <= 160|
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|8WS(9CPU cycle)| NA | NA |176 < HCLK <= 180|160 < HCLK <= 168|
+-------------------------------------------------------------------------------------+
(#) For STM32F401xx devices, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
PCLK2 84 MHz and PCLK1 42 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
- +-------------------------------------------------------------------------------------+
+ +-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
- | |---------------------------------------------------------------------|
+ | |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 22 |0 < HCLK <= 20 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |22 < HCLK <= 44 |20 < HCLK <= 40 |
+ |---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 84 |48 < HCLK <= 72 |44 < HCLK <= 66 |40 < HCLK <= 60 |
- |---------------|----------------|----------------|-----------------|-----------------|
+ |---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)| NA |72 < HCLK <= 84 |66 < HCLK <= 84 |60 < HCLK <= 80 |
- |---------------|----------------|----------------|-----------------|-----------------|
- |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+ |---------------|----------------|----------------|-----------------|-----------------|
+ |4WS(5CPU cycle)| NA | NA | NA |80 < HCLK <= 84 |
+-------------------------------------------------------------------------------------+
- (#) For STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+ (#) For STM32F410xx/STM32F411xE devices, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
PCLK2 100 MHz and PCLK1 50 MHz. Depending on the device voltage range, the maximum
frequency should be adapted accordingly:
+-------------------------------------------------------------------------------------+
@@ -888,7 +1107,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
(++) when VOS = '0', the maximum value of fHCLK = 144MHz.
(++) when VOS = '1', the maximum value of fHCLK = 168MHz.
[..]
- On STM32F42xxx/43xxx devices:
+ On STM32F42xxx/43xxx/469xx/479xx devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 120MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 144MHz.
(++) when VOS[1:0] = '0x11', the maximum value of f is 168MHz
@@ -896,7 +1115,7 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
On STM32F401x devices:
(++) when VOS[1:0] = '0x01', the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10', the maximum value of fHCLK is 84MHz.
- On STM32F411xE devices:
+ On STM32F410xx/STM32F411xE devices:
(++) when VOS[1:0] = '0x01' the maximum value of fHCLK is 64MHz.
(++) when VOS[1:0] = '0x10' the maximum value of fHCLK is 84MHz.
(++) when VOS[1:0] = '0x11' the maximum value of fHCLK is 100MHz.
@@ -921,9 +1140,10 @@ void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
* currently used as system clock source.
* @param RCC_SYSCLKSource: specifies the clock source used as system clock.
* This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+ * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
+ * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
+ * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source (RCC_SYSCLKSource_PLLPCLK for STM32F446xx devices)
+ * @arg RCC_SYSCLKSource_PLLRCLK: PLL R selected as system clock source only for STM32F412xG, STM32F413_423xx and STM32F446xx devices
* @retval None
*/
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
@@ -952,7 +1172,8 @@ void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
* of the following:
* - 0x00: HSI used as system clock
* - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
+ * - 0x08: PLL used as system clock (PLL P for STM32F446xx devices)
+ * - 0x0C: PLL R used as system clock (only for STM32F412xG, STM32F413_423xx and STM32F446xx devices)
*/
uint8_t RCC_GetSYSCLKSource(void)
{
@@ -998,7 +1219,6 @@ void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
RCC->CFGR = tmpreg;
}
-
/**
* @brief Configures the Low Speed APB clock (PCLK1).
* @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
@@ -1063,7 +1283,7 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK)
/**
* @brief Returns the frequencies of different on chip clocks; SYSCLK, HCLK,
- * PCLK1 and PCLK2.
+ * PCLK1 and PCLK2.
*
* @note The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
@@ -1097,46 +1317,74 @@ void RCC_PCLK2Config(uint32_t RCC_HCLK)
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ uint32_t pllr = 2;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
-
+
switch (tmp)
{
- case 0x00: /* HSI used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
+ case 0x00: /* HSI used as system clock source */
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+ break;
+ case 0x08: /* PLL P used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLP
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
+ break;
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
- SYSCLK = PLL_VCO / PLLP
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
- break;
- default:
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ case 0x0C: /* PLL R used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
+ RCC_Clocks->SYSCLK_Frequency = pllvco/pllr;
+ break;
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+ default:
+ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+ break;
}
/* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
-
+
/* Get HCLK prescaler */
tmp = RCC->CFGR & RCC_CFGR_HPRE;
tmp = tmp >> 4;
@@ -1275,6 +1523,177 @@ void RCC_BackupResetCmd(FunctionalState NewState)
*(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
}
+#if defined (STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S APB clock.
+ *
+ * @param RCC_I2SAPBx: specifies the APBx I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SBus_APB1: I2S peripheral instance is on APB1 Bus
+ * @arg RCC_I2SBus_APB2: I2S peripheral instance is on APB2 Bus
+ *
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SCLKSource_PLLI2S: PLLI2S clock used as I2S clock source
+ * @arg RCC_I2SCLKSource_Ext: External clock mapped on the I2S_CKIN pin
+ * used as I2S clock source
+ * @arg RCC_I2SCLKSource_PLL: PLL clock used as I2S clock source
+ * @arg RCC_I2SCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as I2S clock source
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SAPBx, uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+ assert_param(IS_RCC_I2S_APBx(RCC_I2SAPBx));
+
+ if(RCC_I2SAPBx == RCC_I2SBus_APB1)
+ {
+ /* Clear APB1 I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S1SRC;
+ /* Set new APB1 I2Sx clock source*/
+ RCC->DCKCFGR |= RCC_I2SCLKSource;
+ }
+ else
+ {
+ /* Clear APB2 I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2S2SRC;
+ /* Set new APB2 I2Sx clock source */
+ RCC->DCKCFGR |= (RCC_I2SCLKSource << 2);
+ }
+}
+#if defined(STM32F446xx)
+/**
+ * @brief Configures the SAIx clock source (SAIxCLK).
+ * @note This function must be called before enabling the SAIx APB clock.
+ *
+ * @param RCC_SAIInstance: specifies the SAIx clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIInstance_SAI1: SAI1 clock source selection
+ * @arg RCC_SAIInstance_SAI2: SAI2 clock source selections
+ *
+ * @param RCC_SAICLKSource: specifies the SAI clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAICLKSource_PLLSAI: PLLSAI clock used as SAI clock source
+ * @arg RCC_SAICLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAICLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAICLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAICLKConfig(uint32_t RCC_SAIInstance, uint32_t RCC_SAICLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SAICLK_SOURCE(RCC_SAICLKSource));
+ assert_param(IS_RCC_SAI_INSTANCE(RCC_SAIInstance));
+
+ if(RCC_SAIInstance == RCC_SAIInstance_SAI1)
+ {
+ /* Clear SAI1 clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI1SRC;
+ /* Set new SAI1 clock source */
+ RCC->DCKCFGR |= RCC_SAICLKSource;
+ }
+ else
+ {
+ /* Clear SAI2 clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_SAI2SRC;
+ /* Set new SAI2 clock source */
+ RCC->DCKCFGR |= (RCC_SAICLKSource << 2);
+ }
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures SAI1BlockA clock source selection.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockACLKSource: specifies the SAI Block A clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIACLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAIACLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIACLK_SOURCE(RCC_SAIBlockACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1ASRC;
+
+ /* Set SAI Block A source selection value */
+ tmpreg |= RCC_SAIBlockACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures SAI1BlockB clock source selection.
+ * @note This function must be called before enabling PLLSAI, PLLI2S and
+ * the SAI clock.
+ * @param RCC_SAIBlockBCLKSource: specifies the SAI Block B clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SAIBCLKSource_PLLI2SR: PLLI2SR clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_PLLI2S: PLLI2S clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_PLL: PLL clock used as SAI clock source
+ * @arg RCC_SAIBCLKSource_HSI_HSE: HSI or HSE depends on PLLSRC used as SAI clock source
+ * @retval None
+ */
+void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_SAIBCLK_SOURCE(RCC_SAIBlockBCLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear RCC_DCKCFGR_SAI1ASRC[1:0] bits */
+ tmpreg &= ~RCC_DCKCFGR_SAI1BSRC;
+
+ /* Set SAI Block B source selection value */
+ tmpreg |= RCC_SAIBlockBCLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx */
+
+#if defined(STM32F410xx)
+/**
+ * @brief Configures the I2S clock source (I2SCLK).
+ * @note This function must be called before enabling the I2S clock.
+ *
+ * @param RCC_I2SCLKSource: specifies the I2S clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+ * @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+ * @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+ * @retval None
+ */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+ /* Clear I2Sx clock source selection bits */
+ RCC->DCKCFGR &= ~RCC_DCKCFGR_I2SSRC;
+ /* Set new I2Sx clock source*/
+ RCC->DCKCFGR |= RCC_I2SCLKSource;
+}
+#endif /* STM32F410xx */
+
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE) || defined(STM32F469_479xx)
/**
* @brief Configures the I2S clock source (I2SCLK).
* @note This function must be called before enabling the I2S APB clock.
@@ -1290,77 +1709,15 @@ void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
/* Check the parameters */
assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
- *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
-}
-
-/**
- * @brief Configures the SAI clock Divider coming from PLLI2S.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @note This function must be called before enabling the PLLI2S.
- *
- * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
- *
- * @retval None
- */
-void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLI2SDIVQ[4:0] bits */
- tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
-
- /* Set PLLI2SDIVQ values */
- tmpreg |= (RCC_PLLI2SDivQ - 1);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
-}
-
-/**
- * @brief Configures the SAI clock Divider coming from PLLSAI.
- *
- * @note This function can be used only for STM32F42xxx/43xxx devices.
- *
- * @note This function must be called before enabling the PLLSAI.
- *
- * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
- * This parameter must be a number between 1 and 32.
- * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
- *
- * @retval None
- */
-void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
-
- tmpreg = RCC->DCKCFGR;
-
- /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
- tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
-
- /* Set PLLSAIDIVQ values */
- tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
-
- /* Store the new value */
- RCC->DCKCFGR = tmpreg;
+ *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F469_479xx */
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/**
* @brief Configures SAI1BlockA clock source selection.
*
- * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
*
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
@@ -1396,7 +1753,7 @@ void RCC_SAIBlockACLKConfig(uint32_t RCC_SAIBlockACLKSource)
/**
* @brief Configures SAI1BlockB clock source selection.
*
- * @note This function can be used only for STM32F42xxx/43xxx devices.
+ * @note This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices.
*
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
@@ -1428,18 +1785,149 @@ void RCC_SAIBlockBCLKConfig(uint32_t RCC_SAIBlockBCLKSource)
/* Store the new value */
RCC->DCKCFGR = tmpreg;
}
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+/**
+ * @brief Configures the SAI clock Divider coming from PLLI2S.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling the PLLI2S.
+ *
+ * @param RCC_PLLI2SDivQ: specifies the PLLI2S division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2S_Q) / RCC_PLLI2SDivQ
+ *
+ * @retval None
+ */
+void RCC_SAIPLLI2SClkDivConfig(uint32_t RCC_PLLI2SDivQ)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(RCC_PLLI2SDivQ));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVQ[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVQ);
+
+ /* Set PLLI2SDIVQ values */
+ tmpreg |= (RCC_PLLI2SDivQ - 1);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the SAI clock Divider coming from PLLSAI.
+ *
+ * @note This function can be used only for STM32F42xxx/43xxx/446xx/469xx/479xx devices.
+ *
+ * @note This function must be called before enabling the PLLSAI.
+ *
+ * @param RCC_PLLSAIDivQ: specifies the PLLSAI division factor for SAI1 clock .
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLSAI_Q) / RCC_PLLSAIDivQ
+ *
+ * @retval None
+ */
+void RCC_SAIPLLSAIClkDivConfig(uint32_t RCC_PLLSAIDivQ)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(RCC_PLLSAIDivQ));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVQ[4:0] and PLLSAIDIVQ[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLSAIDIVQ);
+
+ /* Set PLLSAIDIVQ values */
+ tmpreg |= ((RCC_PLLSAIDivQ - 1) << 8);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures the SAI clock Divider coming from PLLI2S.
+ *
+ * @note This function can be used only for STM32F413_423xx
+ *
+ * @param RCC_PLLI2SDivR: specifies the PLLI2S division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLI2SR) / RCC_PLLI2SDivR
+ * @retval None
+ */
+void RCC_SAIPLLI2SRClkDivConfig(uint32_t RCC_PLLI2SDivR)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLLI2S_DIVR_VALUE(RCC_PLLI2SDivR));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLI2SDIVR[4:0] bits */
+ tmpreg &= ~(RCC_DCKCFGR_PLLI2SDIVR);
+
+ /* Set PLLI2SDIVR values */
+ tmpreg |= (RCC_PLLI2SDivR-1);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the SAI clock Divider coming from PLL.
+ *
+ * @note This function can be used only for STM32F413_423xx
+ *
+ * @note This function must be called before enabling the PLLSAI.
+ *
+ * @param RCC_PLLDivR: specifies the PLL division factor for SAI1 clock.
+ * This parameter must be a number between 1 and 32.
+ * SAI1 clock frequency = f(PLLR) / RCC_PLLDivR
+ *
+ * @retval None
+ */
+void RCC_SAIPLLRClkDivConfig(uint32_t RCC_PLLDivR)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_PLL_DIVR_VALUE(RCC_PLLDivR));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear PLLDIVR[12:8] */
+ tmpreg &= ~(RCC_DCKCFGR_PLLDIVR);
+
+ /* Set PLLDivR values */
+ tmpreg |= ((RCC_PLLDivR - 1 ) << 8);
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
/**
* @brief Configures the LTDC clock Divider coming from PLLSAI.
*
- * @note The LTDC peripheral is only available with STM32F429xx/439xx Devices.
+ * @note The LTDC peripheral is only available with STM32F42xxx/43xxx/446xx/469xx/479xx Devices.
*
* @note This function must be called before enabling the PLLSAI.
*
* @param RCC_PLLSAIDivR: specifies the PLLSAI division factor for LTDC clock .
- * This parameter must be a number between 2 and 16.
* LTDC clock frequency = f(PLLSAI_R) / RCC_PLLSAIDivR
+ * This parameter can be one of the following values:
+ * @arg RCC_PLLSAIDivR_Div2: LTDC clock = f(PLLSAI_R)/2
+ * @arg RCC_PLLSAIDivR_Div4: LTDC clock = f(PLLSAI_R)/4
+ * @arg RCC_PLLSAIDivR_Div8: LTDC clock = f(PLLSAI_R)/8
+ * @arg RCC_PLLSAIDivR_Div16: LTDC clock = f(PLLSAI_R)/16
*
* @retval None
*/
@@ -1462,6 +1950,97 @@ void RCC_LTDCCLKDivConfig(uint32_t RCC_PLLSAIDivR)
RCC->DCKCFGR = tmpreg;
}
+#if defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief Configures the DFSDM clock source (DFSDMCLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDMCLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDMCLKSource_APB: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDMCLKSource_SYS: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM1CLKConfig(uint32_t RCC_DFSDMCLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDM1CLK_SOURCE(RCC_DFSDMCLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDM-SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1SEL;
+
+ /* Set CKDFSDM-SEL bit according to RCC_DFSDMCLKSource value */
+ tmpreg |= (RCC_DFSDMCLKSource << 31) ;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+/**
+ * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDM1ACLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM1ACLKConfig(uint32_t RCC_DFSDM1ACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDMACLK_SOURCE(RCC_DFSDM1ACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDMA SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
+
+ /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
+ tmpreg |= RCC_DFSDM1ACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Configures the DFSDM Audio clock source (DFSDMACLK).
+ * @note This function must be called before enabling the DFSDM APB clock.
+ * @param RCC_DFSDM2ACLKSource: specifies the DFSDM clock source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1: APB clock used as DFSDM clock source.
+ * @arg RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2: System clock used as DFSDM clock source.
+ *
+ * @retval None
+ */
+void RCC_DFSDM2ACLKConfig(uint32_t RCC_DFSDMACLKSource)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_RCC_DFSDMCLK_SOURCE(RCC_DFSDMACLKSource));
+
+ tmpreg = RCC->DCKCFGR;
+
+ /* Clear CKDFSDMA SEL bit */
+ tmpreg &= ~RCC_DCKCFGR_CKDFSDM1ASEL;
+
+ /* Set CKDFSDM-SEL bt according to RCC_DFSDMCLKSource value */
+ tmpreg |= RCC_DFSDMACLKSource;
+
+ /* Store the new value */
+ RCC->DCKCFGR = tmpreg;
+}
+#endif /* STM32F413_423xx */
+#endif /* STM32F412xG || STM32F413_423xx */
+
/**
* @brief Configures the Timers clocks prescalers selection.
*
@@ -1486,7 +2065,6 @@ void RCC_TIMCLKPresConfig(uint32_t RCC_TIMCLKPrescaler)
assert_param(IS_RCC_TIMCLK_PRESCALER(RCC_TIMCLKPrescaler));
*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = RCC_TIMCLKPrescaler;
-
}
/**
@@ -1571,14 +2149,16 @@ void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
}
}
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/**
* @brief Enables or disables the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1598,6 +2178,7 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
RCC->AHB3ENR &= ~RCC_AHB3Periph;
}
}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/**
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
@@ -1615,9 +2196,11 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
* @arg RCC_APB1Periph_TIM12: TIM12 clock
* @arg RCC_APB1Periph_TIM13: TIM13 clock
* @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
* @arg RCC_APB1Periph_WWDG: WWDG clock
* @arg RCC_APB1Periph_SPI2: SPI2 clock
* @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
* @arg RCC_APB1Periph_USART2: USART2 clock
* @arg RCC_APB1Periph_USART3: USART3 clock
* @arg RCC_APB1Periph_UART4: UART4 clock
@@ -1625,8 +2208,10 @@ void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
* @arg RCC_APB1Periph_I2C1: I2C1 clock
* @arg RCC_APB1Periph_I2C2: I2C2 clock
* @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
* @arg RCC_APB1Periph_CAN1: CAN1 clock
* @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
* @arg RCC_APB1Periph_PWR: PWR clock
* @arg RCC_APB1Periph_DAC: DAC clock
* @arg RCC_APB1Periph_UART7: UART7 clock
@@ -1669,13 +2254,20 @@ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
* @arg RCC_APB2Periph_SPI1: SPI1 clock
* @arg RCC_APB2Periph_SPI4: SPI4 clock
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+ * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
* @arg RCC_APB2Periph_TIM9: TIM9 clock
* @arg RCC_APB2Periph_TIM10: TIM10 clock
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1717,7 +2309,7 @@ void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
* @arg RCC_AHB1Periph_DMA2D: DMA2D clock (STM32F429xx/439xx devices)
* @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
* @arg RCC_AHB1Periph_OTG_HS: USB OTG HS clock
- *
+ * @arg RCC_AHB1Periph_RNG: RNG clock for STM32F410xx devices
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1745,7 +2337,7 @@ void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
* @arg RCC_AHB2Periph_DCMI: DCMI clock
* @arg RCC_AHB2Periph_CRYP: CRYP clock
* @arg RCC_AHB2Periph_HASH: HASH clock
- * @arg RCC_AHB2Periph_RNG: RNG clock
+ * @arg RCC_AHB2Periph_RNG: RNG clock for STM32F40_41xxx/STM32F412xG/STM32F413_423xx/STM32F427_437xx/STM32F429_439xx/STM32F469_479xx devices
* @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
@@ -1767,11 +2359,13 @@ void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
}
}
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/**
* @brief Forces or releases AHB3 peripheral reset.
* @param RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * or RCC_AHB3Periph_FMC (STM32F42xxx/43xxx devices)
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG, STM32F413_423xx and STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F446xx/STM32F469_479xx devices)
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1791,6 +2385,7 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
RCC->AHB3RSTR &= ~RCC_AHB3Periph;
}
}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/**
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
@@ -1805,9 +2400,11 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
* @arg RCC_APB1Periph_TIM12: TIM12 clock
* @arg RCC_APB1Periph_TIM13: TIM13 clock
* @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
* @arg RCC_APB1Periph_WWDG: WWDG clock
* @arg RCC_APB1Periph_SPI2: SPI2 clock
* @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
* @arg RCC_APB1Periph_USART2: USART2 clock
* @arg RCC_APB1Periph_USART3: USART3 clock
* @arg RCC_APB1Periph_UART4: UART4 clock
@@ -1815,8 +2412,10 @@ void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
* @arg RCC_APB1Periph_I2C1: I2C1 clock
* @arg RCC_APB1Periph_I2C2: I2C2 clock
* @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1:FMPI2C1 clock
* @arg RCC_APB1Periph_CAN1: CAN1 clock
* @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock(STM32F446xx devices)
* @arg RCC_APB1Periph_PWR: PWR clock
* @arg RCC_APB1Periph_DAC: DAC clock
* @arg RCC_APB1Periph_UART7: UART7 clock
@@ -1860,8 +2459,14 @@ void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
* @param NewState: new state of the specified peripheral reset.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1962,6 +2567,7 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
}
}
+#if defined(STM32F40_41xxx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
/**
* @brief Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
@@ -1969,8 +2575,9 @@ void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewSt
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @param RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
- * This parameter must be: RCC_AHB3Periph_FSMC
- * or RCC_AHB3Periph_FMC (STM32F429x/439x devices)
+ * This parameter must be:
+ * - RCC_AHB3Periph_FSMC or RCC_AHB3Periph_FMC (STM32F412xG/STM32F413_423xx/STM32F429x/439x devices)
+ * - RCC_AHB3Periph_QSPI (STM32F412xG/STM32F413_423xx/STM32F446xx/STM32F469_479xx devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -1989,6 +2596,7 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt
RCC->AHB3LPENR &= ~RCC_AHB3Periph;
}
}
+#endif /* STM32F40_41xxx || STM32F412xG || STM32F413_423xx || STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
/**
* @brief Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
@@ -2007,9 +2615,11 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt
* @arg RCC_APB1Periph_TIM12: TIM12 clock
* @arg RCC_APB1Periph_TIM13: TIM13 clock
* @arg RCC_APB1Periph_TIM14: TIM14 clock
+ * @arg RCC_APB1Periph_LPTIM1: LPTIM1 clock (STM32F410xx and STM32F413_423xx devices)
* @arg RCC_APB1Periph_WWDG: WWDG clock
* @arg RCC_APB1Periph_SPI2: SPI2 clock
* @arg RCC_APB1Periph_SPI3: SPI3 clock
+ * @arg RCC_APB1Periph_SPDIF: SPDIF RX clock (STM32F446xx devices)
* @arg RCC_APB1Periph_USART2: USART2 clock
* @arg RCC_APB1Periph_USART3: USART3 clock
* @arg RCC_APB1Periph_UART4: UART4 clock
@@ -2017,8 +2627,10 @@ void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewSt
* @arg RCC_APB1Periph_I2C1: I2C1 clock
* @arg RCC_APB1Periph_I2C2: I2C2 clock
* @arg RCC_APB1Periph_I2C3: I2C3 clock
+ * @arg RCC_APB1Periph_FMPI2C1: FMPI2C1 clock
* @arg RCC_APB1Periph_CAN1: CAN1 clock
* @arg RCC_APB1Periph_CAN2: CAN2 clock
+ * @arg RCC_APB1Periph_CEC: CEC clock (STM32F446xx devices)
* @arg RCC_APB1Periph_PWR: PWR clock
* @arg RCC_APB1Periph_DAC: DAC clock
* @arg RCC_APB1Periph_UART7: UART7 clock
@@ -2061,13 +2673,20 @@ void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewSt
* @arg RCC_APB2Periph_SPI1: SPI1 clock
* @arg RCC_APB2Periph_SPI4: SPI4 clock
* @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+ * @arg RCC_APB2Periph_EXTIT: EXTIIT clock
* @arg RCC_APB2Periph_TIM9: TIM9 clock
* @arg RCC_APB2Periph_TIM10: TIM10 clock
* @arg RCC_APB2Periph_TIM11: TIM11 clock
* @arg RCC_APB2Periph_SPI5: SPI5 clock
* @arg RCC_APB2Periph_SPI6: SPI6 clock
- * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx devices)
- * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_SAI1: SAI1 clock (STM32F42xxx/43xxx/446xx/469xx/479xx/413_423xx devices)
+ * @arg RCC_APB2Periph_SAI2: SAI2 clock (STM32F446xx devices)
+ * @arg RCC_APB2Periph_LTDC: LTDC clock (STM32F429xx/439xx devices)
+ * @arg RCC_APB2Periph_DSI: DSI clock (STM32F469_479xx devices)
+ * @arg RCC_APB2Periph_DFSDM1: DFSDM Clock (STM32F412xG and STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_DFSDM2: DFSDM2 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART9: UART9 Clock (STM32F413_423xx Devices)
+ * @arg RCC_APB2Periph_UART10: UART10 Clock (STM32F413_423xx Devices)
* @param NewState: new state of the specified peripheral clock.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -2089,19 +2708,19 @@ void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewSt
/**
* @brief Configures the External Low Speed oscillator mode (LSE mode).
- * @note This mode is only available for STM32F411xx devices.
+ * @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469_479xx devices.
* @param Mode: specifies the LSE mode.
* This parameter can be one of the following values:
* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode.
* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode.
* @retval None
*/
-void RCC_LSEModeConfig(uint8_t Mode)
+void RCC_LSEModeConfig(uint8_t RCC_Mode)
{
/* Check the parameters */
- assert_param(IS_RCC_LSE_MODE(Mode));
+ assert_param(IS_RCC_LSE_MODE(RCC_Mode));
- if(Mode == RCC_LSE_HIGHDRIVE_MODE)
+ if(RCC_Mode == RCC_LSE_HIGHDRIVE_MODE)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
}
@@ -2111,10 +2730,276 @@ void RCC_LSEModeConfig(uint8_t Mode)
}
}
+#if defined(STM32F410xx) || defined(STM32F413_423xx)
+/**
+ * @brief Configures the LPTIM1 clock Source.
+ * @note This feature is only available for STM32F410xx devices.
+ * @param RCC_ClockSource: specifies the LPTIM1 clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_LPTIM1CLKSOURCE_PCLK: LPTIM1 clock from APB1 selected.
+ * @arg RCC_LPTIM1CLKSOURCE_HSI: LPTIM1 clock from HSI selected.
+ * @arg RCC_LPTIM1CLKSOURCE_LSI: LPTIM1 clock from LSI selected.
+ * @arg RCC_LPTIM1CLKSOURCE_LSE: LPTIM1 clock from LSE selected.
+ * @retval None
+ */
+void RCC_LPTIM1ClockSourceConfig(uint32_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_LPTIM1_CLOCKSOURCE(RCC_ClockSource));
+
+ /* Clear LPTIM1 clock source selection source bits */
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_LPTIM1SEL;
+ /* Set new LPTIM1 clock source */
+ RCC->DCKCFGR2 |= RCC_ClockSource;
+}
+#endif /* STM32F410xx || STM32F413_423xx */
+
+#if defined(STM32F469_479xx)
+/**
+ * @brief Configures the DSI clock Source.
+ * @note This feature is only available for STM32F469_479xx devices.
+ * @param RCC_ClockSource: specifies the DSI clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_DSICLKSource_PHY: DSI-PHY used as DSI byte lane clock source (usual case).
+ * @arg RCC_DSICLKSource_PLLR: PLL_R used as DSI byte lane clock source, used in case DSI PLL and DSI-PHY are off (low power mode).
+ * @retval None
+ */
+void RCC_DSIClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_DSI_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_DSICLKSource_PLLR)
+ {
+ SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL);
+ }
+}
+#endif /* STM32F469_479xx */
+
+#if defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
+/**
+ * @brief Configures the 48MHz clock Source.
+ * @note This feature is only available for STM32F446xx/STM32F469_479xx devices.
+ * @param RCC_ClockSource: specifies the 48MHz clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_48MHZCLKSource_PLL: 48MHz from PLL selected.
+ * @arg RCC_48MHZCLKSource_PLLSAI: 48MHz from PLLSAI selected.
+ * @arg RCC_CK48CLKSOURCE_PLLI2SQ : 48MHz from PLLI2SQ
+ * @retval None
+ */
+void RCC_48MHzClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_48MHZ_CLOCKSOURCE(RCC_ClockSource));
+#if defined(STM32F469_479xx)
+ if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
+ {
+ SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL);
+ }
+#elif defined(STM32F446xx)
+ if(RCC_ClockSource == RCC_48MHZCLKSource_PLLSAI)
+ {
+ SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
+ }
+#elif defined(STM32F412xG) || defined(STM32F413_423xx)
+ if(RCC_ClockSource == RCC_CK48CLKSOURCE_PLLI2SQ)
+ {
+ SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL);
+ }
+#else
+#endif /* STM32F469_479xx */
+}
+
+/**
+ * @brief Configures the SDIO clock Source.
+ * @note This feature is only available for STM32F469_479xx/STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the SDIO clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SDIOCLKSource_48MHZ: 48MHz clock selected.
+ * @arg RCC_SDIOCLKSource_SYSCLK: system clock selected.
+ * @retval None
+ */
+void RCC_SDIOClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SDIO_CLOCKSOURCE(RCC_ClockSource));
+#if defined(STM32F469_479xx)
+ if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
+ {
+ SET_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL);
+ }
+#elif defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+ if(RCC_ClockSource == RCC_SDIOCLKSource_SYSCLK)
+ {
+ SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL);
+ }
+#else
+#endif /* STM32F469_479xx */
+}
+#endif /* STM32F412xG || STM32F413_423xx || STM32F446xx || STM32F469_479xx */
+
+#if defined(STM32F446xx)
+/**
+ * @brief Enables or disables the AHB1 clock gating for the specified IPs.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_AHB1ClockGating: specifies the AHB1 clock gating.
+ * This parameter can be any combination of the following values:
+ * @arg RCC_AHB1ClockGating_APB1Bridge: AHB1 to APB1 clock
+ * @arg RCC_AHB1ClockGating_APB2Bridge: AHB1 to APB2 clock
+ * @arg RCC_AHB1ClockGating_CM4DBG: Cortex M4 ETM clock
+ * @arg RCC_AHB1ClockGating_SPARE: Spare clock
+ * @arg RCC_AHB1ClockGating_SRAM: SRAM controller clock
+ * @arg RCC_AHB1ClockGating_FLITF: Flash interface clock
+ * @arg RCC_AHB1ClockGating_RCC: RCC clock
+ * @param NewState: new state of the specified peripheral clock.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_AHB1ClockGatingCmd(uint32_t RCC_AHB1ClockGating, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_AHB1_CLOCKGATING(RCC_AHB1ClockGating));
+
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ RCC->CKGATENR &= ~RCC_AHB1ClockGating;
+ }
+ else
+ {
+ RCC->CKGATENR |= RCC_AHB1ClockGating;
+ }
+}
+
+/**
+ * @brief Configures the SPDIFRX clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the SPDIFRX clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_SPDIFRXCLKSource_PLLR: SPDIFRX clock from PLL_R selected.
+ * @arg RCC_SPDIFRXCLKSource_PLLI2SP: SPDIFRX clock from PLLI2S_P selected.
+ * @retval None
+ */
+void RCC_SPDIFRXClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_SPDIFRX_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_SPDIFRXCLKSource_PLLI2SP)
+ {
+ SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL);
+ }
+}
+
+/**
+ * @brief Configures the CEC clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the CEC clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_CECCLKSource_HSIDiv488: CEC clock from HSI/488 selected.
+ * @arg RCC_CECCLKSource_LSE: CEC clock from LSE selected.
+ * @retval None
+ */
+void RCC_CECClockSourceConfig(uint8_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_CEC_CLOCKSOURCE(RCC_ClockSource));
+
+ if(RCC_ClockSource == RCC_CECCLKSource_LSE)
+ {
+ SET_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
+ }
+ else
+ {
+ CLEAR_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL);
+ }
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configures the FMPI2C1 clock Source.
+ * @note This feature is only available for STM32F446xx devices.
+ * @param RCC_ClockSource: specifies the FMPI2C1 clock Source.
+ * This parameter can be one of the following values:
+ * @arg RCC_FMPI2C1CLKSource_APB1: FMPI2C1 clock from APB1 selected.
+ * @arg RCC_FMPI2C1CLKSource_SYSCLK: FMPI2C1 clock from Sytem clock selected.
+ * @arg RCC_FMPI2C1CLKSource_HSI: FMPI2C1 clock from HSI selected.
+ * @retval None
+ */
+void RCC_FMPI2C1ClockSourceConfig(uint32_t RCC_ClockSource)
+{
+ /* Check the parameters */
+ assert_param(IS_RCC_FMPI2C1_CLOCKSOURCE(RCC_ClockSource));
+
+ /* Clear FMPI2C1 clock source selection source bits */
+ RCC->DCKCFGR2 &= ~RCC_DCKCFGR2_FMPI2C1SEL;
+ /* Set new FMPI2C1 clock source */
+ RCC->DCKCFGR2 |= RCC_ClockSource;
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
/**
* @}
*/
+#if defined(STM32F410xx)
+/**
+ * @brief Enables or disables the MCO1.
+ * @param NewState: new state of the MCO1.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_MCO1Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = (uint32_t)NewState;
+}
+
+/**
+ * @brief Enables or disables the MCO2.
+ * @param NewState: new state of the MCO2.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void RCC_MCO2Cmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ *(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = (uint32_t)NewState;
+}
+#endif /* STM32F410xx */
+
/** @defgroup RCC_Group4 Interrupts and flags management functions
* @brief Interrupts and flags management functions
*
@@ -2137,7 +3022,7 @@ void RCC_LSEModeConfig(uint8_t Mode)
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
* @param NewState: new state of the specified RCC interrupts.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -2167,7 +3052,7 @@ void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
* @arg RCC_FLAG_PLLRDY: main PLL clock ready
* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
- * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx devices)
+ * @arg RCC_FLAG_PLLSAIRDY: PLLSAI clock ready (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
@@ -2239,8 +3124,8 @@ void RCC_ClearFlag(void)
* @arg RCC_IT_HSIRDY: HSI ready interrupt
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx devices)
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI clock ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
* @arg RCC_IT_CSS: Clock Security System interrupt
* @retval The new state of RCC_IT (SET or RESET).
*/
@@ -2274,7 +3159,7 @@ ITStatus RCC_GetITStatus(uint8_t RCC_IT)
* @arg RCC_IT_HSERDY: HSE ready interrupt
* @arg RCC_IT_PLLRDY: main PLL ready interrupt
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
- * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx devices)
+ * @arg RCC_IT_PLLSAIRDY: PLLSAI ready interrupt (only for STM32F42xxx/43xxx/446xx/469xx/479xx devices)
* @arg RCC_IT_CSS: Clock Security System interrupt
* @retval None
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
similarity index 93%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
index ed851c71d..02ed12413 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rng.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* + Initialization and Configuration
@@ -35,7 +35,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -64,7 +64,7 @@
* @brief RNG driver modules
* @{
*/
-
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@@ -98,11 +98,20 @@
*/
void RNG_DeInit(void)
{
+#if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
/* Enable RNG reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
/* Release RNG from reset state */
RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F469_479xx */
+#if defined(STM32F410xx)
+ /* Enable RNG reset state */
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, ENABLE);
+
+ /* Release RNG from reset state */
+ RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_RNG, DISABLE);
+#endif /* STM32F410xx*/
}
/**
@@ -154,7 +163,7 @@ void RNG_Cmd(FunctionalState NewState)
*
* @note Before to call this function you have to wait till DRDY (data ready)
* flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
- * @note Each time the the Random number data is read (using RNG_GetRandomNumber()
+ * @note Each time the Random number data is read (using RNG_GetRandomNumber()
* function), the RNG_FLAG_DRDY flag is automatically cleared.
* @note In the case of a seed error, the generation of random numbers is
* interrupted for as long as the SECS bit is '1'. If a number is
@@ -384,7 +393,7 @@ void RNG_ClearITPendingBit(uint8_t RNG_IT)
/**
* @}
*/
-
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
/**
* @}
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
index 4861ade1d..ea566ced6 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_rtc.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Real-Time Clock (RTC) peripheral:
* + Initialization
@@ -264,7 +264,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -305,7 +305,7 @@
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \
- RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
+ RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | RTC_FLAG_SHPF))
#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
#define SYNCHRO_TIMEOUT ((uint32_t) 0x00020000)
@@ -1892,10 +1892,10 @@ void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
* This parameter can be can be one of the following values:
* @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration period is 32s.
* @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration period is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibartion period is 8s.
+ * @arg RTC_SmoothCalibPeriod_8sec : The smooth calibration period is 8s.
* @param RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK puls every 2**11 pulses.
+ * @arg RTC_SmoothCalibPlusPulses_Set : Add one RTCCLK pulse every 2**11 pulses.
* @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
* @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
* This parameter can be one any value from 0 to 0x000001FF.
@@ -2092,7 +2092,7 @@ uint32_t RTC_GetTimeStampSubSecond(void)
/**
* @brief Configures the select Tamper pin edge.
* @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1.
+ * This parameter can be RTC_Tamper_1 or RTC_Tamper 2
* @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
* stimulates tamper event.
* This parameter can be one of the following values:
@@ -2123,7 +2123,7 @@ void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
/**
* @brief Enables or Disables the Tamper detection.
* @param RTC_Tamper: Selected tamper pin.
- * This parameter can be RTC_Tamper_1.
+ * This parameter can be RTC_Tamper_1 or RTC_Tamper_2
* @param NewState: new state of the tamper pin.
* This parameter can be: ENABLE or DISABLE.
* @retval None
@@ -2356,8 +2356,8 @@ uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
* @brief Selects the RTC Tamper Pin.
* @param RTC_TamperPin: specifies the RTC Tamper Pin.
* This parameter can be one of the following values:
- * @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
- * @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.
+ * @arg RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin.
+ * @arg RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin.
* @retval None
*/
void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
@@ -2588,6 +2588,7 @@ void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
* This parameter can be one of the following values:
* @arg RTC_FLAG_RECALPF: RECALPF event flag.
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
* @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
* @arg RTC_FLAG_TSF: Time Stamp event flag
* @arg RTC_FLAG_WUTF: WakeUp Timer flag
@@ -2630,6 +2631,7 @@ FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
* @param RTC_FLAG: specifies the RTC flag to clear.
* This parameter can be any combination of the following values:
* @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+ * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
* @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
* @arg RTC_FLAG_TSF: Time Stamp event flag
* @arg RTC_FLAG_WUTF: WakeUp Timer flag
@@ -2655,7 +2657,8 @@ void RTC_ClearFlag(uint32_t RTC_FLAG)
* @arg RTC_IT_WUT: WakeUp Timer interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
+ * @arg RTC_IT_TAMP2: Tamper 2 event interrupt
* @retval The new state of RTC_IT (SET or RESET).
*/
ITStatus RTC_GetITStatus(uint32_t RTC_IT)
@@ -2670,7 +2673,7 @@ ITStatus RTC_GetITStatus(uint32_t RTC_IT)
tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
/* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));
+ enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)) | (tmpreg & (RTC_IT >> 16)));
/* Get the Interrupt pending bit */
tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
@@ -2695,7 +2698,8 @@ ITStatus RTC_GetITStatus(uint32_t RTC_IT)
* @arg RTC_IT_WUT: WakeUp Timer interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
+ * @arg RTC_IT_TAMP1: Tamper 1 event interrupt
+ * @arg RTC_IT_TAMP2: Tamper 2 event interrupt
* @retval None
*/
void RTC_ClearITPendingBit(uint32_t RTC_IT)
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c
similarity index 92%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c
index d05b519ec..85ee039e8 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sai.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sai.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI):
* + Initialization and Configuration
@@ -52,7 +52,7 @@
completely independent. The Clock generator is configured using RCC_SAIBlockACLKConfig() and
RCC_SAIBlockBCLKConfig() functions.
- (#) Each SAI Block A or B can be configured separetely :
+ (#) Each SAI Block A or B can be configured separately :
(++) Program the Master clock divider, Audio mode, Protocol, Data Length, Clock Strobing Edge,
Synchronous mode, Output drive and FIFO Thresold using SAI_Init() function.
In case of master mode, program the Master clock divider (MCKDIV) using
@@ -105,7 +105,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -134,6 +134,9 @@
* @brief SAI driver modules
* @{
*/
+#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || \
+ defined (STM32F401xx) || defined (STM32F411xE) || defined (STM32F446xx) || defined (STM32F469_479xx) || \
+ defined (STM32F413_423xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -183,11 +186,26 @@ void SAI_DeInit(SAI_TypeDef* SAIx)
{
/* Check the parameters */
assert_param(IS_SAI_PERIPH(SAIx));
-
- /* Enable SAI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE);
- /* Release SAI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE);
+
+ if(SAIx == SAI1)
+ {
+ /* Enable SAI1 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, ENABLE);
+ /* Release SAI1 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI1, DISABLE);
+ }
+ else
+ {
+#if defined(STM32F446xx)
+ if(SAIx == SAI2)
+ {
+ /* Enable SAI2 reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, ENABLE);
+ /* Release SAI2 from reset state */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_SAI2, DISABLE);
+ }
+#endif /* STM32F446xx */
+ }
}
/**
@@ -216,6 +234,7 @@ void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct)
assert_param(IS_SAI_BLOCK_FIRST_BIT(SAI_InitStruct->SAI_FirstBit));
assert_param(IS_SAI_BLOCK_CLOCK_STROBING(SAI_InitStruct->SAI_ClockStrobing));
assert_param(IS_SAI_BLOCK_SYNCHRO(SAI_InitStruct->SAI_Synchro));
+ assert_param(IS_SAI_BLOCK_SYNCEXT(SAI_InitStruct->SAI_SynchroExt));
assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(SAI_InitStruct->SAI_OUTDRIV));
assert_param(IS_SAI_BLOCK_NODIVIDER(SAI_InitStruct->SAI_NoDivider));
assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(SAI_InitStruct->SAI_MasterDivider));
@@ -240,8 +259,8 @@ void SAI_Init(SAI_Block_TypeDef* SAI_Block_x, SAI_InitTypeDef* SAI_InitStruct)
tmpreg |= (uint32_t)(SAI_InitStruct->SAI_AudioMode | SAI_InitStruct->SAI_Protocol |
SAI_InitStruct->SAI_DataSize | SAI_InitStruct->SAI_FirstBit |
SAI_InitStruct->SAI_ClockStrobing | SAI_InitStruct->SAI_Synchro |
- SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider |
- (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20));
+ SAI_InitStruct->SAI_OUTDRIV | SAI_InitStruct->SAI_NoDivider |
+ SAI_InitStruct->SAI_SynchroExt | (uint32_t)((SAI_InitStruct->SAI_MasterDivider) << 20));
/* Write to SAI_Block_x CR1 */
SAI_Block_x->CR1 = tmpreg;
@@ -371,6 +390,8 @@ void SAI_StructInit(SAI_InitTypeDef* SAI_InitStruct)
SAI_InitStruct->SAI_ClockStrobing = SAI_ClockStrobing_FallingEdge;
/* Initialize the SAI_Synchro member */
SAI_InitStruct->SAI_Synchro = SAI_Asynchronous;
+ /* Initialize the SAI_SynchroExt member */
+ SAI_InitStruct->SAI_SynchroExt = SAI_SyncExt_Disable;
/* Initialize the SAI_OUTDRIV member */
SAI_InitStruct->SAI_OUTDRIV = SAI_OutputDrive_Disabled;
/* Initialize the SAI_NoDivider member */
@@ -470,14 +491,14 @@ void SAI_MonoModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mono_StreoM
}
/**
- * @brief Configures the TRIState managment on data line for the selected SAI block.
+ * @brief Configures the TRIState management on data line for the selected SAI block.
*
* @note This function has a meaning only when the SAI block is configured in transmitter
*
* @param SAI_Block_x: where x can be A or B to select the SAI Block peripheral.
* @param SAI_TRIState: specifies the SAI block TRIState management.
* This parameter can be one of the following values:
- * @arg SAI_Output_NotReleased : SD output line is still drived by the SAI.
+ * @arg SAI_Output_NotReleased : SD output line is still driven by the SAI.
* @arg SAI_Output_Released : SD output line is released (HI-Z)
* @retval None
*/
@@ -504,9 +525,9 @@ void SAI_TRIStateConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_TRIState)
* This parameter can be one of the following values:
* @arg SAI_NoCompanding : no companding algorithm set
* @arg SAI_ULaw_1CPL_Companding : Set U law (algorithm 1's complement representation)
- * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement repesentation)
+ * @arg SAI_ALaw_1CPL_Companding : Set A law (algorithm 1's complement representation)
* @arg SAI_ULaw_2CPL_Companding : Set U law (algorithm 2's complement representation)
- * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement repesentation)
+ * @arg SAI_ALaw_2CPL_Companding : Set A law (algorithm 2's complement representation)
* @retval None
*/
void SAI_CompandingModeConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_CompandingMode)
@@ -597,6 +618,72 @@ void SAI_MuteFrameCounterConfig(SAI_Block_TypeDef* SAI_Block_x, uint32_t SAI_Mut
/* Set new Mute value */
SAI_Block_x->CR2 |= (SAI_MuteCounter << 7);
}
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469_479xx) || defined(STM32F413_423xx) || defined(STM32F446xx)
+/**
+ * @brief Configure SAI Block synchronization mode
+ * @param SAI_InitStruct: pointer to a SAI_InitTypeDef structure that
+ * contains the configuration information for the specified SAI Block peripheral.
+ * @param SAIx: To select the SAIx peripheral, where x can be the different instances
+ * @retval None
+ */
+void SAI_BlockSynchroConfig(SAI_InitTypeDef* SAI_InitStruct, SAI_TypeDef* SAIx)
+{
+ uint32_t tmpregisterGCR = 0U;
+
+#if defined(STM32F446xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(SAI_InitStruct->SAI_SynchroExt)
+ {
+ case SAI_SyncExt_Disable :
+ tmpregisterGCR = 0U;
+ break;
+ case SAI_SyncExt_OutBlockA_Enable :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SyncExt_OutBlockB_Enable :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ default:
+ break;
+ }
+
+ if(((SAI_InitStruct->SAI_Synchro) == SAI_Synchronous_Ext) && (SAIx == SAI1))
+ {
+ tmpregisterGCR |= SAI_GCR_SYNCIN_0;
+ }
+
+ if(SAIx == SAI1)
+ {
+ SAI1->GCR = tmpregisterGCR;
+ }
+ else
+ {
+ SAI2->GCR = tmpregisterGCR;
+ }
+
+#endif /* STM32F446xx */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+ defined(STM32F469_479xx) || defined(STM32F413_423xx)
+ /* This setting must be done with both audio block (A & B) disabled */
+ switch(SAI_InitStruct->SAI_SynchroExt)
+ {
+ case SAI_SyncExt_Disable :
+ tmpregisterGCR = 0U;
+ break;
+ case SAI_SyncExt_OutBlockA_Enable :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_0;
+ break;
+ case SAI_SyncExt_OutBlockB_Enable :
+ tmpregisterGCR = SAI_GCR_SYNCOUT_1;
+ break;
+ default:
+ break;
+ }
+ SAI1->GCR = tmpregisterGCR;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx */
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469_479xx || STM32F413_423xx || STM32F446xx */
/**
* @brief Reinitialize the FIFO pointer
@@ -1067,6 +1154,7 @@ uint32_t SAI_GetFIFOStatus(SAI_Block_TypeDef* SAI_Block_x)
/**
* @}
*/
+#endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE || STM32F446xx || STM32F469_479xx */
/**
* @}
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
index ca1c89585..ec4faff45 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_sdio.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Secure digital input/output interface (SDIO)
* peripheral:
@@ -135,7 +135,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
index fa7030708..523e220b5 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_spi.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Serial peripheral interface (SPI):
* + Initialization and Configuration
@@ -93,7 +93,7 @@
(#) Configure SPIx in I2S mode (I2S_Init() function) as described above.
- (#) Call the I2S_FullDuplexConfig() function using the same strucutre passed to
+ (#) Call the I2S_FullDuplexConfig() function using the same structure passed to
I2S_Init() function.
(#) Call I2S_Cmd() for SPIx then for its extended block.
@@ -138,7 +138,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -341,7 +341,7 @@ void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
*
* @note if an external clock is used as source clock for the I2S, then the define
* I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
- * to the value of the the source clock frequency (in Hz).
+ * to the value of the source clock frequency (in Hz).
*
* @retval None
*/
@@ -475,8 +475,16 @@ void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
(uint16_t)I2S_InitStruct->I2S_CPOL))));
+#if defined(SPI_I2SCFGR_ASTRTEN)
+ if((I2S_InitStruct->I2S_Standard == I2S_Standard_PCMShort) || (I2S_InitStruct->I2S_Standard == I2S_Standard_PCMLong))
+ {
+ /* Write to SPIx I2SCFGR */
+ SPIx->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN;
+ }
+#else
/* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
+ SPIx->I2SCFGR = tmpreg ;
+#endif
}
/**
@@ -725,7 +733,7 @@ void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
* used for the master I2S peripheral. In this case, if the master is
* configured as transmitter, the slave will be receiver and vice versa.
* Or you can force a different mode by modifying the field I2S_Mode to the
- * value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.
+ * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration.
*
* @note The I2S full duplex extension can be configured in slave mode only.
*
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
similarity index 53%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
index 29f472dfa..240c9fc88 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_syscfg.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the SYSCFG peripheral.
*
@verbatim
@@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -68,20 +68,25 @@
#define MEMRMP_OFFSET SYSCFG_OFFSET
#define UFB_MODE_BitNumber ((uint8_t)0x8)
#define UFB_MODE_BB (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (UFB_MODE_BitNumber * 4))
-
-
+
/* --- PMC Register ---*/
/* Alias word address of MII_RMII_SEL bit */
#define PMC_OFFSET (SYSCFG_OFFSET + 0x04)
#define MII_RMII_SEL_BitNumber ((uint8_t)0x17)
#define PMC_MII_RMII_SEL_BB (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4))
-
+
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20)
#define CMP_PD_BitNumber ((uint8_t)0x00)
#define CMPCR_CMP_PD_BB (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4))
+/* --- MCHDLYCR Register ---*/
+/* Alias word address of BSCKSEL bit */
+#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30)
+#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
+#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32) + (BSCKSEL_BIT_NUMBER * 4))
+
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -109,8 +114,9 @@ void SYSCFG_DeInit(void)
* This parameter can be one of the following values:
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx and STM32F415xx/417xx devices.
- * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
+ * @arg SYSCFG_MemoryRemap_FSMC: FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F405xx/407xx, STM32F415xx/417xx and STM32F413_423xx devices.
+ * @arg SYSCFG_MemoryRemap_FMC: FMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
+ * @arg SYSCFG_MemoryRemap_ExtMEM: External Memory mapped at 0x00000000 for STM32F446xx/STM32F469_479xx devices.
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM (112kB) mapped at 0x00000000
* @arg SYSCFG_MemoryRemap_SDRAM: FMC (External SDRAM) mapped at 0x00000000 for STM32F42xxx/43xxx devices.
* @retval None
@@ -124,11 +130,11 @@ void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
}
/**
- * @brief Enables or disables the Interal FLASH Bank Swapping.
+ * @brief Enables or disables the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F42xxx/43xxx devices.
*
- * @param NewState: new state of Interal FLASH Bank swapping.
+ * @param NewState: new state of Internal FLASH Bank swapping.
* This parameter can be one of the following values:
* @arg ENABLE: Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
* and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
@@ -225,6 +231,281 @@ FlagStatus SYSCFG_GetCompensationCellStatus(void)
return bitstatus;
}
+#if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
+/**
+ * @brief Connects the selected parameter to the break input of TIM1.
+ * @note The selected configuration is locked and can be unlocked by system reset
+ * @param SYSCFG_Break: selects the configuration to be connected to break
+ * input of TIM1
+ * This parameter can be any combination of the following values:
+ * @arg SYSCFG_Break_PVD: PVD interrupt is connected to the break input of TIM1/8.
+ * @arg SYSCFG_Break_HardFault: Lockup output of CortexM4 is connected to the break input of TIM1/8.
+ * @retval None
+ */
+void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
+{
+ /* Check the parameter */
+ assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
+
+ SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
+}
+#endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
+
+#if defined(STM32F413_423xx)
+/**
+ * @brief Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+ * @param source: BITSTREAM_CLOCK_DFSDM2.
+ * BITSTREAM_CLOCK_TIM2OC1.
+ * @retval None
+ */
+void DFSDM_BitstreamClock_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
+
+ SYSCFG->MCHDLYCR = (tmp|source);
+}
+
+/**
+ * @brief Disable Delay Clock for DFSDM1/2.
+ * @param MCHDLY: MCHDLY_CLOCK_DFSDM2.
+ * MCHDLY_CLOCK_DFSDM1.
+ * @retval None
+ */
+void DFSDM_DisableDelayClock(uint32_t MCHDLY)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ if(MCHDLY == MCHDLY_CLOCK_DFSDM2)
+ {
+ tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
+ }
+ else
+ {
+ tmp =tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
+ }
+
+ SYSCFG->MCHDLYCR = tmp;
+}
+
+/**
+ * @brief Enable Delay Clock for DFSDM1/2.
+ * @param MCHDLY: MCHDLY_CLOCK_DFSDM2.
+ * MCHDLY_CLOCK_DFSDM1.
+ * @retval None
+ */
+void DFSDM_EnableDelayClock(uint32_t MCHDLY)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = tmp & ~MCHDLY;
+
+ SYSCFG->MCHDLYCR = (tmp|MCHDLY);
+}
+
+/**
+ * @brief Select the source for CKin signals for DFSDM1/2.
+ * @param source: DFSDM2_CKIN_PAD.
+ * DFSDM2_CKIN_DM.
+ * DFSDM1_CKIN_PAD.
+ * DFSDM1_CKIN_DM.
+ * @retval None
+ */
+void DFSDM_ClockIn_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ if((source == DFSDM2_CKIN_PAD) || (source == DFSDM2_CKIN_DM))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
+ }
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Select the source for CKOut signals for DFSDM1/2.
+ * @param source: DFSDM2_CKOUT_DFSDM2.
+ * DFSDM2_CKOUT_M27.
+ * DFSDM1_CKOUT_DFSDM1.
+ * DFSDM1_CKOUT_M27.
+ * @retval None
+ */
+void DFSDM_ClockOut_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == DFSDM2_CKOUT_DFSDM2) || (source == DFSDM2_CKOUT_M27))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
+ }
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn0 signals for DFSDM1/2.
+ * @param source: DATAIN0_DFSDM2_PAD.
+ * DATAIN0_DFSDM2_DATAIN1.
+ * DATAIN0_DFSDM1_PAD.
+ * DATAIN0_DFSDM1_DATAIN1.
+ * @retval None
+ */
+void DFSDM_DataIn0_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == DATAIN0_DFSDM2_PAD)|| (source == DATAIN0_DFSDM2_DATAIN1))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
+ }
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn2 signals for DFSDM1/2.
+ * @param source: DATAIN2_DFSDM2_PAD.
+ * DATAIN2_DFSDM2_DATAIN3.
+ * DATAIN2_DFSDM1_PAD.
+ * DATAIN2_DFSDM1_DATAIN3.
+ * @retval None
+ */
+void DFSDM_DataIn2_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if((source == DATAIN2_DFSDM2_PAD)|| (source == DATAIN2_DFSDM2_DATAIN3))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
+ }
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn4 signals for DFSDM2.
+ * @param source: DATAIN4_DFSDM2_PAD.
+ * DATAIN4_DFSDM2_DATAIN5
+ * @retval None
+ */
+void DFSDM_DataIn4_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Select the source for DataIn6 signals for DFSDM2.
+ * @param source: DATAIN6_DFSDM2_PAD.
+ * DATAIN6_DFSDM2_DATAIN7.
+ * @retval None
+ */
+void DFSDM_DataIn6_SourceSelection(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Configure the distribution of the bitstream clock gated from TIM4.
+ * @param source: DFSDM1_CLKIN0_TIM4OC2
+ * DFSDM1_CLKIN2_TIM4OC2
+ * DFSDM1_CLKIN1_TIM4OC1
+ * DFSDM1_CLKIN3_TIM4OC1
+ * @retval None
+ */
+void DFSDM1_BitStreamClk_Config(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if ((source == DFSDM1_CLKIN0_TIM4OC2) || (source == DFSDM1_CLKIN2_TIM4OC2))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
+ }
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+/**
+ * @brief Configure the distribution of the bitstream clock gated from TIM3.
+ * @param source: DFSDM2_CLKIN0_TIM3OC4
+ * DFSDM2_CLKIN4_TIM3OC4
+ * DFSDM2_CLKIN1_TIM3OC3
+ * DFSDM2_CLKIN5_TIM3OC3
+ * DFSDM2_CLKIN2_TIM3OC2
+ * DFSDM2_CLKIN6_TIM3OC2
+ * DFSDM2_CLKIN3_TIM3OC1
+ * DFSDM2_CLKIN7_TIM3OC1
+ * @retval None
+ */
+void DFSDM2_BitStreamClk_Config(uint32_t source)
+{
+ uint32_t tmp = 0;
+
+ tmp = SYSCFG->MCHDLYCR;
+
+ if ((source == DFSDM2_CLKIN0_TIM3OC4) || (source == DFSDM2_CLKIN4_TIM3OC4))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
+ }
+ else if ((source == DFSDM2_CLKIN1_TIM3OC3) || (source == DFSDM2_CLKIN5_TIM3OC3))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
+
+ }else if ((source == DFSDM2_CLKIN2_TIM3OC2) || (source == DFSDM2_CLKIN6_TIM3OC2))
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
+ }
+ else
+ {
+ tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
+ }
+
+ SYSCFG->MCHDLYCR |= (source|tmp);
+}
+
+#endif /* STM32F413_423xx */
/**
* @}
*/
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
index 79bd26503..7c62e1ab0 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_tim.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the TIM peripheral:
* + TimeBase management
@@ -98,7 +98,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
@@ -327,7 +327,7 @@ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseIn
}
/* Generate an update event to reload the Prescaler
- and the repetition counter(only for TIM1 and TIM8) value immediatly */
+ and the repetition counter(only for TIM1 and TIM8) value immediately */
TIMx->EGR = TIM_PSCReloadMode_Immediate;
}
@@ -354,7 +354,7 @@ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
* This parameter can be one of the following values:
* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+ * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
* @retval None
*/
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
@@ -1864,7 +1864,7 @@ void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
(++) TIM Input Capture polarity: TIM_ICPolarity
(++) TIM Input Capture selection: TIM_ICSelection
(++) TIM Input Capture Prescaler: TIM_ICPrescaler
- (++) TIM Input CApture filter value: TIM_ICFilter
+ (++) TIM Input Capture filter value: TIM_ICFilter
(#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel
with the corresponding configuration and to measure only frequency
@@ -3158,7 +3158,7 @@ void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
* @param TIM_Remap: specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
- * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trogger output.
+ * @arg TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
* @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
* @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
* @arg TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
similarity index 99%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
index 275747875..d4ebc3f4c 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_usart.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Universal synchronous asynchronous receiver
* transmitter (USART):
@@ -71,7 +71,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
diff --git a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
similarity index 98%
rename from radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
rename to radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
index 5ddbee869..45bf1dda7 100644
--- a/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.4.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
+++ b/radio/src/thirdparty/STM32F4xx_DSP_StdPeriph_Lib_V1.8.0/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f4xx_wwdg.c
* @author MCD Application Team
- * @version V1.4.0
- * @date 04-August-2014
+ * @version V1.8.0
+ * @date 04-November-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Window watchdog (WWDG) peripheral:
* + Prescaler, Refresh window and Counter configuration
@@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2014 STMicroelectronics
+ * © COPYRIGHT 2016 STMicroelectronics
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.