Bsongis/horus xjt external module (#3566)
* [Horus] PXX and DSM2 in external module * [Taranis] Pulses driver refactoring (uses DMA also for PPM in external module and saves 800bytes RAM) * Cosmetics (Pulses driver splitted)
This commit is contained in:
Bertrand Songis
@@ -20,41 +20,64 @@
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#include "opentx.h"
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void setupPulses(unsigned int port);
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void setupPulsesPPM(unsigned int port);
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void setupPulsesPXX(unsigned int port);
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void intmoduleStop(void);
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void extmoduleStop(void);
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static void intmodulePxxStart( void ) ;
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static void intmodulePxxStop( void ) ;
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static void extmodulePxxStart( void ) ;
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static void extmodulePxxStop( void ) ;
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void intmoduleNoneStart(void);
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void intmodulePxxStart(void);
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void extmoduleNoneStart(void);
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void extmodulePpmStart(void);
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void extmodulePxxStart(void);
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#if defined(DSM2)
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static void extmoduleDsm2Start( void ) ;
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static void extmoduleDsm2Stop( void ) ;
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void extmoduleDsm2Start(void);
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#endif
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static void extmodulePpmStart( void ) ;
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static void extmodulePpmStop( void ) ;
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static void intmoduleNoneStart( void ) ;
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static void intmoduleNoneStop( void ) ;
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static void extmoduleNoneStart( void ) ;
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static void extmoduleNoneStop( void ) ;
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static void extmoduleCrossfireStart( void ) ;
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static void extmoduleCrossfireStop( void ) ;
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void extmoduleCrossfireStart(void);
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStart();
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else
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extmoduleNoneStart();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleStop();
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else
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extmoduleStop();
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}
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void init_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStart();
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}
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}
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void disable_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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void init_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStart() ;
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intmodulePxxStart();
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else
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extmodulePxxStart() ;
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extmodulePxxStart();
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}
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void disable_pxx(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmodulePxxStop() ;
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intmoduleStop();
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else
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extmodulePxxStop() ;
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extmoduleStop();
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}
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#if defined(DSM2)
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@@ -68,48 +91,11 @@ void init_dsm2(uint32_t port)
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void disable_dsm2(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmoduleDsm2Stop();
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extmoduleStop();
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}
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}
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#endif
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void init_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStart();
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}
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}
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void disable_ppm(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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extmodulePpmStop();
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}
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}
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void set_external_ppm_parameters(uint32_t idleTime, uint32_t delay, uint32_t positive)
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{
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EXTMODULE_TIMER->CCR2 = idleTime;
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EXTMODULE_TIMER->CCR1 = delay;
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EXTMODULE_TIMER->CCER = TIM_CCER_CC1E | (positive ? 0 : TIM_CCER_CC1P);
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}
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void init_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStart();
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else
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extmoduleNoneStart();
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}
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void disable_no_pulses(uint32_t port)
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{
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if (port == INTERNAL_MODULE)
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intmoduleNoneStop();
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else
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extmoduleNoneStop();
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}
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void init_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE) {
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@@ -119,184 +105,51 @@ void init_crossfire(uint32_t port)
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void disable_crossfire(uint32_t port)
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{
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if (port == EXTERNAL_MODULE)
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extmoduleCrossfireStop();
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if (port == EXTERNAL_MODULE) {
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extmoduleStop();
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}
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}
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static void intmoduleNoneStart()
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void intmoduleStop()
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{
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INTERNAL_MODULE_OFF();
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NVIC_DisableIRQ(INTMODULE_TIMER_CC_IRQn);
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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}
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void intmoduleNoneStart()
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{
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INTERNAL_MODULE_OFF();
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// Timer1, channel 3
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = INTMODULE_TX_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(INTMODULE_TX_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN) ; // Set high
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GPIO_SetBits(INTMODULE_TX_GPIO, INTMODULE_TX_GPIO_PIN); // Set high
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTMODULE_TIMER->ARR = 36000 ; // 18mS
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INTMODULE_TIMER->CCR2 = 32000 ; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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INTMODULE_TIMER->ARR = 36000; // 18mS
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INTMODULE_TIMER->CCR2 = 32000; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCMR2 = 0 ;
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INTMODULE_TIMER->EGR = 1 ; // Restart
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INTMODULE_TIMER->CCMR2 = 0;
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INTMODULE_TIMER->EGR = 1; // Restart
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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}
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static void intmoduleNoneStop()
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{
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NVIC_DisableIRQ(INTMODULE_TIMER_IRQn) ;
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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}
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#if !defined(SIMU)
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extern "C" void DMA2_Stream7_IRQHandler(void)
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{
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DEBUG_INTERRUPT(INT_DMA2S7);
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if(DMA_GetITStatus(INTMODULE_DMA_STREAM, DMA_IT_TCIF7)) {
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// TODO we could send the 8 next channels here (when needed)
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DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, DMA_IT_TCIF7);
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}
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}
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extern "C" void TIM1_CC_IRQHandler()
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{
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DEBUG_INTERRUPT(INT_TIM1CC);
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DEBUG_TIMER_SAMPLE(debugTimerIntPulses);
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DEBUG_TIMER_START(debugTimerIntPulsesDuration);
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INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
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setupPulses(INTERNAL_MODULE);
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if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
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DMA_InitTypeDef DMA_InitStructure;
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DMA_DeInit(INTMODULE_DMA_STREAM);
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DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL;
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DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&INTMODULE_USART->DR);
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DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
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DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)modulePulsesData[INTERNAL_MODULE].pxx.pulses;
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DMA_InitStructure.DMA_BufferSize = (uint8_t *)modulePulsesData[INTERNAL_MODULE].pxx.ptr - (uint8_t *)modulePulsesData[INTERNAL_MODULE].pxx.pulses;
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DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
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DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
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DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
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DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
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DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
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DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
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DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
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DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
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DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
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DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure);
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DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE);
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USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE);
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// DMA_ITConfig(INTMODULE_DMA_STREAM, DMA_IT_TC, ENABLE);
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}
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
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DEBUG_TIMER_STOP(debugTimerIntPulsesDuration);
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}
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#endif
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static void extmoduleNoneStart()
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{
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if (!IS_TRAINER_EXTERNAL_MODULE()) {
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EXTERNAL_MODULE_OFF();
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}
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GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, 0); // TODO : check if needed
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN) ; // Set high
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TIM_DeInit(EXTMODULE_TIMER);
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TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
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TIM_TimeBaseStructure.TIM_Prescaler = EXTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
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TIM_TimeBaseStructure.TIM_Period = 36000; // 18mS
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TIM_TimeBaseStructure.TIM_ClockDivision = 0;
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TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
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TIM_TimeBaseInit(EXTMODULE_TIMER, &TIM_TimeBaseStructure);
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// set CC2 compare to fire slightly before the Update
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TIM_SetCompare2(EXTMODULE_TIMER, 32000); // 16ms
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// enable CC2 interrupt
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TIM_ClearFlag(EXTMODULE_TIMER, TIM_FLAG_CC2);
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TIM_ITConfig(EXTMODULE_TIMER, TIM_IT_CC2, ENABLE);
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// start timer
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TIM_Cmd(EXTMODULE_TIMER, ENABLE);
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// enable interrupt and set it's priority
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NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
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}
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static void extmoduleNoneStop()
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{
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NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
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TIM_DeInit(EXTMODULE_TIMER);
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}
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static void extmoduleCrossfireStart()
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{
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EXTERNAL_MODULE_ON();
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT ;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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GPIO_SetBits(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PIN); // Set high
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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EXTMODULE_TIMER->ARR = 5000 ; // 2.5mS
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EXTMODULE_TIMER->CCR2 = 32000 ; // Update time
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EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
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EXTMODULE_TIMER->CCMR2 = 0 ;
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EXTMODULE_TIMER->EGR = 1 ; // Restart
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EXTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
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}
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static void extmoduleCrossfireStop()
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{
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NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
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EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
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EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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if (!IS_TRAINER_EXTERNAL_MODULE()) {
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EXTERNAL_MODULE_OFF();
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}
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7);
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}
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void intmodulePxxStart()
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@@ -306,7 +159,7 @@ void intmodulePxxStart()
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INTERNAL_MODULE_ON();
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setupPulsesPXX(INTERNAL_MODULE) ; // TODO not here!
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setupPulsesPXX(INTERNAL_MODULE);
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NVIC_InitStructure.NVIC_IRQChannel = INTMODULE_DMA_STREAM_IRQ;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
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@@ -340,270 +193,69 @@ void intmodulePxxStart()
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USART_Init(INTMODULE_USART, &USART_InitStructure);
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USART_Cmd(INTMODULE_USART, ENABLE);
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// open DMA------------------------------
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RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE); // Enable DMA1 clock
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// Timer
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
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INTMODULE_TIMER->ARR = 18000 ; // 9mS
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INTMODULE_TIMER->CCR2 = 15000 ; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E ;
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INTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN;
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INTMODULE_TIMER->ARR = 18000; // 9mS
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INTMODULE_TIMER->CCR2 = 15000; // Update time
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INTMODULE_TIMER->PSC = INTMODULE_TIMER_FREQ / 2000000 - 1; // 0.5uS (2Mhz)
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCER = TIM_CCER_CC3E;
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INTMODULE_TIMER->CCMR2 = 0 ;
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INTMODULE_TIMER->EGR = 1 ; // Restart
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INTMODULE_TIMER->CCMR2 = 0;
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INTMODULE_TIMER->EGR = 1; // Restart
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0 ; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
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NVIC_EnableIRQ(INTMODULE_TIMER_IRQn) ;
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NVIC_SetPriority(INTMODULE_TIMER_IRQn, 7);
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INTMODULE_TIMER->CCMR2 = TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0; // Toggle CC1 o/p
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INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // Clear flag
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INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE; // Enable this interrupt
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INTMODULE_TIMER->CR1 |= TIM_CR1_CEN;
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NVIC_EnableIRQ(INTMODULE_TIMER_CC_IRQn);
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NVIC_SetPriority(INTMODULE_TIMER_CC_IRQn, 7);
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}
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static void intmodulePxxStop()
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extern "C" void INTMODULE_DMA_STREAM_IRQHandler(void)
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{
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INTERNAL_MODULE_OFF();
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}
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void extmodulePxxStart()
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{
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EXTERNAL_MODULE_ON();
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setupPulsesPXX(EXTERNAL_MODULE);
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GPIO_InitTypeDef GPIO_InitStructure;
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GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF);
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GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
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GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
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GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
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GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
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GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
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GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
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|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
EXTMODULE_TIMER->ARR = 18000 ; // 9mS
|
||||
EXTMODULE_TIMER->CCR2 = 15000 ; // Update time
|
||||
EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
|
||||
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE ;
|
||||
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
|
||||
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
|
||||
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
|
||||
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
|
||||
EXTMODULE_TIMER->EGR = 1 ; // Restart
|
||||
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
|
||||
EXTMODULE_TIMER->DCR = 13;
|
||||
|
||||
// Enable the DMA channel here, DMA1 stream 5, channel 3 (TIM2_CH1)
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
|
||||
DMA1_Stream5->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
||||
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
||||
DMA1_Stream5->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
|
||||
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
|
||||
// DMA1_Stream5->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
|
||||
// DMA1_Stream5->NDTR = 100 ;
|
||||
DMA1_Stream5->CR |= DMA_SxCR_EN ; // Enable DMA
|
||||
|
||||
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
||||
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
|
||||
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn);
|
||||
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
||||
}
|
||||
|
||||
static void extmodulePxxStop()
|
||||
{
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
||||
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
||||
EXTERNAL_MODULE_OFF();
|
||||
DEBUG_INTERRUPT(INT_DMA2S7);
|
||||
if (DMA_GetITStatus(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC)) {
|
||||
// TODO we could send the 8 next channels here (when needed)
|
||||
DMA_ClearITPendingBit(INTMODULE_DMA_STREAM, INTMODULE_DMA_FLAG_TC);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(DSM2)
|
||||
static void extmoduleDsm2Start()
|
||||
extern "C" void INTMODULE_TIMER_CC_IRQHandler()
|
||||
{
|
||||
EXTERNAL_MODULE_ON();
|
||||
DEBUG_INTERRUPT(INT_TIM1CC);
|
||||
DEBUG_TIMER_SAMPLE(debugTimerIntPulses);
|
||||
DEBUG_TIMER_START(debugTimerIntPulsesDuration);
|
||||
INTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE; // stop this interrupt
|
||||
INTMODULE_TIMER->SR &= ~TIM_SR_CC2IF; // clear flag
|
||||
|
||||
setupPulsesDSM2(EXTERNAL_MODULE);
|
||||
setupPulses(INTERNAL_MODULE);
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF);
|
||||
GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
|
||||
if (s_current_protocol[INTERNAL_MODULE] == PROTO_PXX) {
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
DMA_DeInit(INTMODULE_DMA_STREAM);
|
||||
DMA_InitStructure.DMA_Channel = INTMODULE_DMA_CHANNEL;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = CONVERT_PTR_UINT(&INTMODULE_USART->DR);
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
|
||||
DMA_InitStructure.DMA_Memory0BaseAddr = CONVERT_PTR_UINT(modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses);
|
||||
DMA_InitStructure.DMA_BufferSize = (uint8_t *)modulePulsesData[INTERNAL_MODULE].pxx_uart.ptr - (uint8_t *)modulePulsesData[INTERNAL_MODULE].pxx_uart.pulses;
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
||||
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
|
||||
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
|
||||
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
|
||||
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
|
||||
DMA_Init(INTMODULE_DMA_STREAM, &DMA_InitStructure);
|
||||
|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
EXTMODULE_TIMER->ARR = 44000 ; // 22mS
|
||||
EXTMODULE_TIMER->CCR2 = 40000 ; // Update time
|
||||
EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
|
||||
EXTMODULE_TIMER->CCER = TIM_CCER_CC1NE | TIM_CCER_CC1NP ;
|
||||
EXTMODULE_TIMER->CR2 = TIM_CR2_OIS1 ; // O/P idle high
|
||||
EXTMODULE_TIMER->BDTR = TIM_BDTR_MOE ; // Enable outputs
|
||||
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
|
||||
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0 ; // Force O/P high
|
||||
EXTMODULE_TIMER->EGR = 1 ; // Restart
|
||||
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC1DE ; // Enable DMA on CC1 match
|
||||
EXTMODULE_TIMER->DCR = 13 ; // DMA to CC1
|
||||
|
||||
// Enable the DMA channel here, DMA1 stream 5, channel 3 (TIM2_CH1)
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
|
||||
DMA1_Stream5->CR = DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1 | DMA_SxCR_PL_0 | DMA_SxCR_MSIZE_0
|
||||
| DMA_SxCR_PSIZE_0 | DMA_SxCR_MINC | DMA_SxCR_DIR_0 | DMA_SxCR_PFCTRL ;
|
||||
DMA1_Stream5->PAR = CONVERT_PTR_UINT(&EXTMODULE_TIMER->DMAR);
|
||||
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
|
||||
// DMA1_Stream5->FCR = 0x05 ; //DMA_SxFCR_DMDIS | DMA_SxFCR_FTH_0 ;
|
||||
// DMA1_Stream5->NDTR = 100 ;
|
||||
DMA1_Stream5->CR |= DMA_SxCR_EN ; // Enable DMA
|
||||
|
||||
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0 ; // Toggle CC1 o/p
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable this interrupt
|
||||
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
|
||||
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
|
||||
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
||||
}
|
||||
|
||||
static void extmoduleDsm2Stop()
|
||||
{
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
||||
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ;
|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
||||
EXTERNAL_MODULE_OFF();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
static void extmodulePpmStart()
|
||||
{
|
||||
EXTERNAL_MODULE_ON();
|
||||
|
||||
GPIO_PinAFConfig(EXTMODULE_PPM_GPIO, EXTMODULE_PPM_GPIO_PinSource, EXTMODULE_PPM_GPIO_AF);
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = EXTMODULE_PPM_GPIO_PIN;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
GPIO_Init(EXTMODULE_PPM_GPIO, &GPIO_InitStructure);
|
||||
|
||||
// PPM generation principle:
|
||||
//
|
||||
// Hardware timer in PWM mode is used for PPM generation
|
||||
// Output is OFF if CNT<CCR1(delay) and ON if bigger
|
||||
// CCR1 register defines duration of pulse length and is constant
|
||||
// AAR register defines duration of each pulse, it is
|
||||
// updated after every pulse in Update interrupt handler.
|
||||
// CCR2 register defines duration of no pulses (time between two pulse trains)
|
||||
// it is calculated every round to have PPM period constant.
|
||||
// CC2 interrupt is then used to setup new PPM values for the
|
||||
// next PPM pulses train.
|
||||
// stop timer
|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
|
||||
// setupPulsesPPM() is also configuring registers,
|
||||
// so it has to be called after the peripheral is enabled
|
||||
setupPulsesPPM(EXTERNAL_MODULE) ;
|
||||
|
||||
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
|
||||
EXTMODULE_TIMER->PSC = EXTMODULE_TIMER_FREQ / 2000000 - 1 ; // 0.5uS (2Mhz)
|
||||
|
||||
// CH1 PWM mode 1, CH1 out is OFF if CNT<CCR1(delay) and ON if bigger (up to AAR,which is pulse length)
|
||||
EXTMODULE_TIMER->CCMR1 = TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC2PE; // PWM mode 1
|
||||
|
||||
// Reloads register vales now
|
||||
EXTMODULE_TIMER->EGR = 1 ;
|
||||
|
||||
// Update DMA request enabled. WHY?????
|
||||
EXTMODULE_TIMER->DIER = TIM_DIER_UDE ;
|
||||
|
||||
// clear interrupt flags and enable Update and
|
||||
// CC2 interrupts (this one is enabled now to trigger pulse setup)
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ;
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ;
|
||||
|
||||
// enable timer and global interrupts
|
||||
EXTMODULE_TIMER->CR1 |= TIM_CR1_CEN ;
|
||||
NVIC_EnableIRQ(EXTMODULE_TIMER_IRQn) ;
|
||||
NVIC_SetPriority(EXTMODULE_TIMER_IRQn, 7);
|
||||
}
|
||||
|
||||
static void extmodulePpmStop()
|
||||
{
|
||||
NVIC_DisableIRQ(EXTMODULE_TIMER_IRQn) ;
|
||||
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE & ~TIM_DIER_UIE ;
|
||||
EXTMODULE_TIMER->CR1 &= ~TIM_CR1_CEN ;
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF & ~TIM_SR_UIF; // Clear all flags
|
||||
if (!IS_TRAINER_EXTERNAL_MODULE()) {
|
||||
EXTERNAL_MODULE_OFF();
|
||||
}
|
||||
}
|
||||
|
||||
extern "C" void TIM2_IRQHandler()
|
||||
{
|
||||
DEBUG_INTERRUPT(INT_TIM2);
|
||||
//determine if its CC or UP interrupt
|
||||
uint16_t sr = EXTMODULE_TIMER->SR;
|
||||
uint16_t dier = EXTMODULE_TIMER->DIER;
|
||||
|
||||
if (sr & TIM_SR_CC2IF && dier & TIM_DIER_CC2IE) { // Capture/Compare 2 interrupt enabled and fired
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear flag
|
||||
|
||||
setupPulses(EXTERNAL_MODULE);
|
||||
|
||||
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PXX) {
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
|
||||
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].pxx.pulses[1]);
|
||||
DMA1_Stream5->CR |= DMA_SxCR_EN ; // Enable DMA
|
||||
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].pxx.pulses[0];
|
||||
}
|
||||
#if defined(DSM2)
|
||||
else if (s_current_protocol[EXTERNAL_MODULE] >= PROTO_DSM2_LP45 && s_current_protocol[EXTERNAL_MODULE] <= PROTO_DSM2_DSMX) {
|
||||
DMA1_Stream5->CR &= ~DMA_SxCR_EN ; // Disable DMA
|
||||
DMA1->HIFCR = DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5 ; // Write ones to clear bits
|
||||
DMA1_Stream5->M0AR = CONVERT_PTR_UINT(&modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[1]);
|
||||
DMA1_Stream5->CR |= DMA_SxCR_EN ; // Enable DMA
|
||||
EXTMODULE_TIMER->CCR1 = modulePulsesData[EXTERNAL_MODULE].dsm2.pulses[0];
|
||||
}
|
||||
#endif
|
||||
else if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
|
||||
// Stop CC2 interrupt, the pulse train period ended
|
||||
// the new PPM values were set, we begin new pulse train
|
||||
// generation with Update interrupt
|
||||
EXTMODULE_TIMER->DIER &= ~TIM_DIER_CC2IE ; // stop CC2 interrupt
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_UDE ;
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear Update interrupt flag
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_UIE ; // Enable Update interrupt
|
||||
}
|
||||
DMA_Cmd(INTMODULE_DMA_STREAM, ENABLE);
|
||||
USART_DMACmd(INTMODULE_USART, USART_DMAReq_Tx, ENABLE);
|
||||
}
|
||||
|
||||
if (sr & TIM_SR_UIF && dier & TIM_DIER_UIE) { // Update interrupt enabled and fired
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_UIF ; // Clear flag
|
||||
if (s_current_protocol[EXTERNAL_MODULE] == PROTO_PPM) {
|
||||
EXTMODULE_TIMER->ARR = *modulePulsesData[EXTERNAL_MODULE].ppm.ptr++ ;
|
||||
if (*modulePulsesData[EXTERNAL_MODULE].ppm.ptr == 0) {
|
||||
// we reached the end of PPM pulses
|
||||
// enable CC2 interrupt (which comes before Update in any case)
|
||||
// to start new PPM cycle and setup pulses
|
||||
EXTMODULE_TIMER->SR &= ~TIM_SR_CC2IF ; // Clear CC1 flag
|
||||
EXTMODULE_TIMER->DIER |= TIM_DIER_CC2IE ; // Enable CC1 interrupt
|
||||
}
|
||||
}
|
||||
}
|
||||
INTMODULE_TIMER->DIER |= TIM_DIER_CC2IE;
|
||||
DEBUG_TIMER_STOP(debugTimerIntPulsesDuration);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user